NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM 184pin One Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 16Mx8 SDRAM Features • 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module • 16Mx64 Double Data Rate (DDR) SDRAM DIMM (16M X 8 SDRA MS) • Performance : Speed Sort PC1600 - 8B DIMM CAS Latency 2 2.5 2 100 10 133 7.5 133 7.5 f CK Clock Frequency t CK Clock Cycle PC2100 - 75B - 7K • Data is read or written on both clock edges • DRAM DLL aligns DQ and DQS transitions with clock transitions. Also aligns QFC transitions with clock during Read cycles • Address and control signals are fully synchronous to positive clock edge • Programmable Operation: - DIMM CAS Latency: 2, 2.5 - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write • Auto Refresh (CBR) and Self Refresh Modes • Automatic and controlled precharge commands • 12/10/2 Addressing (row/column/bank) • 15.6 µs Max. Average Periodic Refresh Interval • Serial Presence Detect • Gold contacts • SDRAMs in 66-pin TSOP Type II Package Unit MHz ns f DQ DQ Burst Frequency 200 266 266 MHz • Intended for 100 MHz and 133 MHz applications • Inputs and outputs are SSTL-2 compatible • V DD = 2.5Volt ±?0.2, V DD = 2.5Volt ± 0.2 • Single Pulsed RAS interface • SDRAMs have 4 internal banks for concurrent operation • Module has one physical bank • Differential clock inputs Description NT128D64S88A0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank high-speed memory array. The 16Mx64 module is a single-bank DIMM that uses eight 16Mx8 DDR SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all devices on the DIMM. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The last 128 bytes are available to the customer. All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint. Ordering Information Part Number NT128D64S88A0G-7K Speed 143MHz (7ns @ CL = 2.5 ) Organization Leads Power 16Mx64 Gold 2.5V PC2100 133MHz (7.5ns @ CL= 2 ) NT128D64S88A0G –75B 133MHz (7.5ns @ CL= 2.5 ) PC2100 100MHz (10ns @ CL = 2 ) NT128D64S88A0G –8B REV1.0 / June 2001 125MHz (8ns @ CL = 2.5 ) PC1600 100MHz (10ns @ CL = 2 ) 1 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Pin Description CK0, CK1, CK2 CK0 , CK1 , CK2 CKE0 Differential Clock Inputs DQ0-DQ63 Data input/output Clock Enable RAS Row Address Strobe DQS0-DQS7, DQS9-DQS16 Bidirectional data strobes CAS WE Column Address Strobe Write Enable VDD V DDQ Power (2.5V) Supply voltage for DQs(2.5V) S0 Chip Selects V SS Ground A0-A9, A11 A10/AP Address Inputs Address Input/Autoprecharge NC SCL No Connect Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output V REF Ref. Voltage for SSTL_2 inputs V DD Identification flag. (Not used when V DD =V DDQ) SA0-2 Serial Presence Detect Address Inputs V DDSPD Serial EEPROM positive power supply(2.5V) V DDID Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 V REF 93 V SS 32 A5 124 V SS 62 V DDQ 154 RAS 2 3 DQ0 V SS 94 95 DQ4 DQ5 33 34 DQ24 V SS 125 126 A6 DQ28 63 64 WE DQ41 155 156 DQ45 V DDQ 4 DQ1 96 V DDQ 35 DQ25 127 DQ29 65 CAS 157 S0 5 6 DQS0 DQ2 97 98 DQS9 DQ6 36 37 DQS3 A4 128 129 V DDQ DQS12 66 67 V SS DQS5 158 159 NC DQS14 7 V DD 99 DQ7 38 V DD 130 A3 68 DQ42 160 V SS 8 9 DQ3 NC 100 101 V SS NC 39 40 DQ26 DQ27 131 132 DQ30 V SS 69 70 DQ43 V DD 161 162 DQ46 DQ47 10 NC 102 NC 41 A2 133 DQ31 71 NC 163 NC 11 12 V SS DQ8 103 104 NC V DDQ 42 43 V SS A1 134 135 NC NC 72 73 DQ48 DQ49 164 165 V DDQ DQ52 13 DQ9 105 DQ12 44 NC 136 V DDQ 74 V SS 166 DQ53 14 15 DQS1 V DDQ 106 107 DQ13 DQS10 45 46 NC V DD 137 138 CK0 CK0 75 76 CK2 CK2 167 168 NC V DD 16 CK1 108 V DD 47 NC 139 V SS 77 V DDQ 169 DQS15 17 18 CK1 V SS 109 110 DQ14 DQ15 48 49 A0 NC 140 141 NC A10 78 79 DQS6 DQ50 170 171 DQ54 DQ55 19 DQ10 111 NC 50 V SS 142 NC 80 DQ51 172 V DDQ 20 21 DQ11 CKE0 112 113 V DDQ NC 51 52 NC BA1 143 144 V DDQ NC 81 82 V SS V DDID 173 174 NC DQ60 22 V DDQ 114 DQ20 83 DQ56 175 DQ61 23 24 DQ16 DQ17 115 116 NC V SS 53 54 DQ32 V DDQ 145 146 V SS DQ36 84 85 DQ57 V DD 176 177 V SS DQS16 25 DQS2 117 DQ21 55 DQ33 147 DQ37 86 DQS7 178 DQ62 26 27 V SS A9 118 119 A11 DQS11 56 57 DQS4 DQ34 148 149 V DD DQS13 87 88 DQ58 DQ59 179 180 DQ63 V DDQ 28 DQ18 120 V DD 58 V SS 150 DQ38 89 V SS 181 SA0 29 30 A7 V DDQ 121 122 DQ22 A8 59 60 BA0 DQ35 151 152 DQ39 V SS 90 91 NC SDA 182 183 SA1 SA2 DQ44 92 SCL 184 V DDSPD KEY KEY 31 DQ19 123 DQ23 61 DQ40 153 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV1.0 / June 2001 2 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Input/Output Functional Description Symbol Type Function Polarity CK0 , CK1, CK2 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to the Positive on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising Edge edge of their associated clocks. CK0 , CK1 , CK2 (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to the Edge on-DIMM PLL. CKE0 (SSTL) S0 (SSTL) RAS , CAS , WE (SSTL) V REF Supply V DDQ Supply BA0, BA1 (SSTL) Activates the SDRAM CK signal when high and deactivates the CK signal when low. By Active High deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command Active decoder when high. When the command decoder is disabled, new commands are ignored Low but previous operations continue. Active When sampled at the positive rising edge of the clock, RAS , CAS , WE define the Low operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - A0 - A9 A10/AP A11 (SSTL) - DQ0 - DQ63, (SSTL) - DQS0 - DQS7 DQS9 - DQS16 (SSTL) V DD , V SS Supply - SDA - SCL - REV1.0 / June 2001 Supply During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Active Data strobes: Output with read data, input with write data. Edge aligned with read data, High centered on write data. Used to capture write data. SA0 – SA2 V DDSPD Selects which SDRAM bank is to be active. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply. 3 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Functional Block Diagram ( 1 Bank, 16Mx8 DDR SDRAMs ) S0 DQS0 DQS9 DQS4 DQS13 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQS1 DQS10 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS D4 DQS5 DQS14 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DQS2 DQS11 DQS D5 DQS6 DQS15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQS3 DQS12 DQS D6 DQS7 DQS16 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 BA0 - BA1 : SDRAMs D0 -D7 A0-A11 RAS : SDRAMs D0 -D7 CAS CAS : SDRAMs D0 -D7 CKE0 Serial PD A0 A1 A2 SA0 SA1 SA2 SDRAM x 2 120 ohm SDRAM x 3 120 ohm SDRAM x 3 CK2 WE : SDRAMs D0 -D7 SCL WP 120 ohm CK1 CK2 CKE0 : SDRAMs D0 -D7 WE D7 CK0 CK1 A0 - A11 : SDRAMs D0 -D7 RAS DQS CK0 CS : SDRAMs D0 -D7 S0 BA0-BA1 Notes : 1. 2. 3. 4. DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VDDQ VDD VREF VSS VDDID SDA D0 D0 D0 D0 - D7 D7 D7 D7 Strap: see Note 4 DQ-to-I/O wring may be changed within a byte. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22 Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV1.0 / June 2001 4 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Serial Presence Detect -- Part 1 of 2 16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD Byte Description SPD Entry Value DDR266A DDR266B DDR200 -7K -75B -8B Serial PD Data Entry (Hexadecimal) Note DDR266A DDR266B DDR200 -7K -75 -8B 0 Number of Serial PD Bytes Written during Production 128 80 1 2 Total Number of Bytes in Serial PD device Fundamental Memory Type 256 DDR SDRAM 08 07 3 Number of Row Addresses on Assembly 12 0C 4 5 Number of Column Addresses on Assembly Number of DIMM Bank 10 1 0A 01 6. Data Width of Assembly X64 40 7 8 Data Width of Assembly (cont’) Voltage Interface Level of this Assembly X64 SSTL 2.5V 00 04 9 DDR SDRAM Device Cycle Time at CL=2.5 11 DDR SDRAM Device Access Time from Clock at CL=2.5 DIMM Configuration Type 12 Refresh Rate/Type 13 14 Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width 15 DDR SDRAM Device Attr: Min CLk Delay, Random Col Access 10 16 17 7ns 7.5ns 8ns 70 75 80 0.75ns 0.75ns 0.8ns 75 75 80 Non-Parity 00 SR/1x(15.625us) 80 X8 N/A 08 00 1 Clock 01 2,4,8 0E 4 04 DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks 18 DDR SDRAM Device Attributes: CAS Latencies Supported 19 20 DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency 21 DDR SDRAM Device Attributes: 22 23 DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2 +/-0.2V Voltage Tolerance 7.5ns 10ns 10ns 75 00 A0 A0 24 Maximum Data Access Time from Clock at CL=2 0.75ns 75 75 80 25 26 27 Minimum Row Precharge Time(tRP) 29 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density Address and Command Setup Time Before Clock 32 2/2.5 2/2.5 0C 0C 0 1 01 02 Differential Clock 20 0.75ns Minimum Clock Cycle Time at CL=1 Maximum Data Access Time from Clock at CL=1 Minimum Row Active to Row Active delay (tRRD ) Minimum RAS to CAS delay (tRCD ) 28 2/2.5 0.8ns N/A 00 N/A 00 0C 20ns 20ns 20ns 50 50 50 15ns 15ns 15ns 3C 3C 3C 20ns 20ns 20ns 50 50 50 45ns 45ns 50ns 2D 2D 32 128MB 20 0.9ns 0.9ns 1.1ns 90 90 B0 33 Address and Command Hold Time After Clock 0.9ns 0.9ns 1.1ns 90 90 B0 34 35 Data Input Setup Time Before Clock Data Input Hold Time After Clock 0.5ns 0.5ns 0.5ns 0.5ns 0.6ns 0.6ns 50 50 50 50 60 60 Initial 00 6C 36-61 62 63 Reserved SPD Revision Checksum Data REV1.0 / June 2001 Undefined Initial Initial 00 00 9C 00 22 5 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Serial Presence Detect -- Part 2 of 2 16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD Byte Description SPD Entry Value DDR266A DDR266B DDR200 -7K -75B -8B 64-71 Manufacturer’s JEDED ID Code 0B Hex bank3 72 73-90 Module Manufacturing Location Module Part number N/A N/A 91-92 Module Revision Code 93-94 95-98 Module Manufacturing Data Module Serial Number 99-255 Reserved 1. 2. N/A Serial PD Data Entry (Hexadecimal) DDR266A DDR266B DDR200 Note -7K -75 -8B 7F7F7F0B00000000 N/A 00 00 00 N/A 00 Year/Week Code Serial Number yy/ww 00 Undefined 00 00 1,2 yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) REV1.0 / June 2001 6 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Absolute Maximum Ratings Symbol V IN , V OUT Parameter Voltage on I/O pins relative to Vss Rating Units -0.5 to VDDQ+0.5 V V IN Voltage on Input relative to Vss -0.5 to +3.6 V V DD Voltage on VDD supply relative to Vss -0.5 to +3.6 V Voltage on VDDQ supply relative to Vss -0.5 to +3.6 V 0 to+70 °C -55 to +150 °C TBD W 50 mA V DDQ TA TSTG PD IOUT Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Symbol Max. Units Notes Input Capacitance: CK0, CK0 , CK1, CK1 , CK2, CK2 CI1 12 pF 1 Input Capacitance: A0-A11, BA0, BA1, WE , RAS , CAS , CKE0, S0 , CI2 30 pF 1 Input Capacitance: SA0-SA2, SCL CI4 9 pF 1 Input/Output Capacitance DQ0-63; DQS0-7, 9-16 CIO1 7 pF 1,2 Parameter CIO3 11 pF Input/Output Capacitance: SDA 1. V DDQ = V DD = 2.5V ± 0.2V, f = 100 MHz, T A = 25 °C, V OUT (DC) = V DDQ/2 , V OUT (Peak to Peak) = 0.2V. 2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV1.0 / June 2001 7 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM DC Electrical Characteristics and Operating Conditions ( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol VDD VDDQ V SS , V SSQ Parameter Min Max Units Notes Supply Voltage 2.3 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 0 0 V Supply Voltage, I/O Supply Voltage I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1,2 I/O Termination Voltage (System) V REF – 0.04 V REF + 0.04 V 1,3 V IH(DC) Input High (Logic1) Voltage V REF + 0.15 V DDQ + 0.3 V 1 V IL(DC) Input Low (Logic0) Voltage -0.3 V REF - 0.15 V 1 V IN(DC) Input Voltage Level, CK and CK Inputs -0.3 V DDQ + 0.3 V 1 V ID(DC) Input Differential Voltage, CK and CK Inputs 0.30 V DDQ + 0.6 V 1,4 -40 40 -5 5 uA 1 -15 15 DQS0-7, 9-16 -5 5 uA 1 SDA -1 1 V REF V TT Address and control inputs II DQ0-63; Input Leakage Current Any input 0V < = V IN < = V DD (All other pins not under test = 0V) DQS0-7, 9-16 CK0, CK0 CK1, CK1 CK2, CK2 DQ0-63; Output Leakage Current IOZ (DQs are disabled; 0V < = V out < = V DDQ IOH Output High Current (V OUT = V DDQ -0.373V, min V REF , min V TT ) -16.8 - mA 1 IOL Output Low Current (V OUT = 0.373, max V REF , max V TT ) 16.8 - mA 1 1. Inputs are not recognized as valid until V REF stabilizes. 2. V REF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on V REF may not exceed 2% of the DC value. 3. V TT is not applied directly to the DIMM. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF , and must track variations in the DC level of V REF . 4. V ID is the magnitude of the difference between the input level on CK and the input level on CK . REV1.0 / June 2001 8 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to V SS . 2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and I DD tests may use a V IL to V IH swing of up to 1.5V in the test environment, but input timing is still referenced to V REF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V IL(AC) and V IH(AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits V TT 50 ohms Output Timing Reference Point V OUT 30 pF AC Operating Conditions ( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Parameter/Condition Min V IH(AC) Input High (Logic 1) Voltage. V IL(AC) Input Low (Logic 0) Voltage. V ID(AC) Input Differential Voltage, CK and CK Inputs V IX(AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Max Unit Notes V 1, 2 V REF ? - 0.31 V 1, 2 V DDQ + 0.6 V 1, 2, 3 V 1, 2, 4 V REF + 0.31 0.62 (0.5*V DDQ ) - 0.2 (0.5*V DDQ ) +?0.2 1. Input slew rate = 1V/ ns . 2. Inputs are not recognized as valid until V REF stabilizes. 3. V ID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. REV1.0 / June 2001 9 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Operating, Standby, and Refresh Currents ( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol Parameter/Condition PC1600 PC2100 Unit Notes I DD0 Operating Current: one bank; active / precharge; t RC =t RC (MIN) ; tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 600 680 mA 1,2 720 880 mA 1,2 120 120 mA 1,2 240 280 mA 1,2 120 120 mA 1,2 400 480 mA 1,2 1040 1320 mA 1,2 920 1200 mA 1,2 1280 1360 mA 1,2 126 126 mA 1,2,4 16 16 mA 1,2,3 I DD1 I DD2P I DD2N I DD3P I DD3N I DD4R I DD4W I DD5 I DD6 Operating Current: one bank; active / read / precharge; Burst = 2; t RC = t RC (MIN) ; CL = 2.5; t CK = t CK (MIN) ;I OUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= V IL (MAX) ; t CK = t CK (MIN) Idle Standby Current: CS >= V IH (MIN) ; all banks idle; CKE >= V IH(MIN) ; t CK = t CK (MIN) ; address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE <= V IL (MAX) ; t CK = t CK (MIN) Active Standby Current: one bank; active / precharge; CS >= V IH (MIN) ; CKE >= V IH (MIN) ; t RC = t RAS (MAX) ; t CK = t CK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; t CK = t CK (MIN) ; I OUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; t CK = t CK (MIN) t RC = t RFC (MIN) Auto-Refresh Current: t RC = 15.625 µs Self-Refresh Current: CKE <= ? 0.2V 1. I DD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns . 3. Enables on-chip refresh and address counters. 4. Current at 15.625 µs is time averaged value of I DD5 at t RFC MIN and I DD2P over 15.625 µs. REV1.0 / June 2001 10 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module ( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2) Symbol -7K Parameter -75B Max. -8B Unit Notes +0.8 ns 1,2,3,4 +0.8 0.55 ns tCK 1,2,3,4 1,2,3,4 0.45 0.55 tCK 1,2,3,4 8 10 12 12 ns ns 1,2,3,4 1,2,3,4 0.6 ns 1,2,3,4 , 18,19 0.5 0.6 ns 1,2,3,4 ,18,19 1.75 2 ns 1,2,3,4 +0.8 ns 1, 2, 3, 4, 5 +0.8 ns 1, 2, 3, 4, 5 0.6 ns 1,2,3,4 0.6 Min. Max. Min. DQ output access time from CK/ CK -0.75 +0.75 -0.75 DQS output access time from CK/ CK CK high-level width -0.75 0.45 +0.75 0.55 -0.75 0.45 tCL CK low -level width 0.45 0.55 tCK tCK Clock cycle time 7 7.5 12 12 tDH DQ and DM input hold time 0.5 0.5 tDS DQ and DM input setup time 0.5 tDIPW DQ and DM input pulse width (each input) 1.75 tHZ Data-out high-impedance time from CK/ CK -0.75 +0.75 -0.75 +0.75 -0.8 tLZ Data-out low -impedance time from CK/ CK -0.75 +0.75 -0.75 +0.75 -0.8 tAC tDQSCK tCH tDQSQ tDQSQA tHP tQH tDQSS tDQSL,H tDSS tDSH tMRD tWPRES CL=2.5 CL=2 DQS-DQ skew (DQS & associated DQ signals) DQS-DQ skew (DQS & all DQ signals) Minimum half clk period for any given cycle; defined by clk high(tCH ) or clk low (tCL ) time Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Min. Max. +0.75 -0.8 +0.75 0.55 -0.8 0.45 0.45 0.55 7.5 10 12 12 0.5 0.5 ns 1,2,3,4 tCH or tCL 0.5 tCH or tCL tCH or tCL tCK 1,2,3,4 tHP 0.75n s tHP 0.75n s tHP 1.0ns tCK 1,2,3,4 tCK 1,2,3,4 0.75 1.25 0.5 0.75 1.25 0.75 1.25 0.35 0.35 0.35 tCK 1,2,3,4 0.2 0.2 0.2 tCK 1,2,3,4 0.2 0.2 0.2 tCK 1,2,3,4 14 15 16 ns 1,2,3,4 0 0 0 ns 1, 2, 3, 4, 7 tCK 1, 2, 3, 4, 6 1,2,3,4 tWPST Write postamble 0.40 tWPRE Write preamble 0.25 0.25 0.25 tCK tIH Address and control input hold time (fast slew rate) 0.9 1.1 1.1 ns tIS Address and control input setup time (fast slew rate) 0.9 1.1 1.1 ns tIH Address and control input hold time (slow slew rate) 1.0 1.1 1.1 ns REV1.0 / June 2001 0.60 0.40 0.60 0.40 0.60 2, 3, 4, 11, 13, 14 2, 3, 4, 11, 13, 14 2, 3, 4, 12, 13, 14, 17 11 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module ( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2) Symbol tIS Parameter Address and control input setup time (slow slewrate) -7K Min. -75B Max. 1.0 Min. -8B Max. 1.0 2.2 tRPRE Read preamble 0.9 1.1 0.9 1.1 tRPST Read postamble 0.40 0.60 0.40 tRAS Active to Precharge command 45 120,000 45 tRFC tRCD tRAP tRP tRRD tWR tDAL tWTR tXSNR Unit Notes ns 2, 3, 4, 12, 13, 14, 17 2, 3, 4, Input pulse width Active to Active/Auto-refresh Max. 1.1 tIPW tRC Min. 2.2 - ns 0.9 1.1 tCK 1,2,3,4 0.60 0.40 0.60 tCK 1,2,3,4 120,000 50 120,000 ns 1,2,3,4 14 65 65 70 ns 1,2,3,4 75 75 80 ns 1,2,3,4 20 20 20 ns 1,2,3,4 20 20 20 ns 1,2,3,4 20 20 20 ns 1,2,3,4 15 15 15 ns 1,2,3,4 15 (tWR / tCK ) + 15 (tWR / tCK ) + ns 1,2,3,4 Auto precharge write recovery + 15 (tWR / tCK ) + precharge time (tRP/ (tRP / (tRP / tCK ) tCK ) tCK ) 1 1 1 tCK 1,2,3,4 75 75 80 ns 1,2,3,4 200 200 200 tCK 1,2,3,4 1, 2, 3, command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Active to Read Command with Autoprecharge Precharge command period Active bank A to Active bank B command Write recovery time Internal write to read command delay Exit self-refresh to non-read command tXSRD Exit self-refresh to read command tREFI Average Periodic Refresh Interval REV1.0 / June 2001 15.6 15.6 1, 2, 3, tCK 15.6 µs 4, 16 4, 8 12 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross: the input reference level for signals other than CK/ CK , is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT . 5. t HZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS . 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. QFC is enabled as soon as possible after the rising CK edge that registers the Write command. 10. QFC is disabled as soon as possible after the last valid DQS edge transitions Low. 11. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL(AC). 12. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 13. CK/ CK slew rates are >= 1.0 V/ns. 14. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 15. The specified timing is guaranteed assuming QFC is connected to a test load consisting of 20 pF to ground and a pull up resistor of 150 ohms to Vddq . 16. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL = 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 17. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate Delta ( tIS ) ? Delta ( tIH ) Unit Note 0.5 V/ns 0 0 ps 1,2 0.4 V/ns +50 0 ps 1,2 0.3 V/ns +100 0 ps 1,2 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice. 18. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate Delta ( tDS ) Delta ( tDH ) Unit Note 0.5 V/ns 0 0 ps 1,2 0.4 V/ns +75 +75 ps 1,2 0.3 V/ns +150 +150 ps 1,2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice. 19. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate Delta ( tDS ) Delta ( tDH ) Unit Note 0.0 ns/V 0 0 ps 1,2,3,4 0.25 ns/V +50 +50 ps 1,2,3,4 0.5 ns/V +100 +100 ps 1,2,3,4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV1.0 / June 2001 13 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM AC Timing for PC2100 - Applicable Specifications Expressed in Clock Cycles ( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) Symbol tMRD tWPRE PC2100 @ CL = 2.5 Parameter Unit Note 2 tCK 1,2,3,4 0.25 tCK 1,2,3,4 tCK 1,2,3,4 Min. Mode register set command cycle time Write preamble Max. tRAS Active to Precharge command 6 tRC Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh 9 tCK 1,2,3,4 10 tCK 1,2,3,4 tRFC command period 16000 tRCD Active to Read or Write delay 3 tCK 1,2,3,4 tRAP Active to Read Command with Autoprecharge 3 tCK 1,2,3,4 tRP Precharge command period 3 tCK 1,2,3,4 tRRD Active bank A to Active bank B command 2 tCK 1,2,3,4 tWR Write recovery time 2 tCK 1,2,3,4,5 tDAL Auto precharge write recovery + precharge time 5 tCK 1, 2, 3,4 tWTR Internal write to read command delay 1 tCK 1, 2, 3,4 tXSNR Exit self-refresh to non-read command 10 tCK 1, 2, 3,4 tXSRD Exit self-refresh to read command 200 tCK 1, 2, 3,4 1. Input slew rate = 1V/ns. 2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross: the input reference level for signals other than CK/ CK , is V REF. 3. Inputs are not recognized as valid until V REF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V TT . 5. tHZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). REV1.0 / June 2001 14 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64S88A0G 128MB : 16M x 64 PC2100 / PC1600 Unbuffered DIMM Package Dimensions D0 REV1.0 / June 2001 D1 D2 D3 D4 D5 D6 D7 15 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.