KK74HC4060A 14 STAGE BINARY COUNTER/OSCILLATOR KK74HC4060A The KK74HC4060A is an high speed CMOS 14-STAGE BINARY COUNTER/OSCILLATOR fabricated with silicon gate C2MOS technology. The oscillator configuration allows design of either RC or crystal oscillator circuits. A high level on the CLEAR accomplishes the reset function, i.e. all counter outputs are made low and the oscillator is disabled. A negative transition on the clock input increments the counter. Ten kinds of divided output are provided; 4 to 10 and 12 to 14 stage inclusive. The maximum division available at Q12 is 1/16384 f oscillator. The Clock Input ( ∅I ) and the CLEAR input are equipped with protection circuits against static discharge and transient excess voltage. o o o o ORDERING INFORMATION KK74HC4060AN Plastic KK74HC4060ADW SOIC TA = -55° to 125° C for all packages . LOW POWER DISSIPATION: ICC =4 µA(MAX.) at TA=25°C SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH = tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2 V to 6 V PIN DESCRIPTION PIN ASSIGNMENT PIN No SYMBOL NAME AND FUNCTION 01, 02, 03 Q12 to Q14 Counter Outputs 07, 05, 04, 06, 14, 13, 15 Q4 to Q10 Counter Outputs 09 ∅O External Capacitor Connection 10 ∅O External Resistor Connection 11 ∅I Clock Input / Oscillator 12 CLEAR Master Reset 08 GND Ground (0V) 16 VCC Positive Supply Voltage CLEAR ∅I ∅O ∅O INPUT AND OUTPUT EQUIVALENT CIRCUIT VCC VCC INPUT OUTPUT GND GND 1 KK74HC4060A TRUTH TABLE ∅I CLEAR FUNCTION H COUNTER IS RESET TO ZERO STATE ∅O OUTPUT GOES TO HIGH LEVEL X ∅O OUTPUT GOES TO LOW LEVEL L COUNT UP ONE STEP L NO CHANGE X : Don’t Care LOGIC DIAGRAM Q4 7 ∅O 10 ∅I 11 ∅O 9 D CK CLEAR Q 12 R CK D D CK R Q R CK D Q R CK D 3 2 1 Q14 Q13 Q12 Q5 5 Q R CK D Q Q R R Q Q R CK D CK D 15 Q10 D CK D CK R Q R CK D 13 Q9 Q D CK R Q R CK D 14 Q8 Q R Q R CK D 6 Q7 Q 4 Q6 This logic diagram has not be used to estimate propagation delays 2 KK74HC4060A ABSOLUTE MAXIMUM RATINGS Symbol VСС Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA DC VCC or Ground Current ± 50 mA ICC or IGND Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VСС Parameter Supply Voltage Value Unit 2 to 6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V TOP Operating Temperature -55 to +125 °C VCC = 2.0 V 0 to 1000 ns VCC = 4.5 V 0 to 500 ns VCC = 6.0 V 0 to 400 ns tr, tf Input Rise and Fall Time 3 KK74HC4060A DC ELECTRICAL CHARACTERISTICS Test Condition Symbol VIH VIL VOH VOL VOH Parameter High Level Input Voltage Low Level Input Voltage ICC -55°C to 125°C Min 2.0 1.5 1.5 4.5 3.15 3.15 6.0 4.2 4.2 Max Min Unit Max V 2.0 0.5 0.5 4.5 1.35 1.35 6.0 1.8 1.8 V IO = -20 µA 1.9 1.9 4.5 IO = -20 µA 4.4 4.4 6.0 IO = -20 µA 5.9 5.9 4.5 IO= -4.0 µA 4.18 4.10 6.0 IO = -5.2 µA 5.68 5.60 2.0 IO = 20 µA 0.1 0.1 4.5 IO = 20 µA 0.1 0.1 6.0 IO = 20 µA 0.1 0.1 4.5 IO= 4.0 µA 0.26 0.40 6.0 IO= 5.2 µA 0.26 0.40 2.0 IO = -20 µA 1.8 1.8 4.5 IO = -20 µA 4.4 4.0 6.0 IO = -20 µA 5.5 5.5 2.0 IO = 20 µA 0.2 0.2 4.5 IO = 20 µA 0.5 0.5 6.0 IO = 20 µA 0.5 0.5 Input Leakage Current 6.0 VI = VCC or GND ±0.1 ±1 µA Quiescent Supply Current 6.0 V I= VCC or GND 4 80 µA Low Level Output Voltage (Q Output) High Level Output Voltage Low Level Output Voltage (∅O, ∅O Output) II TA = 25°C VCC (V) 2.0 High Level Output Voltage (Q Output) (∅O, ∅O Output) VOL Value V V V V 4 KK74HC4060A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Test Condition Symbol Parameter tTLH, tTHL Output Transition Time tPHL fMAX tW(H), tW(L) tW(H) tREM TA = 25°C VCC (V) Min -55°C to 125°C Max Min 75 110 4.5 15 22 6.0 13 19 2.0 300 450 4.5 60 90 6.0 51 76 Propagation Delay Time Difference (Qn – Qn+1) 2.0 75 110 4.5 15 22 6.0 13 19 Propagation Delay Time (CLEAR – Qn) 2.0 195 295 4.5 39 59 6.0 33 50 Maximum Clock Frequency 2.0 6 4 4.5 30 20 6.0 35 24 Minimum Pulse Width ( ∅I ) Minimum Pulse Width (CLEAR) Minimum Removal Time Unit Max 2.0 tPLH, tPHL Propagation Delay Time ( ∅I-Q4 ) tPD Value ns ns ns ns MHz 2.0 75 110 4.5 15 22 6.0 13 19 2.0 75 110 4.5 15 22 6.0 13 19 2.0 100 150 4.5 20 30 6.0 17 26 ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol CIN Parameter Input Capacitance VCC (V) 5.0 Value TA = 25°C Min Max 10 -55°C to 125°C Min Unit Max 10 pF 5 KK74HC4060A TEST CIRCUIT VCC PULSE GENERATOR D.U.T. CL RT CL = 50 pF or equivalent (includes jig and probe capacitance) RL = ZOUT of pulse generator (typically 50 Ω) WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH ( ∅I ) (f=1MHz; 50% duty cycle) 6ns 6ns ∅I VCC 90% 50% 10% 50% tW GND tW VOH Q4 50% 50% tPLH tPHL VOL WAVEFORM 2 : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CLEAR) (f=1MHz; 50% duty cycle) 6ns 6ns VCC 90% CLEAR 50% 10% GND tW VOH 50% QN tPHL VOL 6 KK74HC4060A WAVEFORM 3 :PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) tTHL VOH 90% 50% QN 10% VOL tTLH 90% QN+1 VOH 50% 10% tPLH VOL WAVEFORM 4 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) tTHL VOH 90% QN 50% 10% VOL tTHL 90% QN+1 VOH 50% 10% tPHL VOL 7 KK74HC4060A N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 9 16 B 1 8 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G K D M H J 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 H B 1 G P 8 R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M F M Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.72 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 NOTES: 8