TENTATIVE TOSHIBA Bi-CMOS Integrated Circuit TB62778FNG Silicon Monolithic TB62778FNG 8-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation The TB62778FNG is comprised of constant-current drivers designed for LEDs and LED panel displays. The regulated current sources are designed to provide a constant current, which is adjustable through one external resistor. The TB62778FNG incorporates eight channels of shift registers, latches, AND gates and constant-current outputs. Fabricated using the Bi-CMOS process, the TB62778FNG satisfies the system requirement of high-speed data transmission. The TB62778FNG is RoHS. Weight: 0.07 g (typ.) Features • Power supply voltages: VDD = 3.3 V/5 V • Output drive capability and output count: 50 mA × 8 channels • Constant-current output range: 5 to 40 mA • Voltage applied to constant-current output terminals: 0.4 V (IOUT = 5 to 40 mA) • Current adjustment (via 7-bit serial data): The MSB, or the HC bit, selects the output current range: 25% to 50% range when HC = 0 or 50% to 100% range when HC = 1 The six LSB bits are used to adjust the current in 64 steps within the selected range. • Designed for common-anode LEDs • Thermal shutdown (TSD) • Power on reset (POR) • Output-open detection (OOD) and output-short detection (OSD) • Input signal voltage level: 3.3-V and 5-V CMOS interfaces (Schmitt trigger input) • Maximum output voltage: 25V • Serial data transfer rate: 25 MHz (max) @cascade connection • Operating temperature range: Topr = −40 to 85°C • Package: SSOP-P-225-0.65B • Constant-current accuracy Output Voltage Current accuracy Between Channels Current Accuracy Between ICs Output Current 0.4 V to 4 V ±3% ±6% 15 mA 1 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Pin Assignment (top view) GND SERIAL-IN CLOCK LATCH VDD R-EXT SERIAL-OUT ENABLE OUT7 OUT6 OUT5 OUT4 OUT0 OUT1 OUT2 OUT3 Block Diagram OUT1 OUT0 R-EXT OUT7 I-REG Error detection TSD VDD POR ENABLE Q Q Q ST R D ST R D ST R D GND LATCH Special mode D0 SERIAL-IN Q0 Q1 Q7 8-bit shift register D0 to D7 R CLOCK D Q SERIAL-OUT CK R Truth Table CLOCK Note 1: LATCH ENABLE SERIAL-IN OUT0 … OUT5 … OUT7 SERIAL-OUT H L Dn Dn … Dn − 5 … Dn − 7 No change L L Dn + 1 No Change No change H L Dn + 2 Dn + 2 … Dn − 3 … Dn − 5 No change X H Dn + 3 OFF No change X H Dn + 3 OFF Dn −4 OUT0 to OUT7 = On when Dn = H; OUT0 to OUT7 = Off when Dn = L. 2 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Timing Diagram n=0 1 2 3 4 5 6 7 H CLOCK L H SERIAL-IN L H LATCH L H ENABLE L ON OUT0 OFF ON OUT1 OFF ON OUT2 OFF ON OUT7 OFF H Data applied when n = 0 SERIAL-OUT L Note 1: Latches are level-sensitive, not edge-triggered. Note 2: The TB62778FNG can be used at 3.3 V or 5.0 V. However, the VDD supply voltage must be equal to the input voltage. Note 3: Serial data is shifted out of SERIAL-OUT on the falling edge of CLOCK. Note 4: The latches hold data while the LATCH terminal is held Low. When the LATCH terminal is High, the latches do not hold data and pass it transparently. When the ENABLE terminal is Low, OUT0 to OUT7 toggle between ON and OFF according to the data. When the ENABLE terminal is High, OUT0 to OUT7 are forced OFF. 3 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Terminal Description Pin No. Pin Name Function 1 GND 2 SERIAL-IN Serial data input terminal 3 CLOCK Serial clock input terminal 4 LATCH 5 OUT0 Constant-current output terminal 6 OUT1 Constant-current output terminal 7 OUT2 Constant-current output terminal 8 OUT3 Constant-current output terminal 9 OUT4 Constant-current output terminal 10 OUT5 Constant-current output terminal 11 OUT6 Constant-current output terminal 12 OUT7 Constant-current output terminal 13 ENABLE 14 SERIAL-OUT 15 R-EXT 16 VDD GND terminal Latch input terminal Output enable input terminal All outputs ( OUT0 to OUT7 ) are disabled when the ENABLE terminal is driven High, and enabled when it is driven Low. Serial data output terminal. Serial data is clocked out on the falling edge of CLOCK. An external resistor is connected between this terminal and ground. OUT0 to OUT7 are adjusted to the same current value. Power supply terminal Equivalent Circuits for Inputs and Outputs 1. ENABLE Terminal VDD 2. LATCH Terminal R (UP) VDD ENABLE LATCH GND GND 3. CLOCK and SERIAL-IN Terminals 4. SERIAL-OUT Terminal VDD VDD CLOCK, SERIAL-IN SERIAL-OUT GND GND 5. R (DOWN) OUT0 to OUT7 Terminals OUT0 to OUT7 GND 4 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Supply voltage VDD 6.0 V Input voltage VIN Output current IOUT Output voltage VOUT Power dissipation Thermal resistance −0.3 to VDD + 0.3 (Note 1) 55 Pd V mA/ch 0.3 to 25 V 1.02 (Notes 2 and 3) W Rth (j-a) 122 Operating temperature range Topr −40 to 85 °C Storage temperature range Tstg −55 to 150 °C Tj 150 °C Maximum junction temperature (Note 2) °C/W Note 1: However, do not exceed 6.0 V. Note 2: When mounted on a PCB (76.2 × 114.3 × 1.6 mm; Cu = 30%; 35-µm-thick; SEMI-compliant) Note 3: Power dissipation is reduced by 1/Rth (j-a) for each °C above 25°C ambient. Operating Ranges (unless otherwise specified, Ta = −40°C to 85°C) Characteristics Symbol Test Condition Min Typ. Max Unit Supply voltage VDD ⎯ 3 ⎯ 5.5 V Output voltage VOUT OUT0 to OUT 7 0.4 ⎯ 4 V IOUT OUT0 to OUT 7 5 ⎯ 40 mA/ch IOH SERIAL-OUT ⎯ ⎯ −5 IOL SERIAL-OUT ⎯ ⎯ 5 0.7 × VDD ⎯ VDD GND ⎯ 0.3 × VDD ⎯ ⎯ 25 Output current VIH Input voltage VIL SERIAL-IN/CLOCK/ LATCH / ENABLE Clock frequency fCLK LATCH pulse width twLAT (Note 2) 20 ⎯ ⎯ CLOCK pulse width twCLK (Note 2) 20 ⎯ ⎯ (Note 2) 2 ⎯ ⎯ twENA IOUT ≥ 20 mA ENABLE pulse width 5 mA ≤ IOUT ≤ 20 mA (Note 2) 3 ⎯ ⎯ tSETUP1 5 ⎯ ⎯ tSETUP2 5 ⎯ ⎯ tSETUP3 5 ⎯ ⎯ 5 ⎯ ⎯ tHOLD1 5 ⎯ ⎯ tHOLD2 5 ⎯ ⎯ tHOLD3 10 ⎯ ⎯ tHOLD4 10 ⎯ ⎯ ⎯ ⎯ 5 ⎯ ⎯ 5 Setup time Cascade connection mA tSETUP4 Hold time Maximum clock rise time Maximum clock fall time tr (Note 2) Single operation tf (Notes 1 and 2) V MHz ns µs ns µs Note 1: For cascade operation, the CLOCK waveform might become ambiguous, causing the tr and tf values to be large. Then it may not be possible to meet the timing requirement for data transfer. Please consider the timing carefully. Note 2: Please see the timing waveform on page 13. 5 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5 V) Symbol Test Circuit IOUT1 5 Output current error between ICs ∆IOUT1 Output current error between channels Min Typ. Max Unit VOUT = 0.4 V, R-EXT = 1.2 kΩ VDD = 5 V, VG = 1 ― 15 ― mA 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 5 V, VG = 1 ― ±3 ±6 ％ ∆IOUT2 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 5 V, VG = 1 ⎯ ±1 ±3 % IOZ 5 VOUT = 25 V ⎯ ⎯ 1 µA VIH ⎯ SERIAL-IN/CLOCK/ LATCH / 0.7 × VDD ⎯ VDD VIL ⎯ SERIAL-IN/CLOCK/ LATCH / GND ⎯ 0.3 × VDD IIH 2 VIN = VDD CLOCK/SERIAL-IN/ ENABLE ― ― 1 IIL 3 VIN = GND CLOCK/SERIAL-IN/ LATCH ― ― −1 VOL 1 IOL = 5.0 mA, VDD = 5 V ⎯ ⎯ 0.3 VOH 1 IOH = −5.0 mA, VDD = 5 V 4.7 ⎯ ⎯ OOD detection voltage VOOD 7 5 to 40 mA 0.2 0.3 0.4 V OSD detection voltage VOSD 7 5 to 40 mA 0.9 × VDD 0.95 × VDD VDD V Changes in constant output current dependent on VDD %/VDD 5 VDD = 3 V to 5.5 V ⎯ 1 2 % Pull-up resistor R (Up) 3 ENABLE 160 200 240 kΩ R (Down) 2 LATCH 160 200 240 kΩ IDD (OFF) 1 4 R-EXT = OPEN, VOUT = 25.0 V ⎯ ⎯ 1 IDD (OFF) 2 4 R-EXT = 1.2 kΩ, VOUT = 25.0 V, All channels OFF ⎯ ⎯ 5 IDD (ON) 4 R-EXT = 1.2 kΩ, VOUT = 0.4 V, All channels ON ⎯ ⎯ 9 Characteristics Output current Output leakage current Test Condition ENABLE Input voltage V Input current ENABLE µA SERIAL-OUT output voltage Pull-down resistor Supply current V 6 mA (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5V) Characteristics Propagation delay time Symbol Test Circuit tpLH1 6 tpLH2 6 tpLH3 6 LATCH = “H” tpLH 6 CLK-SERIAL OUT tpHL1 6 Test Condition (Note 1) CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH − OUTn , ENABLE = “L” ENABLE − OUTn , CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH − OUTn , Min Typ. Max ⎯ 20 300 ⎯ 20 300 ⎯ 20 300 2 10 14 ⎯ 30 340 ns ⎯ 70 340 ⎯ 70 340 CLK-SERIAL OUT 2 10 14 6 10% to 90% points of OUT0 to OUT7 voltage waveforms ― 20 150 6 90% to 10% points of OUT0 to OUT7 voltage waveforms ― 125 300 tpHL2 6 tpHL3 6 LATCH = “H” tpHL 6 Output rise time tor Output fall time tof ENABLE = “L” ENABLE − OUTn , Unit Note 1: Topr = 25°C, VDD = VIH = 5 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15mA, VL = 5.0 V, CL = 10.5pF (see test circuit 6.) 7 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V) Symbol Test Circuit IOUT1 5 Output current error between ICs ∆IOUT1 Output current error between channels Characteristics Output current Output leakage current Test Condition Min Typ. Max Unit VOUT = 0.4 V, R-EXT = 1.2 kΩ VDD = 3.3 V, VG = 1 ― 15 ― mA 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 3.3 V, VG = 1 ― ±3 ±6 % ∆IOUT2 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 3.3 V, VG = 1 ⎯ ±1 ±3 % IOZ 5 VOUT = 25 V ⎯ ⎯ 1 µA VIH ⎯ SERIAL-IN/CLOCK/ LATCH / 0.7 × VDD ⎯ VDD VIL ⎯ SERIAL-IN/CLOCK/ LATCH / GND ⎯ 0.3 × VDD IIH 2 ― ― 1 ENABLE Input voltage V ENABLE VIN = VDD CLOCK/SERIAL-IN/ LATCH / ENABLE Input current IIL 3 VIN = GND CLOCK/SERIAL-IN/ LATCH / µA ― ― −1 ENABLE VOL 1 IOL = 5.0 mA, VDD = 3.3 V ⎯ ⎯ 0.3 VOH 1 IOH = −5.0 mA, VDD = 3.3 V 3.0 ⎯ ⎯ OOD detection voltage VOOD 7 5 to 40 mA 0.2 0.3 0.4 V OSD detection voltage VOSD 7 5 to 40 mA 0.9 × VDD 0.95 × VDD VDD V Changes in constant output current dependent on VDD %/VDD 5 VDD = 3 V to 5.5 V ⎯ 1 2 % V SERIAL-OUT output voltage Pull-up resistor Pull-down resistor Supply current R (Up) 3 ENABLE 160 200 240 kΩ R (Down) 2 LATCH 160 200 240 kΩ IDD (OFF) 1 4 R-EXT = OPEN, VOUT = 25.0 V ⎯ ⎯ 1 IDD (OFF) 2 4 R-EXT = 1.2 kΩ, VOUT = 25.0 V, All channels OFF ⎯ ⎯ 5 IDD (ON) 4 R-EXT = 1.2 kΩ, VOUT = 0.4 V, All channels ON ⎯ ⎯ 9 8 mA (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V) Characteristics Propagation delay time Symbol Test Circuit tpLH1 6 tpLH2 6 tpLH3 6 LATCH = “H” tpLH 6 CLK-SERIAL OUT tpHL1 6 Test Condition (Note 1) CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH - OUTn , ENABLE = “L” ENABLE - OUTn , CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH - OUTn , Min Typ. Max ⎯ ⎯ 300 ⎯ ⎯ 300 ⎯ ⎯ 300 2 ⎯ 14 ⎯ ⎯ 340 ns ⎯ ⎯ 340 ⎯ ⎯ 340 CLK-SERIAL OUT 2 ⎯ 14 6 10% to 90% points of OUT0 to OUT7 voltage waveforms ⎯ ⎯ 150 6 90% to 10% points of OUT0 to OUT7 voltage waveforms ⎯ ⎯ 300 tpHL2 6 tpHL3 6 LATCH = “H” tpHL 6 Output rise time tor Output fall time tof ENABLE = “L” ENABLE - OUTn , Unit Note 1: Topr = 25°C, VDD = VIH = 3.3 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15mA, VL = 5.0 V, CL = 10.5pF (see test circuit 6.) 9 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Test Circuits Test Circuit 1: High-Level and Low-Level Input Voltages (VIH/VIL) ENABLE VDD OUT0 CLOCK F.G LATCH GND SERIAL-OUT REXT IO = −5 mA to 5 mA R-EXT CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) V VDD = 5 V、3.3V OUT7 SERIAL-IN Test Circuit 2: High-Level Input Current (IIH) VIN = VDD A A A VDD ENABLE OUT0 CLOCK LATCH A GND SERIAL-OUT REXT CL = 10.5 pF R-EXT VDD = 4.5 to 5.5 V、3 to 3.6V OUT7 SERIAL-IN Test Circuit 3: Low-Level Input Current (IIL) OUT0 CLOCK LATCH OUT7 SERIAL-IN R-EXT GND SERIAL-OUT 10 VDD = 4 5 to 5 5 V、3 to 3 6V A VDD CL = 10.5 pF A A ENABLE REXT A (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Test Circuit 4: Supply Current ENABLE LATCH OUT7 SERIAL-IN R-EXT GND SERIAL-OUT CL = 10.5 pF REXT = 1.2 kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VDD = 4.5 to 5.5 V、3 to 3.6V F.G OUT0 CLOCK A Note: The output terminal is based on the power supply current conditions on page 6 and 7. Test Circuit 5: Output Current (IOUT1), Output Leakage Current (IOZ) Output Current Variations (∆IOUT1/∆IOUT2), Current Variation with VDD (%/VDD) ENABLE VDD OUT0 A OUT7 A CLOCK LATCH SERIAL-IN A GND SERIAL-OUT CL = 10.5 pF VOUT = 0.4 V, 25 V R-EXT REXT = 1.2 kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VDD = 4.5 to 5.5 V、3 to 3.6V F.G Theoretical output current = 1.13 V/REXT × 16 (VG=1) Test Circuit 6: Switching Characteristics ENABLE RL=300Ω VDD OUT0 CLOCK CL LATCH IOUT SERIAL-IN CL = 10.5 pF R-EXT GND SERIAL-OUT CL = 10.5 pF REXT = 12 kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) 11 VL = 5 V OUT7 VDD = 4.5 to 5.5 V、3 to 3.6V F.G (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Test Circuit 7: ODD and OSD Characteristics F.G CLOCK SERIAL-IN VDD OUT0 V LATCH ENABLE OUT7 V 12 VOUT2 = ?V SOUT VOUT1 = ?V GND CL = 10.5 pF REXT REXT = ?? kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VDD = 4.5 V to 5.5 V、3 to 3.6V V (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Timing Waveforms 1. CLOCK, SERIAL-IN, SERIAL-OUT twCLK CLOCK 50% 90% 50% 10% tSETUP1 SERIAL-IN 90% 10% tr 50% tf 50% tHOLD1 SERIAL-OUT 50% tpLH/tpHL 2. CLOCK, SERIAL-IN, LATCH , ENABLE , OUTn 50% CLOCK 50% SERIAL-IN LATCH tHOLD2 tSETUP2 50% 50% twLAT twENA twENA 50% ENABLE OUTn 50% 50% 50% 50% tpHL1/LH1 tpHL2/LH2 tpHL3/LH3 3. OUTn 90% OFF 90% OUTn 10% 10% tof ON tor 4. Special Mode twCLK CLOCK 50% 50% 50% tSETUP3 tHOLD3 50% 50% tSETUP4 LATCH tHOLD4 50% 50% Note: The timing chart waveform may be simplified to explain a function and operation. Timing conditions must be taken care enough. 13 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Special Mode Sequence for Switching to Special Mode 1 2 3 4 5 ENABLE H L H H H LATCH L L L H L CLOCK Only the above signal sequence puts the TB62778FNG in special mode. In this mode, two sub-modes are available: total brightness adjustment mode and error detection (OOD/OSD) mode. While switching to special mode, data is not latched by LATCH . After power-on, the TB62778FNG defaults to normal mode. Total Brightness Adjustment Mode Writing a brightness code 1 0 2 3 4 5 6 7 CLOCK ENABLE H H LATCH L SERIAL-IN Bit 6 Bit 7 Bit 5 Bit 2 Bit 4 Bit 3 Bit 1 Bit 0 Brightness code In total brightness adjustment mode, when LATCH is High, a brightness code in the shift register is latched into the brightness adjustment register instead of the output latches. Once latched into the brightness adjustment register, the brightness code is held until the TB62778FNG is powered off or it is overwritten with a new code. Adjusting the total brightness Bit definition of the brightness code Default Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Reserved HC AG5 AG4 AG3 AG2 AG1 AG0 1 1 1 1 1 1 1 1 The 8-bit brightness code is shifted in from the SERIAL-IN terminal, with bit 7 first. Bits 1 to 7 of the code determine the voltage applied to the R-EXT terminal (VG). Bit 1, HC, divides the voltage range into 25% to 50% (HC = 0) or 50% to 100% (HC = 1), and bits 2 to 7 are used to adjust the voltage in 64 steps within the range selected by bit 1. After on power, total brightness adjustment code becomes the above-mentioned default value. 14 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Theoretical Current Settings (preliminary) Current = 1.13 V × VG ÷ R-EXT × 16 1.2 1 VG 0.8 0.6 0.4 0.2 [1,１１１１１１] [1,１０１１１１] [1,０１１１１１] [1,００１１１１] [０,１１１１１１] [1,００００００] [０,１０１１１１] 0 [０,０１１１１１] [０,００１１１１] [０,００００００] 0 16 32 48 64 80 96 11 12 2 8 Brightness code (HC, AG[0:5]) 全輝度調整コード（HC,AG[0：5]） Note) After setting up total luminance, it must be paid attention because the operation moves to the error detection mode (OOD) when five clocks are taken during the setting current output ( ENABLE = L period). (Please see the error detection mode on page 15.) Error Detection Mode 1 (OOD Detection) 3.5 µs min 1 2 3 4 L L L L 5 6 CLOCK ENABLE H L L H H H H H Error status code SOUT Bit 7 Input source of the shift register H SERIAL-IN Error detection Bit Bit Bit Bit Bit 6 5 4 3 2 SERIAL-IN In special mode, the TB62778FNG not only enables the outputs but also performs error detection, and if any error is detected, loads an error status code into the shift register. For ODD detection, five Low bits must be shifted in. Immediately following the fifth Low bit, the input source of the shift register switches from the SERIAL-IN terminal to the 8-bit parallel error status code register. An error status code is generated at least 3.5µs from the fifth rising edge of CLOCK after ENABLE is set Low. If any Low bit occurs thereafter, the detected error status code is saved in the shift register. Therefore, while ENABLE is Low, serial data can not be shifted into the TB62778FNG via the SERIAL-IN terminal. Setting ENABLE high changes the input source of the shift register to the SERIAL-IN terminal, disables the outputs and terminates error detection. Thereupon, new serial data is shifted into the TB62778FNG via the SERIAL-IN terminal while the error code in the shift register is shifted out from the SERIAL-OUT terminal on the falling edge of CLOCK. The output is Hi-Z when the output is turning off before OOD detection. So please execute the OOD detection after the output is turning on. Error Status Code in OOD Detection Mode Error Status Code Output Terminal State VOOD ≥ VO 0 Open VOOD < VO 1 Normal 15 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Error Detection Mode 2 (OSD Detection) 3.5 µs min 1 2 3 4 L L H L 5 6 CLOCK H ENABLE L L H H H H H H Error status code SOUT Bit 7 Input source of the shift register SERIAL-IN Error detection Bit Bit Bit Bit Bit 6 5 4 3 2 SERIAL-IN In special mode, the TB62778FNG not only enables the outputs but also performs error detection, and if any error is detected, loads an error status code into the shift register. For OSD detection, an L-L-H-L-L sequence must be shifted in. Immediately following the fifth Low bit, the input source of the shift register switches from the SERIAL-IN terminal to the 8-bit parallel error status code register. An error status code is generated at least 3.5 µs from the fifth rising edge of CLOCK after ENABLE is set Low. If any Low bit occurs thereafter, the detected error status code is saved in the shift register. Therefore, while ENABLE is Low, serial data can not be shifted into the TB62778FNG via the SERIAL-IN terminal. Setting ENABLE high changes the input source of the shift register to the SERIAL-IN terminal, disables the outputs and terminates error detection. Thereupon, new serial data is shifted into the TB62778FNG via the SERIAL-IN terminal while the error code in the shift register is shifted out from the SERIAL-OUT terminal on the falling edge of CLOCK. TB62777FNG is over the power dissipation when OSD detection. So please execute the OSD detection after the output is turning off. Error Status Code in OSD Detection Mode Error Status Code Output Terminal State VOOD ≤ VO 0 Shorted VOOD > VO 1 Normal Note) The output current at the error detection mode is 25% of a set current (total brightness adjustment code（LSB） : minimum current setting). Sequence for Switching to Normal Mode 1 2 3 4 5 ENABLE H L H H H LATCH L L L L L CLOCK Low level Only in the case of this signal sequence, it changes to the normal mode. Data is reset(0) when the mode is changes from the specified mode to the normal mode. POR Characteristic VDD 2.8Ｖ or less 0.5Ｖ or less POR Release 16 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Output current vs. Dirating (lighting rate) graph PCB Conditions: 76.2 × 114.3 × 1.6 mm, Cu = 30%, 35-µm Thick, SEMI-Compliant IOUT − Duty ON PCB Pd-Ta 1.4 100 90 1.2 70 1.0 60 0.8 Pd(W) IOUT (mA) 80 50 40 0.6 ON PCB 30 All outputs ON 0.4 Ta = 85°C 20 VDD = 5.0 V 10 0.2 VOUT = 1.0 V 0.0 0 0 20 40 60 80 0 100 50 100 150 Ta (°C) Duty − Turn-ON rate (%) Output Current vs. External Resistor (typ.) IOUT −R IOUT - EXT REXT 50 45 40 IOUT (mA) IOUT (mA) 35 30 25 20 15 10 5 All outputs ON Ta = 25°C VOUT = 0.7 V 0 100 1000 REXT (Ω) 10000 The above graphs are presented merely as a guide and does not constitute any guarantee as to the performance or characteristics of the device. Each product design should be fully evaluated in the real-world environment. 17 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Application Circuit: General Composition for Dynamic Lighting of LEDs In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V. VLED O0 O1 O2 O5 O6 O7 SERIAL-IN C.U. ENABLE LATCH O0 SERIAL-OUT ENABLE TB62778FNG LATCH CLOCK O1 O2 O5 O6 O7 SERIAL-OUT SERIAL-IN TB62778FNG CLOCK R-EXT GND R-EXT 18 GND (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Application Circuit: General Composition for Dynamic Lighting of LEDs In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V. Example) TD62M8600FG 8 bit multichip PNP transistor array. It is not necessary when lighting statically. VLED O0 O6 O1 O7 SERIAL-IN C.U. ENABLE LATCH SERIAL-OUT ENABLE TB62778FNG LATCH CLOCK SERIAL-OUT SERIAL-IN TB62778FNG CLOCK R-EXT R-EXT GND 19 GND (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Package Dimensions Weight: 0.07 g (typ.) 20 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. IC Usage Considerations Notes on handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. 21 (Ver.0.0) 08-02-07 TENTATIVE (5) TB62778FNG Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. Points to remember on handling of ICs (1) Over current Protection Circuit Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all circumstances. If the Over current protection circuits operate against the over current, clear the over current status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over current protection circuit to not operate properly or IC breakdown before operation. In addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the IC may generate heat resulting in breakdown. (2) Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 22 (Ver.0.0) 08-02-07 TENTATIVE TB62778FNG About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux RESTRICTIONS ON PRODUCT USE 070122EBA • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C • The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E 23 (Ver.0.0) 08-02-07