TMD4903 Color and Proximity Sensor Module with mobeam™ Barcode Emulation and IR Remote Control General Description The TMD4903 features ambient light and color (RGB) sensing, proximity detection and IRBeam optical pattern generator capable of mobeam™ barcode emulation and IR remote control. In addition, the device integrates an IR LED and advanced LED driver, all within a low-profile and small footprint, 2.0mm x 5.0mm x 1.0mm package. The Proximity sensing function synchronizes IR emission and detection to sense proximity events. The architecture of the engine features self-maximizing dynamic range, ambient light subtraction, advanced crosstalk cancelation, 14-bit data output, 32-dataset FIFO, and interrupt-driven I²C communication. Sensitivity, power consumption, and noise can be optimized with adjustable IR LED timing and power. The proximity engine recognizes detect/release events and produces a configurable interrupt whenever proximity result crosses upper or lower threshold settings. The Ambient Light and Color Sensing function provides Red, Green, and Blue (RGB) ambient light sensing with a Clear reference (C). The color diode array has a UV/IR blocking filter and parallel ADCs to produce simultaneous 16-bit results. This architecture accurately measures ambient light and enables the calculation of illuminance, chromaticity, and color temperature to manage display appearance. The IRBeam pattern generator supports mobeam™ barcode emulation and IR remote control. The engine features RAM for pattern storage and specialized control logic that is tailored to repetitively broadcast a barcode pattern using the integrated LED or an external LED with a low side driver. The IRBeam engine features adjustable timing, looping, and IR intensity to maximize successful transmission. IRBeam is designed to support all requirements for 1-D barcode transmission over IR to point-of-sale (POS) terminals as well as IR remote control. Ordering Information and Content Guide appear at end of datasheet. ams Datasheet [v1-12] 2015-May-14 Page 1 Document Feedback TMD4903 − General Description Key Benefits & Features The benefits and features of TMD4903, Color and Proximity Sensor Module with mobeam™ Barcode Emulation and IR Remote Control are listed below: Figure 1: Added Value of Using TMD4903 Benefit Feature Proximity detection • • • • • • Selectable direction sensitivity Ambient light rejection Advanced crosstalk compensation AFE saturation flag Programmable LED driver Interrupt-Driven I²C communication Ambient light and color sensing • • • • • • Variable sensitivity Designed to operate behind inked glass UV/IR blocking filter Programmable gain and integration time 6.7M:1 dynamic range by gain adjustment only Interrupt-driven I²C communication IRBeam pattern generator • mobeam™ support • Universal remote control support • Interrupt-driven I²C communication Integrated LED and driver • Calibrated emission and response • Invisible 950nm emission Low supply voltage • 1.8V operation Applications The TMD4903 applications include: • Color sensing • Ambient light sensing • Cell phone touch screen disable • Mechanical switch replacement • 1D barcode emulation • Universal remote control Page 2 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − General Description Block Diagram The functional blocks of this device for reference are shown below: Figure 2: TMD4903 Block Diagram I2C 256 Byte FIFO (2048 Bit Pattern RAM) ! "! ! # "! ams Datasheet [v1-12] 2015-May-14 TMD4903 Page 3 Document Feedback TMD4903 − Pin Assignment The device pin assignments are described below. Pin Assignment Figure 3: Pin Diagram R Pin Description Figure 4: Pin Description Pin Number Pin Name 1 VDD Supply voltage (1.8V) 2 SCL I²C serial clock terminal 3 GND Ground. All voltages are referenced to GND 4 LEDA LED anode 5 LDR LED driver (sinks current) and LED cathode (for direct access to LED) 6 GPIO Open drain IRBeam output or alternate interrupt 7 INT Interrupt. Open drain output and logic level output for external IR LED circuit 8 SDA I²C serial data I/O terminal Page 4 Document Feedback Description ams Datasheet [v1-12] 2015-May-14 TMD4903 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Min Max Units Supply voltage -0.3 2.2 V LED anode supply -0.3 3.6 V VIO Digital I/O terminal voltage -0.3 3.6 V VLDR Terminal voltage -0.3 3.6 V VDD VLEDA Parameter IIO Output terminal current -1 20 mA Tstg Storage temperature range -40 85 ºC ESDHBM ESD tolerance, human body model ±2000 Comments see note (2) V Note(s) and/or Footnote(s): 1. All voltages with respect to GND 2. Measured with LDR = OFF or LDR = ON and LDRIVE = 310mA. ams Datasheet [v1-12] 2015-May-14 Page 5 Document Feedback TMD4903 − Electrical Characteristics The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Electrical Characteristics Figure 6: Recommended Operating Conditions Symbol VDD TA Parameter Min Typ Max Units Supply voltage 1.7 1.8 2.0 V Operating free-air temperature (1) -30 85 °C Note(s) and/or Footnote(s): 1. While the device is operational across the temperature range, functionality will vary with temperature. Specifications are stated at 25°C, unless otherwise noted. Figure 7: Operating Characteristics, VDD = 1.8 V, TA = 25ºC (unless otherwise noted) Symbol fOSC Parameter Conditions Min Oscillator Frequency Typ Max 8.1 Active ALS state (PON=AEN=1, PEN=IBEN=0) (2) 90 150 Units MHz 200 μA IDD Supply current (1) Idle state (PON=1, AEN=PEN=IBEN=0) (3) 30 60 Sleep State (4) 0.4 5 VOL INT, SDA, GPIO output low voltage ILEAK Leakage current, SDA, SCL, INT, GPIO, LDR pins -5 VIH SCL, SDA input high voltage 1.26 VIL SCL, SDA input low voltage 6 mA sink current 0.6 V 5 μA V 0.54 V Note(s) and/or Footnote(s): 1. Values are shown at the VDD pin and do not include current through the IR LED. 2. This parameter indicates the supply current during periods of ALS integration. If Wait is enabled (WEN=1), the supply current is lower during the Wait period. 3. Idle state occurs when PON=1 and all functions are not enabled. 4. Sleep state occurs when PON = 0 and I²C bus is idle. If Sleep state has been entered as the result of operational flow, SAI = 1, PON will remain high. Page 6 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Electrical Characteristics Figure 8: ALS/Color Operating Characteristics, VDD = 1.8 V, TA = 25ºC, AGAIN = 16x, ATIME = 0xF6 (unless otherwise noted) Parameter Conditions Integration time step size(1), (2) Dark ADC count value (2) Ee = 0 μW/ cm2 AGAIN: 64x ATIME: 100ms (0xDC) Min Typ Max Units 2.68 2.78 2.90 ms 0 1 3 counts AGAIN: 1/4x 0.0135 0.0175 AGAIN: 1x 0.058 0.067 AGAIN: 4x 0.237 0.263 AGAIN: 64x 3.75 4.37 Clear channel irradiance responsivity White LED, 2700K 8.94 10.28 11.62 counts/ (μW/ cm2) Lux accuracy (3) White LED, 2700K 90 100 110 % ADC Noise (4) AGAIN: 16x Gain scaling, relative to 16x gain setting x 0.005 % Full Scale Note(s) and/or Footnote(s): 1. Integration time is configured from 1 step (0xFF) to 256 steps (0x00) for a typical range of 2.78ms to 711.11ms. An ATIME setting of 0xFF results in a full-scale count value of 1024. Each additional integration step adds 1024 counts to full scale. To enable 16-bit ADC range, 64 or more integration steps (177.8ms or more) are required (ATIME <= 0xC0). 2. The typical 3-sigma distribution is between 0 and 1 count for an AGAIN setting of 16x. 3. Lux accuracy is function of red, green, blue and clear channels, and not 100% production tested. 4. ADC noise is calculated as the standard deviation of 1000 data samples. ams Datasheet [v1-12] 2015-May-14 Page 7 Document Feedback TMD4903 − Electrical Characteristics Figure 9: Color Ratio Characteristics, VDD = 1.8V, TA = 25ºC Ratio of Color to Clear Channel Parameter Color ADC count value ratio: Color/Clear Test Conditions Red Channel Green Channel Blue Channel Min Max Min Max Min Max White LED, 2700 K 45% 65% 19% 39% 15% 40% λD = 465 nm (1) 0% 15% 10% 42% 70% 90% λD = 525 nm (2) 4% 25% 60% 85% 10% 45% λD = 615 nm (3) 80% 110% 0% 14% 5% 24% Note(s) and/or Footnote(s): 1. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength λ D = 465 nm, spectral halfwidth Δλ½ = 22 nm. 2. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength λ D = 525 nm, spectral halfwidth Δλ½ = 35 nm. 3. The 615 nm input irradiance is supplied by an AlInGaP light-emitting diode with the following characteristics: dominant wavelength λ D = 615 nm, spectral halfwidth Δλ½ = 15 nm. Page 8 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Electrical Characteristics Figure 10: Proximity Operating Characteristics, VDD = 1.8 V, TA = 25ºC (unless otherwise noted) Parameter Conditions Min ADC conversion time step size Typ Max 20 Offset (no target response) (1) PGAIN = 2 (4x) PGLDRIVE = 7 (150mA) PGPULSE_LEN = 1 (8us) No target present After electrical calibration Part to part variation (2) PGAIN = 2 (4x) PGLDRIVE = 1 (30mA) PGPULSE_LEN = 1 (8us) d=23mm round target 30mm target distance After electrical calibration Response, absolute (3) PGAIN = 2 (4x) PGLDRIVE = 7 (150mA) PGPULSE_LEN = 1 (8us) 100x100mm, 90% reflective Kodak gray card 100mm target distance After electrical calibration Noise/Signal (4) PGAIN = 2 (4x) PGLDRIVE = 2 (50mA) PGPULSE_LEN = 1 (8us) PGPULSE = 7 (8 pulses) Unit μs 16 36 counts 75 100 125 % 790 990 1190 counts 2 % Note(s) and/or Footnote(s): 1. Offset varies with power supply characteristics and system noise. 2. Production tested result is the average of 5 readings expressed relative to a calibrated response. 3. Representative result by characterization. Device settings can vary from 1 to 64 pulse count, 4μs to 32μs pulse width, 10mA to 310mA current setting, and 1x to 8x electrical gain. Refer to Figure 22 for device performance with different settings. 4. Production tested result is the range of 20 readings divided by the average response. ams Datasheet [v1-12] 2015-May-14 Page 9 Document Feedback TMD4903 − Electrical Characteristics Figure 11: Proximity Test Circuit 22Ω VDD 1µF GND 4 LEDA 1 1µF TMD4903 5 3 22µF LDR Figure 12: Wait Characteristics, VDD = 1.8 V, TA = 25ºC, WEN = 1 (unless otherwise noted) Parameter Conditions Wait step size Min Typ Max Units 2.68 2.78 2.90 ms Long wait step size 33.3 ms Figure 13: IRBeam Operating Characteristics, VDD = 1.8 V, TA = 25ºC (unless otherwise noted) Symbol Parameter Conditions t(PBT min) Minimum bit time IBEN = 1 Page 10 Document Feedback Min Typ 0.25 Max Units μs ams Datasheet [v1-12] 2015-May-14 TMD4903 − Timing Characteristics Timing Characteristics Figure 14: AC Electrical Characteristics, VDD = 1.8 V, TA = 25ºC (unless otherwise noted) Parameter Description Min Typ Max Unit 400 kHz fSCL (1) Clock frequency (I²C only) tBUF (1) Bus free time between start and stop condition 1.3 μs tHS;STA (1) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 μs tSU;STA (1) Repeated start condition setup time 0.6 μs tSU;STO (1) Stop condition setup time 0.6 μs tHD;DAT (1) Data hold time 0 ns tSU;DAT (1) Data setup time 100 ns tLOW (1) SCL clock low period 1.3 μs tHIGH (1) SCL clock high period 0.6 μs 0 tF (1) Clock/data fall time 300 ns tR (1) Clock/data rise time 300 ns Ci (1) Input pin capacitance 10 pF Note(s) and/or Footnote(s): 1. Specified by design and characterization; not production tested. Timing Diagram Figure 15: Timing Parameter Measurement Drawing tHIGH tR tLOW tF VIH SCL VIL tHD; STA tSU; DAT tHD; DAT tSU; STA tSU; STO tBUF SDA VIH VIL STOP START ams Datasheet [v1-12] 2015-May-14 START STOP Page 11 Document Feedback TMD4903 − Typical Operating Characteristics Typical Operating Characteristics Figure 16: Spectral Responsivity Spectral Responsivity 180% Clear Red Green Blue IR Normalized Responsivity 160% 140% 120% 100% 80% 60% 40% 20% 0% 300 400 500 600 700 800 900 1000 1100 λ - Wavelength - nm Figure 17: CRGB Responsivity vs. Angular Displacement Normalized Angular Response Normalized Response (%) 100% 90% Green LED All Channels 80% 70% 60% 50% 40% 30% 20% 10% 0% -90 -75 -60 -45 -30 -15 0 15 30 45 60 75 90 Angle of Incident Light (degrees) Page 12 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Typical Operating Characteristics Figure 18: Typical LDR Current vs. Voltage Typical LDR Current vs. Voltage 0.35 310mA 290mA 0.3 270mA 250mA LDR Current 0.25 230mA 210mA 0.2 190mA 170mA 150mA 0.15 130mA 110mA 0.1 90mA 70mA 0.05 50mA 30mA 0 10mA 0 0.5 1 1.5 2 2.5 3 3.5 LDR Voltage (V) Temperature Coefficient - ppm/ºC Figure 19: Responsivity Temperature Coefficient λ - Wavelength - nm ams Datasheet [v1-12] 2015-May-14 Page 13 Document Feedback TMD4903 − Typical Operating Characteristics Figure 20: Illuminance (Lux) vs. Counts (Clear Channel) Dynamic Range (ATIME = 100ms) 1000000 Illuminance (lux) 100000 10000 1000 100 1/4x 1x 10 4x 1 16x 64x 0.1 0.01 1 10 100 1000 10000 100000 Clear channel (counts) Figure 21: 950nm LED Forward Voltage vs. Current LED Forward Voltage Forward Current (mA DC) 300 250 200 150 100 50 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Forward Voltage (V) Note(s) and/or Footnote(s): 1. The voltage on the LDR pin (VLEDA – VLED FORWARD) must be sufficiently large to guarantee proper operation of the regulated current sink. Page 14 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Typical Operating Characteristics Figure 22: Proximity Response vs. Target Distance PGAIN =2 (4x), PGLDRIVE = 7 (150mA), 100x100mm, 90% Reflective Kodak gray card TMD4903 Proximity Response by Pulse Width 18000 4µs 8µs 16µs 32µs 16000 14000 Counts 12000 10000 8000 6000 4000 2000 0 0 5 10 15 20 Distance - cm ams Datasheet [v1-12] 2015-May-14 Page 15 Document Feedback TMD4903 − I²C Protocol I²C Protocol The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and both standard and full-speed clock frequency modes. Read and Write transactions comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (I.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general it is recommended to use I²C bursts whenever possible, especially in this case when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors. I²C Write Transaction A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP. Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP. I²C Read Transaction A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP. The I²C bus protocol was developed by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification. Page 16 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − I²C Protocol Figure 23: Simplified State Diagram ( # / & # !-!. * %&' # $ / / & %&' / , & # %&' & # )*+ ams Datasheet [v1-12] 2015-May-14 * & , / # )*+ * * Page 17 Document Feedback TMD4903 − I²C Protocol Figure 24: Detailed State Diagram *78/9 : 0 %,//1' # SAI = 1? # + # 2&3 + )# 2/ 2& %*' $ 0 %45!' , 66 2/ $# #2& # )*+ %*' #2/ , ( % #* ' $*$ # 2& * + + $# $# $ $# EVALUATE : INTERRUPT? * *# $ * * * # Note(s) and/or Footnote(s): 1. While IRBeam is enabled (IBEN = 1), PROXIMITY is disabled automatically. Page 18 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Detailed Description Detailed Description Upon power-up, POR, the device initializes. During initialization (typically 200μs), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed, and all outputs from the device must be ignored including interrupts. After initialization, the device enters the SLEEP state. In this operational state the internal oscillator and other circuitry are not active, resulting in ultra-low power consumption. If I²C transaction occurs during this state, the I²C core wake up temporarily to service the communication. Once the Power ON bit, PON, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. The first time the SLEEP state is exited and any functions are enabled (PEN | AEN | IBEN = 1) an EXIT SLEEP pause occurs followed by an immediate entry into the selected engines. If all functions are disabled (PEN = 0 & AEN = 0 & IBEN = 0), the device returns to the IDLE state. As depicted in Figure 23 and Figure 24, the proximity and CRGB color sensing functions operate in parallel when enabled (PEN | AEN = 1). The IRBeam pattern generator takes priority when enabled (IBEN = 1).Proximity will not function, and ALS integration only occurs while IRBeam is in standby. In addition, when proximity or calibration is requested, it will temporarily disable the proximity function. A simplified state diagram for each function is depicted in Figure 24. Each function is individually configured (e.g. Gain, ADC integration time, wait time, persistence, thresholds, etc.). Sleep After Interrupt Operation If Sleep After Interrupt is enabled (SAI = 1), the state machine will enter SLEEP when non-gesture interrupts occur. However for IRBeam, the state machine remains active to continue to support this function. Entering SLEEP does not automatically change any of the register settings (E.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP state is terminated when the SAI bit is cleared. ams Datasheet [v1-12] 2015-May-14 Page 19 Document Feedback TMD4903 − Register Description The device is controlled and monitored by registers accessed through the I²C serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Figure 25. Register Description Figure 25: Control Register Map Reset Value Address Register Name R/W 0x00 – 0x7F RAM R/W Volatile Storage for Pattern data 0x00 0x80 ENABLE R/W Enables states and interrupts 0x00 0x81 ATIME R/W ADC integration time 0xFF 0x82 PTIME R/W Proximity sample time 0x00 0x83 WTIME R/W ALS wait time 0xFF 0x84 AILTL R/W ALS interrupt low threshold low byte 0x00 0x85 AILTH R/W ALS interrupt low threshold high byte 0x00 0x86 AIHTL R/W ALS interrupt high threshold low byte 0x00 0x87 AIHTH R/W ALS interrupt high threshold high byte 0x00 0x88 PILTL R/W Proximity interrupt low threshold low byte 0x00 0x89 PILTH R/W Proximity interrupt high threshold high byte 0x00 0x8A PIHTL R/W Proximity interrupt low threshold low byte 0x00 0x8B PIHTH R/W Proximity interrupt high threshold high byte 0x00 0x8C PERS R/W ALS & Proximity interrupt persistence filters 0x00 0x8D CFG0 R/W Configuration register zero 0xA0 0x8E PGCFG0 R/W Proximity pulse width and count 0x4F 0x8F PGCFG1 R/W Proximity gain and LED current 0x80 0x90 CFG1 R/W Configuration register one 0x00 0x91 REVID R Revision ID 0x22 0x92 ID R Device ID 0xB8 0x93 STATUS R Device status register one 0x00 0x94 CDATAL R Clear ADC low data register 0x00 0x95 CDATAH R Clear ADC high data register 0x00 0x96 RDATAL R Red ADC low data register 0x00 Page 20 Document Feedback Register Function ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Register Name R/W 0x97 RDATAH R Red ADC high data register 0x00 0x98 GDATAL R Green ADC low data register 0x00 0x99 GDATAH R Green ADC high data register 0x00 0x9A BDATAL R Blue ADC low data register 0x00 0x9B BDATAH R Blue ADC high data register 0x00 0x9C PDATAL R Proximity ADC low data register 0x00 0x9D PDATAH R Proximity ADC high data register 0x00 0x9E STATUS2 R Additional device status 0x00 0x9F CFG2 R/W Configuration register two 0x04 0xA0 ICONFIG R/W IRBeam configuration register one 0x00 0xA1 ICONFIG2 R/W IRBeam configuration register two 0x00 0xA2 ISNL R/W IRBeam symbol loops 0x00 0xA3 ISOFF R/W IRBeam delay between symbol loops 0x00 0xA4 IPNL R/W IRbeam packet loops 0x00 0xA5 IPOFF R/W IRBeam delay between packet loops 0x00 0xA6 IBT R/W IRBeam time period 0x00 0xA7 ISLEN R/W IRBeam symbol length 0x00 0xA8 ISTATUS R IRBeam status 0x00 0xA9 ISTART R/W IRBeam start transmission 0x00 0xAB CFG3 R/W Configuration register three 0x00 0xAC CFG4 R/W Configuration register four 0x07 0xAD CFG5 R/W Configuration register five 0x08 0xB3 STATUS3 R Status register three 0x00 0xBC CONTROL R/W Control register 0x00 0xBD AUXID R Auxiliary ID 0x00 0xC0 OFFSETNL R/W North channel offset low byte 0x00 0xC1 OFFSETNH R/W North channel offset high byte 0x00 0xC2 OFFSETSL R/W South channel offset low byte 0x00 0xC3 OFFSETSH R/W South channel offset high byte 0x00 0xC4 OFFSETWL R/W West channel offset low byte 0x00 ams Datasheet [v1-12] 2015-May-14 Register Function Reset Value Address Page 21 Document Feedback TMD4903 − Register Description Register Name R/W 0xC5 OFFSETWH R/W West channel offset high byte 0x00 0xC6 OFFSETEL R/W East channel offset low byte 0x00 0xC7 OFFSETEH R/W East channel offset high byte 0x00 0xD6 AZ_CONFIG R/W Configure CRGB autozero frequency 0xFF 0xD7 CALIB R/W Start offset calibration 0x00 0xD8 CALIBCFG0 R/W Calibration configuration register zero 0x44 0xD9 CALIBCFG1 R/W Calibration configuration register one 0x0C 0xDD INTENAB R/W Interrupt enable 0x00 0xDE INCLEAR R/W Interrupt clear 0x00 Page 22 Document Feedback Register Function Reset Value Address ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Enable Register (ENABLE 0x80) Enable has fields that power on the device and enable the functions. Before enabling any functions, all of the bits associated with each function must be set. Changing control register values while operating may result in invalid results. Figure 26: Enable Register 7 6 5 4 3 2 1 0 IBEN Reserved PIEN AIEN WEN PEN AEN PON Field Bits Description IBEN 7 IRBeam Enable. When asserted, the LED driver pin (LDR) is controlled by the IRBeam state machine. Proximity is suppressed. ALS continues in the background except when IBUSY = 1 (ISTATUS register). Reserved 6 Reserved. Bit must be set to 0. PIEN 5 Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter. AIEN 4 ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. WEN 3 Wait Enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the wait timer. PEN 2 Proximity Enable. This bit activates the proximity function. Writing a 1 enables proximity. Writing a 0 disables proximity. AEN 1 ALS Enable. This bit activates the ALS/Color functionality. Writing a 1 enables ALS/Color. Writing a 0 disables ALS/Color. 0 Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator and clears IBEN, PEN, and AEN. Only set this bit after all other registers have been initialized by the host. PON ams Datasheet [v1-12] 2015-May-14 Page 23 Document Feedback TMD4903 − Register Description ALS Integration Time Register (ATIME 0x81) Figure 27: ALS Integration Time Register 7 6 5 4 3 2 1 0 ATIME Field Bits Description ALS Integration Time. Sets the internal integration time of ALS/Color analog to digital converters in increments of 2.78ms. The power on reset value is 0xFF. The ADC maximum count (or saturation) value depends on the integration time. It is the lesser of either: 65535 (16-bit saturation) or The result of equation: CountMAX = 1024 X CYCLES ATIME 7:0 Page 24 Document Feedback VALUE INTEGRATION TIME MAX COUNTS 0xFF 2.78ms 1024 0xF6 27.8ms 10240 0xDC 100ms 36864 … 2.78ms X (256 - ATIME) … 0xC0 178ms 65535 0x00 711ms 65535 ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Proximity Sample Time Register (PTIME 0x82) Figure 28: Proximity Sample Time Register 7 6 5 4 3 2 1 0 PTIME Field Bits Description Proximity Sample Time. Sets the proximity sample rate. The power on reset value is 0x00. Proximity is executed once for each sample time. PTIME 7:0 ams Datasheet [v1-12] 2015-May-14 VALUE SAMPLE TIME FREQUENCY 0x00 2.78ms 360Hz 0x01 5.56ms 180Hz 0x03 11.1ms 90Hz 0x23 100ms 10Hz … 2.78ms X (PTIME +1) 1/Proximity Sample Time 0xFF 711ms 1.41Hz Page 25 Document Feedback TMD4903 − Register Description Wait Time Register (WTIME 0x83) Figure 29: Wait Time Register 7 6 5 4 3 2 1 0 WTIME Field Bits Description Wait Time. Sets the wait time between ALS cycles. Wait mode reduces current consumption. It is set in 2.78ms increments unless the WLONG bit is asserted in which case the wait times are 12x longer. The power on reset value is 0xFF. Wait time should be configured before AEN is asserted. WTIME 7:0 Page 26 Document Feedback VALUE WAIT TIME (WLONG=0) WAIT TIME (WLONG=1) 0xFF 2.78ms 0.03sec 0xDC 100ms 1.20sec … 2.78ms X (256 - WTIME) 33.3ms X (256 - WTIME) 0x6A 417ms 5.00sec 0x00 711ms 8.53sec ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description ALS Interrupt Threshold Registers (0x84 – 0x87) ALS level detection uses data generated by the Clear Channel. The ALS Interrupt Threshold registers provide 16-bit values to be used as the high and low thresholds for comparison to the 16-bit CDATA values. If AIEN is enabled and CDATA is not between AILT and AIHT for the number of consecutive samples specified in APERS an interrupt is asserted on the interrupt pin. Figure 30: ALS Interrupt Threshold Registers Field Register Bits Description 0x84 7:0 ALS low threshold low byte 0x85 15:8 ALS low threshold high byte 0x86 7:0 ALS high threshold low byte 0x87 15:8 ALS high threshold high byte AILT AIHT Proximity Interrupt Threshold Registers (0x88 – 0x8B) The Proximity Interrupt Threshold Registers set the high and low trigger points for the comparison function which generates an interrupt. If PDATA, the value generated by proximity channel, crosses from above to below the lower threshold or from below to above the upper threshold, an interrupt may be signaled to the host processor. Interrupt generation is subject to the value set in persistence filter (PPERS). Figure 31: Proximity Interrupt Threshold Registers Field Register Bits Description 0x88 7:0 Proximity low threshold low byte 0x89 15:8 Proximity low threshold high byte 0x8A 7:0 Proximity high threshold low byte 0x8B 15:8 Proximity high threshold high byte PILT PIHT ams Datasheet [v1-12] 2015-May-14 Page 27 Document Feedback TMD4903 − Register Description Interrupt Persistence Register (PERS 0x8C) Figure 32: Interrupt Persistence Register 7 6 5 4 3 2 PPERS Field 1 0 APERS Bits Description Proximity Interrupt Persistence. Defines a filter for the number of consecutive occurrences that PDATA must remain outside the threshold range between PILT and PIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE PPERS 7:4 CONSECUTIVE OCCURENCES OUT OF RANGE 0 Every proximity cycle generates an interrupt 1 Generate interrupt after every occurrence. 2 Generate interrupt after 2 occurrences. ... Generate interrupt after PPERS occurrences. 15 Generate interrupt after 15 occurrences. ALS Interrupt Persistence. Defines a filter for the number of consecutive occurrences that CDATA must remain outside the threshold range between AILT and AIHT before an interrupt is generated. Any sample that is inside the threshold range resets the counter to 0. VALUE APERS 3:0 Page 28 Document Feedback CONSECUTIVE OCCURENCES OUT OF RANGE 0 Every ALS cycle generates an interrupt 1 Generate interrupt after every occurrence. 2 Generate interrupt after 2 occurrences. 3 Generate interrupt after 3 occurrences. 4 Generate interrupt after 5 occurrences. 5 Generate interrupt after 10 occurrences. … Generate interrupt after 5 X (APERS -3) occurrences. 14 Generate interrupt after 55 occurrences. 15 Generate interrupt after 60 occurrences. ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Configuration Register Zero (CFG0 0x8D) Figure 33: Configuration Register Zero 7 6 Reserved 5 4 LOWPOWER_IDLE Field Bits Reserved 7:6 LOWPOWER_IDLE 5 Reserved 4:3 WLONG 2 3 Reserved 2 WLONG 1 0 RAM_BANK Description Reserved Low Power Idle. When asserted, the device will run in a low power mode if all functions are in wait states or disabled. Reserved Wait Long Enable. When asserted, the wait cycles are increased by a factor 12x. RAM Bank Selection. Specifies the RAM bank to access for IRBeam. VALUE RAM_BANK 1:0 RAM BANK ACCESS 0 Ram Bank 0 (lower 128 bytes) 1 Ram Bank 1 (upper 128 bytes) 2 Access is given to the 16 words at 0xB0…0xBF. 3 ams Datasheet [v1-12] 2015-May-14 Page 29 Document Feedback TMD4903 − Register Description Proximity Configuration Register Zero (PGCFG0 0x8E) PGCFG0 has fields that set the amount of time the LDR driver is sinking current during a proximity pulse and set the maximum number of pulses for each proximity sample. Figure 34: Proximity Configuration Register Zero 7 6 5 4 PGPULSE_LEN Field 3 2 1 0 PPULSE Bits Description Proximity Pulse Length. Sets the LED-ON pulse width during a Proximity Pulse. PGPULSE_LEN PPULSE Page 30 Document Feedback 7:6 5:0 VALUE LED ON 0 4μs 1 8μs 2 16μs 3 32μs Proximity Pulse Count. Specifies the maximum number of Proximity pulses to be generated on LDR. The pulse count can be set between 1 and 64 pulses. The number of pulses is equal to the PPULSE value plus 1. ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Proximity Configuration Register One (PGCFG1 0x8F) PGCFG1 has fields that set the electrical gain of the proximity response and set the LED drive current during pulses. Figure 35: Proximity Configuration Register One 7 6 5 PGGAIN Reserved Field Bits 4 3 2 1 0 PGLDRIVE Reserved Description Proximity Gain Control. PGGAIN Reserved VALUE GAIN VALUE 0 1x Gain 1 2x Gain 2 4x Gain 3 8x Gain 7:6 5 Reserved. Bit must be set to 0. Proximity LED Drive Strength. Configures nominal LED current linearly in steps of 20mA (actual current depends on factory-configuration of LED drive strength). PGLDRIVE Reserved ams Datasheet [v1-12] 2015-May-14 4:1 0 VALUE LED STRENGTH 0 10mA 1 30mA 2 50mA … 10mA + (20mA * PGLDRIVE) 14 290mA 15 310mA Reserved. Bit must be set to 0. Page 31 Document Feedback TMD4903 − Register Description Configuration Register One (CFG1 0x90) CFG1 has fields that enable or disable the saturation interrupts for Proximity and ALS and set the electrical gain of the ALS response. Figure 36: Configuration Register One 7 6 5 PGSIEN ASIEN 4 3 2 1 0 Reserved AGAIN Field Bits Description PGSIEN 7 Proximity Saturation Interrupt Enable. When asserted permits proximity saturation interrupts to be generated. ASIEN 6 ALS Saturation Interrupt Enable. When asserted permits ALS saturation interrupts to be generated. Reserved 5:2 Reserved. Bits must be set to 0. ALS and Color Gain Control. AGAIN FIELD VALUE CRGB GAIN VALUE 0 1x Gain 1 4x Gain 2 16x Gain 3 64x Gain 1:0 Revision ID Register (REVID 0x91) Figure 37: Revision ID Register 7 6 5 4 3 2 Reserved 0 REV_ID Field Bits Reserved 7:3 Reserved. Default value is 00100. REV_ID 2:0 Wafer die revision level. Default value is 010. Page 32 Document Feedback 1 Description ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description ID Register (ID 0x92) Figure 38: ID Register 7 6 5 4 3 2 1 ID 0 Reserved Field Bits Description ID 7:2 Device Identification = 101110 Reserved 1:0 Reserved. Default value is 00. Status Register (STATUS 0x93) The read-only Status Register provides the status of the device. Figure 39: Status Register 7 6 5 4 3 2 1 0 ASAT PGSAT PINT AINT IINT Reserved CINT Reserved Field Bits ASAT 7 ALS Saturation. If ASIEN is set, indicates ALS saturation. Check the STATUS2 register to differentiate between analog or digital saturation. PGSAT 6 Proximity Saturation. If PGSIEN is set, indicates analog saturation during a previous proximity cycle. Check the STATUS2 register to differentiate between ambient or reflected light saturation. PINT 5 Proximity Interrupt. If PIEN is set, indicates that a proximity detect or release event that met the programmed proximity thresholds (PILT or PIHT) and persistence (PPERS) occurred. AINT 4 ALS Interrupt. If ASIEN is set, indicates that an ALS event that met the programmed ALS thresholds (AILT or AIHT) and persistence (APERS) occurred. IINT 3 IRBeam Interrupt. If IIEN is set, indicates that the device is asserting an end-of-transmission interrupt after transmitting a block of data. Bit is mirrored in the ISTATUS register. Reserved 2 Reserved. CINT 1 Calibration Interrupt. Indicates that either calibration is finished or that one of certain events have occurred during normal operation. If each function is enabled, CINT will be asserted if too many zeroes occur too often in a period of samples, if the proximity baseline has decreased, or if at least one offset register has been adjusted. Check the CALIBSTAT register to identify the triggering event(s). Reserved 0 Reserved. ams Datasheet [v1-12] 2015-May-14 Description Page 33 Document Feedback TMD4903 − Register Description CRGB Data Registers (0x94 − 0x9B) Red, green, blue, and clear data are stored as 16-bit values. The read sequence must read byte pairs (low followed by high) starting on an even address boundary (0x94, 0x96, 0x98, or 0x9A) inside the CRGB Data Register block. In addition, reading the Clear channel data low byte (0x94) latches all 8 data bytes. Reading these 8 bytes consecutively (0x94 - 0x9A) ensures that the data is concurrent. Figure 40: CRGB Data Registers Field Register Bits Description 0x94 7:0 Clear channel data low byte 0x95 15:8 Clear channel data high byte 0x96 7:0 Red channel data low byte 0x97 15:8 Red channel data high byte 0x98 7:0 Green channel data low byte 0x99 15:8 Green channel data high byte 0x9A 7:0 Blue channel data low byte 0x9B 15:8 Blue channel data high byte CDATA RDATA GDATA BDATA Page 34 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Proximity Data Registers (0x9C – 0x9D) Proximity data is stored as a 14-bit value (two bytes). PDATA has a two-byte latch like 16-bit fields. Reading the low byte first latches the high byte. Proximity detection uses an Automatic Pulse Control (APC) mechanism that adjusts the number of pulses per measurement based on the magnitude of the reflected IR signal. As the magnitude of the signal increases, the number of pulses decreases. Proximity detection uses a 10-bit ADC that is extended to a 14-bit dynamic range for PDATA using the following formula: PDATA = ADCvalue x (16 / proximity pulses) PDATA is the average response of the non-masked proximity photodiodes. If one or more photodiodes are masked (CFG2 register 0x9F), the proximity response will remain the same since it is an average of the active photodiodes. PDATA is therefore proportional to the reflected energy per pulse, independent of the number of pulses used. Figure 41: Proximity Data Register Field Register Bits Description 0x9C 7:0 Proximity data low byte 0x9D 13:8 Proximity data high byte PDATA ams Datasheet [v1-12] 2015-May-14 Page 35 Document Feedback TMD4903 − Register Description Status Register Two (STATUS2 0x9E) Figure 42: Status Register Two 7 6 5 4 3 2 1 0 PVALID AVALID Reserved ASAT_ DIGITAL ASAT_ ANALOG PGSAT_ ADC PGSAT_ REFLECTIVE PGSAT_ AMBIENT Field Bits Description PVALID 7 Proximity Valid. Indicates that the proximity state has completed a cycle since either an assertion of PEN or the last readout of PDATA. AVALID 6 ALS Valid. Indicates that the ALS state has completed a cycle since either an assertion of AEN or the last readout of at least one the CDATAL register. Reserved 5 Reserved. ASAT_DIGITAL 4 ALS Digital Saturation. Indicates that the maximum counter value has been reached. Maximum counter value depends on integration time set in the ATIME register. ASAT_ANALOG 3 ALS Analog Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the ALS analog circuit. PGSAT_ADC 2 Proximity ADC Saturation. Indicates that the maximum ADC value has occurred. PGSAT_REFLECTIVE 1 Proximity Reflective Saturation. Indicates that the intensity of reflected light has exceeded the maximum integration level for the proximity analog circuit. PGSAT_AMBIENT 0 Proximity Ambient Saturation. Indicates that the intensity of ambient light has exceeded the maximum integration level for the proximity analog circuit. Page 36 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Configuration Register Two (CFG2 0x9F) Figure 43: Configuration Register Two 7 6 5 4 3 2 PMASK_E PMASK_W PMASK_S PMASK_N AMASK 1 0 Reserved Field Bits PMASK_E 7 Proximity Mask East. Writing a 1 disables the East photodiode. PMASK_W 6 Proximity Mask West. Writing a 1 disables the West photodiode. PMASK_S 5 Proximity Mask South. Writing a 1 disables the South photodiode. PMASK_N 4 Proximity Mask North. Writing a 1 disables the North photodiode. AMASK 3 ALS Mask. Writing a 1 reduces the ALS gain by a factor of the ALS photodiode pixels. Only the center 2x2 array of pixels remains enabled out of the 4x4 array. Reduces ALS sensitivity for measurement of maximum ambient light levels. Reserved 2:0 ams Datasheet [v1-12] 2015-May-14 Description Reserved. Page 37 Document Feedback TMD4903 − Register Description IRBeam Configuration Register (ICONFIG 0xA0) Figure 44: IRBeam Configuration Register 7 6 Reserved 5 4 3 IIEN SLEW Reserved 2 1 0 ISQZT Field Bits Description Reserved 7:6 IIEN 5 IRBeam Interrupt Enable. When asserted permits IRBeam interrupts to be generated. SLEW 4 Slew Rate Control. Must be set to 1. Slew rate is used to maintain LED pulse symmetry. Reserved 3 Reserved Reserved IRBeam Symbol Quiet Zone Time. Defines the delay between symbols as a multiple of fundamental bit-times (IBT), calculated as follows: tISQZT = nISQZT X tIBT ISQZT Page 38 Document Feedback VALUE QUIET ZONE DURATION 0 0 bit-times (Not activated) 1 5 bit-times 2 9 bit-times … nISQZT = 2ISQZT + 1 + 1 6 129 bit-times 7 257 bit-times 2:0 ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description IRBeam Configuration Register Two (ICONFIG2 0xA1) Figure 45: IRBeam Configuration Register Two 7 6 Reserved 5 IINVERT Field Bits Reserved 7:6 IINVERT 5 4 3 IOUTPUT 2 1 0 IRCDCMODE IDUTY Description Reserved. IRBeam Invert. If asserted, the IRBeam output is inverted. IRBeam Output Pin. Define which output pin used for IRBeam. IOUTPUT IRCDCMODE VALUE IRBEAM OUTPUT PIN 0 LDR 1 LDR (digital mode) 2 INT 3 GPIO 4:3 2 IRBeam Remote Control DC Mode. If asserted, the pattern is transmitted in DC mode without carrier modulation. Timing is still defined by the IBT register. IRBeam Duty Cycle. Define the IRBeam duty cycle. IDUTY ams Datasheet [v1-12] 2015-May-14 VALUE IRBEAM DUTY CYCLE 0 50% 1 37.5% 2 25% 3 12.5% 1:0 Page 39 Document Feedback TMD4903 − Register Description IRBeam Symbol Looping Register (ISNL 0xA2) Figure 46: IRBeam Symbol Looping Register 7 6 5 4 3 2 1 0 ISNL Field ISNL Bits 7:0 Description IRBeam Symbol Looping. Sets the number of times that a Symbol is repeated in each Packet. A Symbol is a single IRBeam data transmission. The following equation describes the number of Symbols per Packet as a function of ISNL: nSymbol Repetitions = ISNL + 1 IRBeam Inter-Symbol OFF Register (ISOFF 0xA3) Figure 47: IRBeam Inter-Symbol OFF Register 7 6 5 4 3 2 1 0 ISOFF Field ISOFF Page 40 Document Feedback Bits Description 7:0 Inter-Symbol Delay Time. Defines the delay (LED OFF) between Symbols within Packets, tISDT, which can range from 4.25μs to 127.75μs. The minimum permitted register value is 8. The following equation describes the time delay as a function of ISOFF and IBT: tISDT = [(2 X ISOFF) + 1] X tIBT ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description IRBeam Packet Looping Register (IPNL 0xA4) Figure 48: IRBeam Packet Looping Register 7 6 5 4 3 2 1 0 IPNL Field IPNL Bits 7:0 Description IRBeam Packet Looping. Sets the number of times that a Packet is repeated. Each packet consists of repeated transmission of a Symbol. The following equation describes the number of Packet repetitions as a function of IPNL: nPacket Repetitions = IPNL + 1 IRBeam Inter-Packet OFF Register (IPOFF 0xA5) Figure 49: IRBeam Inter-Packet OFF Register 7 6 5 4 3 2 1 0 IPOFF Field IPOFF Bits 7:0 Description Inter-Packet Delay Time. Defines the delay (LED OFF) between Packet repetitions, tIPDT, which can range from 10μs to 255.25μs. The minimum permitted register value is 8. The following equation describes the time delay as a function of IPOFF and IBT: tISDT = [(2 X IPOFF) + 1] X tIBT ams Datasheet [v1-12] 2015-May-14 Page 41 Document Feedback TMD4903 − Register Description IRBeam Bit Time Register (IBT 0xA6) Figure 50: IRBeam Bit Time Register 7 6 5 4 3 2 Reserved 1 0 IBT Field Bits Reserved 7:6 Reserved. 5:0 IRBeam Bit Time. Defines the fundamental IRBeam bit-time, tIBT, which can range from 0.25μs to 64μs. The IRBeam bit time is set by the following equation: IBT Description tIBT = (IBT + 1) X 0.25μs IRBeam Symbol Length Register (ISLEN 0xA7) Figure 51: IRBeam Symbol Length Register 7 6 5 4 3 2 1 0 ISLEN Field ISLEN Bits Description 7:0 IRBeam Symbol Length. Defines the length of the IRBeam Symbol in bytes. The minimum length is 2 bytes, meaning the minimum register value is 1. The following equation describes the length of the Symbol in bytes: lSymbol = ISLEN + 1 Page 42 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description IRBeam Status Register (ISTATUS 0xA8) Figure 52: IRBeam Status Register 7 6 5 4 3 2 Reserved 1 0 IINT IBUSY Field Bits Description Reserved 7:2 IINT 1 IRBeam Interrupt. If IIEN is set, indicates that the device is asserting an end-of-transmission interrupt after transmitting a block of data. Bit is mirrored in the STATUS register. IBUSY 0 IRBeam Busy. Indicates an IRBeam transmission is in progress. Reserved. IRBeam Start Register (ISTART 0xA9) Figure 53: IRBeam Start Register 7 6 5 4 Reserved 3 2 1 0 ISTARTREMCON ISTARTMOBEAM Field Bits Reserved 7:2 ISTARTREMCON 1 IRBeam Start Remote Control. Write 1 to start the remote control machine, executing from address 0. Transmission can be stopped by writing a 0 to this bit. ISTARTMOBEAM 0 IRBeam Start mobeam. Write 1 to start a mobeam transmission. Transmission can be stopped by writing a 0 to this bit. ams Datasheet [v1-12] 2015-May-14 Description Reserved. Page 43 Document Feedback TMD4903 − Register Description Configuration Register Three (CFG3 0xAB) Figure 54: Configuration Register Three 7 6 5 4 Reserved LTF_USEPROX Reserved SAI Field Bits Reserved 7 3 2 1 0 Reserved Description Reserved. Use Proximity Photodiodes for ALS Measurement. Connects the IR-sensitive proximity photodiodes to the ALS engine in order to collect ALS data in the IR band. The data registers contain the following channel data depending on the LTF_USEPROX setting. 16-bit Output Registers LTF_USEPROX Reserved 6 5 LTF_USEPROX High Low 0 1 0x95 0x94 Clear North 0x97 0x96 Red South 0x99 0x98 Green West 0x9B 0x9A Blue East Reserved. Sleep After Interrupt. Powers down the device at the end of a proximity/ALS cycle if an interrupt has been generated. Note that SAI does not modify any register bits directly, it rather uses the interrupt signal to turn off the oscillator. The only way to "wake up" the device from SAI-sleep is by clearing the SAI_ACTIVE flag. SAI 4 PON SAI INT (Low Active) 0 Reserved Page 44 Document Feedback 3:0 Oscillator Off 1 0 On 1 1 1 On 1 1 0 Off (sleep after interrupt) Reserved. ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Configuration Register Four (CFG4 0xAC) Figure 55: Configuration Register Four 7 6 5 4 ALS_INT_ DIRECT ALS_INT_ DIRECT_GPIO PROX_INT_ DIRECT PROX_INT_ DIRECT_GPIO Field 3 2 1 0 Reserved Bits Description ALS_INT_DIRECT 7 ALS Interrupt Direct. If asserted, then the INT pin shows the ALS state directly and it is not necessary to clear the interrupt. If the CLEAR data exits the threshold range from within, the INT pin is asserted. The interrupt pin is de-asserted when the CLEAR data re-enters the threshold range. As long as the CLEAR data is within the thresholds, the INT pin is not asserted. ALS_INT_DIRECT_GPIO 6 ALS Interrupt Direct on GPIO Pin. If asserted, the GPIO pin shows the ALS interrupt state directly instead of the INT pin. This function operates in the same manner otherwise as ALS_INT_DIRECT. 5 Proximity Interrupt Direct. If asserted, then the INT pin shows the proximity state directly and it is not necessary to clear the interrupt. If PDATA crosses the upper threshold from below, the INT pin is asserted. The interrupt pin is only de-asserted when PDATA crosses the lower threshold from above. As long as PDATA is below the lower threshold, the INT pin is not asserted. PROX_INT_DIRECT_GPIO 4 Proximity Interrupt Direct on GPIO Pin. If asserted, the GPIO pin shows the proximity interrupt state directly instead of the INT pin. This function operates in the same manner otherwise as PROX_INT_DIRECT. Reserved 3:0 PROX_INT_DIRECT ams Datasheet [v1-12] 2015-May-14 Reserved. Page 45 Document Feedback TMD4903 − Register Description Configuration Register Five (CFG5 0xAD) Figure 56: Configuration Register Five 7 6 Reserved 5 4 3 2 1 0 LONG_LTFSTOP_ DISCARD_ALS Reserved DISABLE_IR_ CORRECTION PROX_FILTER_ DOWNSAMPLE PROX_FILTER_ SIZE PROX_ FILTER Field Bits Reserved 7:6 Description Reserved. LONG_LTFSTOP_DISCARD_ ALS 5 Long Disruption Discard ALS. Aborts ALS integration that is disrupted if the proximity state is entered (sensor field of view is obstructed) or an IRBeam transmission is executed (long disruption while LED is pulsed for an extended duration). Immediately after proximity mode is exited or IRBeam transmission is complete, a new ALS integration is started. When restarting ALS, this function ignores wait configuration, which may cause more ALS measurements to occur than expected. Reserved 4 Reserved. DISABLE_IR_CORRECTION 3 Disable IR Correction. Default is 1. If bit is 0, then calculate IR=(R+G+B-C)/2 and store R'=R-IR, G', B', and C' in the color DATA registers. 2 Proximity Filter Downsample. If PROX_FILTER = 1, then, if asserted, PDATA and proximity interrupt check are performed only every n proximity samples. If not asserted, then proximity filtering uses a moving window: PDATA is updated every cycle and proximity interrupt is checked every cycle. PROX_FILTER_ DOWNSAMPLE Proximity Filter Size. Determines the number of consecutive proximity samples to average to filter out noise. PROX_FILTER_SIZE PROX_FILTER Page 46 Document Feedback 1 0 VALUE FILTER 0 2 samples Proximity Filter. If asserted, enables proximity filter functionality. Depending on PROX_FILTER_SIZE, 2 or 4 consecutive proximity samples are averaged. ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Status Register Three (STATUS3 0xB3) Figure 57: Status Register Three 7 6 5 4 3 2 Reserved Field Bits Reserved 7:2 1 0 SAI_ACTIVE Reserved Description Reserved. SAI_ACTIVE 1 Sleep-After-Interrupt Active. If SAI is set, indicates that the oscillator has been stopped and the device is in sleep after an interrupt. SAI_ACTIVE must be cleared (CONTROL 0xBC[0]: CLEAR_SAI_ACTIVE) to clear SAI and resume chip operation. Reserved 0 Reserved. Control Register (CONTROL 0xBC) Figure 58: Control Register 7 6 5 4 3 2 1 Reserved Field Bits Reserved 7:1 SAI_ACTIVE_CLEAR ams Datasheet [v1-12] 2015-May-14 0 0 SAI_ACTIVE_CLEAR Description Reserved. Sleep-After-Interrupt Active Clear. If SAI is set and SAI_ACTIVE is true (an Interrupt has occurred), asserting this pin clears the SAI_ACTIVE flag and restarts the device oscillator to resume chip operation if functions are enabled. Page 47 Document Feedback TMD4903 − Register Description Auxiliary ID Register (AUXID 0xBD) Figure 59: Auxiliary ID Register 7 6 5 4 3 Reserved 2 1 0 AUXID Field Bits Description Reserved 7:4 Reserved. AUXID 3:0 Auxiliary ID. Value is 0000. Proximity Offset Registers (0xC0 − 0xC7) Proximity offset values have a range of ±255 and are expressed as 9-bit two’s-complement values. Do not program values outside of this range. Only the lower 9 bits are significant, but the high byte must only be programmed with values of 0x00 (indicates that the low byte has a positive value) or 0xFF (indicates that the low byte has a negative value). Figure 60: Proximity Offset Registers Field Register Bits Description 0xC0 7:0 North channel offset low byte 0xC1 15:8 North channel offset high byte 0xC2 7:0 South channel offset low byte 0xC3 15:8 South channel offset high byte 0xC4 7:0 West channel offset low byte 0xC5 15:8 West channel offset high byte 0xC6 7:0 East channel offset low byte 0xC7 15:8 East channel offset high byte OFFSETN OFFSETS OFFSETW OFFSETE Page 48 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Autozero Configuration Register (AZ_CONFIG 0xD6) Figure 61: Autozero Configuration Register 7 6 5 4 3 2 1 0 AZ_NTH_ITERATION Field Bits Description ALS Autozero Frequency. Sets the frequency at which the device performs autozero of the ALS pulse counter. AZ_NTH_ITERATION VALUE AUTOZERO FREQUENCY 0 Never 1 Every cycle 2 Every 2 cycles … Every (AZ_NTH_ITERATION) cycles 253 Every 253 cycles 254 Every 254 cycles 255 Only once (before 1st cycle) 7:0 Calibration Register (CALIB 0xD7) Figure 62: Calibration Register 7 6 5 4 3 2 Bits Reserved 7:1 START_OFFSET_ CALIB ams Datasheet [v1-12] 2015-May-14 0 0 START_OFFSET _CALIB Reserved Field 1 Description Reserved. Start Offset Calibration. Starts the proximity offset register calibration routine. Results are stored in the Proximity Offset Registers (0xC0 – 0xC7). The CALIB_FINISHED flag is asserted when calibration is complete and an interrupt (CINT) is asserted if CIEN is set. Calibration can be stopped by writing a 0 to this field. Page 49 Document Feedback TMD4903 − Register Description Calibration Configuration Register Zero (CALIBCFG0 0xD8) Figure 63: Calibration Configuration Register Zero 7 6 5 4 3 2 Reserved DCAVG_ AUTO_OFFSET_ ADJUST Reserved ELECTRICAL_ CALIBRATION BINSRCH_ SKIP 1 0 DCAVG_ITERATIONS Field Bits Reserved 7 Reserved. DCAVG_AUTO_OFFSET_ADJUST 6 DC Averaging Auto Offset Adjust. If set, then during DC averaging, whenever an ADC measurement is zero, the appropriate offset register will be decreased and the OFFSET_ADJUSTED flag is set. Note also that DC averaging is not automatically restarted when this happens, so the calculated baseline might be wrong. Software could restart averaging in this case. Reserved 5 Reserved. 4 Enable Electrical Calibration. When asserted the calibration routine will perform an internal electrical calibration to adjust the proximity offset registers to remove electrical crosstalk – there is no optical response at all for this routine. When not asserted, calibration will measure both optical and electrical crosstalk during calibration. 3 Binary Search Skip. When asserted the calibration routine will skip the binary search step. It is useful if zeroes are detected during the DC averaging process to manually reset the baseline and reduce the likelihood of zero counts. ELECTRICAL_CALIBRATION BINSRCH_SKIP Page 50 Document Feedback Description ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Field Bits Description DC Averaging Iterations. Sets the number of proximity results during calibration that are averaged after the binary search is complete. During this period, whenever a result is zero, the appropriate offset register is automatically decremented. The default value is 4 (16 iterations). DCAVG_ITERATIONS ams Datasheet [v1-12] 2015-May-14 VALUE SAMPLES 0 Skip 1 2 2 4 … nIterations = 2DCAVG_ITERATIONS 6 64 7 128 2:0 Page 51 Document Feedback TMD4903 − Register Description Calibration Configuration Register One (CALIBCFG1 0xD9) Figure 64: Calibration Configuration Register One 7 6 PXDCAVG_ AUTO_ GTHR PROX_ AUTO_OFFSET_ ADJUST Field 5 4 3 2 PXDCAVG_ AUTO_ BASELINE Reserved 1 0 PXDCAVG_BASELINE_WINDOW Bits Description 7 Proximity Automatic Thresholds. When asserted, GTHR_IN and GTHR_OUT are automatically written with a multiple of the PBSLN every time PBSLN changes. The multiplication factor is set in AUTO_GTHR_IN_MULT. PBSLN can only change if PXDCAVG_AUTO_BASELINE is asserted and PBSLN_MEAS is less than PBSLN. PROX_AUTO_OFFSET_ADJUST 6 Proximity Auto Offset Adjust. If set, then during proximity/gesture mode, whenever an ADC measurement is zero, the appropriate offset register will be decreased. Will set the OFFSET_ADJUSTED flag if it happens. Reserved 5:4 PXDCAVG_AUTO_GTHR PXDCAVG_AUTO_BASELINE 3 Reserved. Proximity Automatic Baseline. When asserted, PBSLN_MEAS is written to PBSLN whenever PBSLN_MEAS is less than PBSLN. When this happens, the BASELINE_ADJUSTED flag is raised. The default value is 1. Prox Baseline Averaging Window. Sets the number of proximity samples averaged to calculate PBSLN_MEAS, which is updated at the end of each window. The default value is 16 samples. PXDCAVG_BASELINE_WINDOW Page 52 Document Feedback 2:0 VALUE SAMPLES 0 Skip 1 2 2 4 … nIterations = 2PXDCAVG_BASELINE_WINDOW 6 64 7 128 ams Datasheet [v1-12] 2015-May-14 TMD4903 − Register Description Interrupt Enable Register (INTENAB 0xDD) Figure 65: Interrupt Enable Register 7 6 5 4 3 2 1 0 ASIEN PGSIEN PIEN AIEN IIEN Reserved CIEN Reserved Field Bits ASIEN 7 ALS Saturation Interrupt Enable. When asserted permits ALS saturation interrupts to be generated. Bit is mirrored in the CFG1 register. PGSIEN 6 Proximity Saturation Interrupt Enable. When asserted permits proximity saturation interrupts to be generated. Bit is mirrored in the CFG1 register. PIEN 5 Proximity Interrupt Enable. When asserted permits proximity interrupts to be generated, subject to the proximity thresholds and persistence filter. Bit is mirrored in the ENABLE register. AIEN 4 ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the ALS thresholds and persistence filter. Bit is mirrored in the ENABLE register. IIEN 3 IRBeam Interrupt Enable. When asserted permits IRBeam interrupts to be generated. Bit is mirrored in the ICONFIG register. Reserved 2 Reserved. Bit must be set to 0. CIEN 1 Calibration Interrupt Enable. When asserted permits calibration interrupts to be generated. Reserved 0 Reserved. ams Datasheet [v1-12] 2015-May-14 Description Page 53 Document Feedback TMD4903 − Register Description Interrupt Clear Register (INTCLEAR 0xDE) Figure 66: Interrupt Clear Register 7 6 5 4 3 2 1 0 INTCLEAR_ ASAT INTCLEAR_ PGSAT INTCLEAR_ PINT INTCLEAR_ AINT INTCLEAR_ IINT Reserved INTCLEAR_ CINT Reserved Field Bits INTCLEAR_ASAT 7 Clear Interrupt: Analog Saturation. Clears the analog saturation interrupt. INTCLEAR_PGSAT 6 Clear Interrupt: Proximity Saturation. Clears the proximity saturation interrupt. INTCLEAR_PINT 5 Clear Interrupt: Proximity. Clears the proximity interrupt. INTCLEAR_AINT 4 Clear Interrupt: ALS. Clears the ALS interrupt. INTCLEAR_IINT 3 Clear Interrupt: IRBeam. Clears the IRBeam interrupt. Reserved 2 Reserved. Bit must be set to 0. INTCLEAR_CINT 1 Clear Interrupt: Calibration. Clears the calibration interrupt. Reserved 0 Reserved. Page 54 Document Feedback Description ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Application Information Figure 67: TMD4903 Typical Application Circuit VBUS VDD VDD VLED VLED 22 VDD 4.7µF GND SCL SDA ams Datasheet [v1-12] 2015-May-14 LEDA " % LDR $ ! & # ( 1µF >4.7µF INT GPIO ' Page 55 Document Feedback TMD4903 − Application Information Figure 68: TMD4903 Recommended Circuit Layout Note(s) and/or Footnote(s): 1. For best performance, all components should be positioned as close as possible to the TMD4903. Traces and vias should be as large as possible. The proximity of the capacitors is most important. Page 56 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Remote Control General Description of RC Functionality The TMD4903 is equipped with Remote Control functionality which is used to generate and transmit patterns over IR for electronic equipment (E.g. television, DVD, or audio receiver). Virtually all protocols can be accommodated by the specialized architecture of the Remote Control engine. The engine contains 256 bytes of pattern RAM and controls for carrier frequency, duty cycle and pattern repetition to easily create and broadcast a complete command waveform. The command waveform is output on a device pin allowing direct control of an external transistor and LED (pull-up resistor required). The integrated LED may also be used to output the IR waveform. Detailed Description of RC Functionality Remote Control functionality uses a digital core that is independent of the analog sensor operation. The logic internal to the digital core is activated when IBEN=1. In this operational mode the LDR pin is exclusively acquired; during this time sensor functionality will not operate. Most of the functional engines are controlled by dedicated registers; however, some devices use a “shared register” scheme. For example, this device uses address space: 0xA0 to 0xAF to also control mobeam operation. Because each functional block serves a different purpose and utilizes common on-chip resources, only one may be activated at a time. ams Datasheet [v1-12] 2015-May-14 Page 57 Document Feedback TMD4903 − Application Information Block Diagram of Remote Control Functionality Figure 69: Block Diagram of RC Functionality VDD VDD OSCILLATOR SCL SDA I2C 256 X 8-bit Pattern RAM Sensor Engines 16 X 16-bit Time Word RAM INT Control Registers INT Flags LEDA LDR Remote Control Engine GPIO Digital Core GND TMD4903 Block Diagram of RC Functionality: Resources associated with Remote Control. There are many different remote control protocols currently in use; and to meet the multitude of requirements the remote control engine has been designed to be flexible. The remote control engine consists of four major components: Pattern RAM, Timeword RAM, control registers, and pattern output pin (or integrated LED). Page 58 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Pattern RAM The Pattern RAM is 256 bytes in length and is divided into two banks with 128 bytes each. Both banks must be used to enable all Pattern RAM. To access the Pattern RAM, write 0 or 1 to RAM_BANK (0x8D<0>). Functionally, the RAM is split into the MSB and LSB nibbles; each of which are used to index the Timeword RAM table. The MSB is used for “pulses”, and the LSB is used for “gaps”. Figure 70: Terminology of Pattern RAM Terminology Pulse First of Repeat part Second of Repeat part LED Modulation Gap “Single” sub-pattern “Repeated” sub-pattern “Complete” Pattern Terminology of Pattern RAM: Pulses/Gaps, and Single/Repeated/Complete Patterns are shown. The pulse-gap pair defines when the LED is modulating or deactivated, respectively. The control logic processes the RAM locations sequentially until special operator values are encountered. ams Datasheet [v1-12] 2015-May-14 Page 59 Document Feedback TMD4903 − Application Information Figure 71: Pattern RAM Table Pattern RAM Address (Bank 0) Data (Pulse-Gap) 0 0x0 to 0xFF 1 0x0 to 0xFF 2 0x0 to 0xFF 3 0x0 to 0xFF ~ ~ 255 0x0 to 0xFF Pattern RAM: Volatile memory used for storing pattern data. Note(s) and/or Footnote(s): 1. T_DATA = 0xFE is a special instruction. The following value in RAM becomes the start address of any repeated sub-pattern. 2. T_DATA = 0xFF is a special instruction. It identifies the end of the pattern. There are two special values that control the flow of the pattern: Stop and Repeat-destination. A Stop is signified by the value of 0xFF loaded into a pattern ram location. The value is analogous to a null character at the end of a text file. Any remaining RAM after the 0xFF operator is encountered is not executed and the pattern is finished. The Repeat-destination operator is signified by a value of 0xFE followed by the start address of any repeated sub-pattern. This value is analogous to a “goto” statement. Once this value is encountered instruction pointer to the pattern RAM is changed to the address stored in the next pattern RAM location. These data values will not be decoded by the logic as a reference/pointer to the timeword table, that is, 0xFF will not index timeword location 15 for pulse and gap. Page 60 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Timeword RAM The Timeword RAM is a dedicated table that contains sixteen, 16-bit words which are used to set pulse and gap widths. The pulse and gap widths are described as a multiple of carrier periods, TCAR. For example, if the LED must modulate for 8 carrier periods, then be off for 15 carrier periods, index 0 could be loaded with 0x0008 and index 1 could be loaded with 0x000F. A pattern RAM value of 0x01 would result in LED activation for 8 TCARs, as stored in index 0, and a LED deactivation for 15 TCARs. Similarly to pattern RAM, the Timeword table also has a special operator. If the timeword value is zero, then whatever state the LED was in last (I.e. modulating or deactivated) will be continued into the next pulse or gap defined in pattern RAM. For example, if the RAM Pulse nibble (MSB) indexes a timeword set to 5, and the gap (LSB) nibble indexes a timeword set to 0, the LED will modulate for 5TCARs then instead of deactivating, the modulation is continued into the next pulse in pattern RAM. In this way pulses or gaps longer than 65535 TCAR s can be generated. Figure 72: Timeword RAM Table Timeword RAM I2C Address (Bank 1) T_INDEX T_DATA 0 0 to 65535 0x01 8-bit MSB 0x00 8-bit LSB 1 0 to 65535 0x03 8-bit MSB 0x02 8-bit LSB 2 0 to 65535 0x05 8-bit MSB 0x04 8-bit LSB 3 0 to 65535 0x07 8-bit MSB 0x06 8-bit LSB ~ ~ ~ ~ 15 0 to 65535 0x0F 8-bit MSB 0x1E 8-bit LSB Timeword RAM: Volatile memory used for storing 16-bit timing data. The Timeword table is located in RAM bank two. Each 16-bit word is accessible using two byte locations: MSB bytes are stored in even addresses and LSBs are stored in odd addresses. For example, if 0x2953 is to be stored at index 0, then 0x29 is written to: bank 2, I²C address of 0x00, and 0x53 is written to bank 2, I²C address of 0x01. ams Datasheet [v1-12] 2015-May-14 Page 61 Document Feedback TMD4903 − Application Information Control Registers The remote control engine has 19 fields that govern pattern timing and flow, output selection, and report status. All pertinent fields are listed in the figure below. Figure 73: Remote Control Registers and Fields Register / Bit Address Description ENABLE<PON> 0x80<0> Power On ENABLE<IBEN> 0x80<7> IRBeam Enable CFG0 <RAM_BANK> 0x8D<0> RAM Bank Select PGCFG1 <PGLDRIVE> 0x8F<4:0> LED Drive Strength STATUS <IINT> 0x93<3> IRBeam Interrupt (mirrors ISTATUS<IINT>) ICONFIG <IIEN> 0xA0<5> IRBeam Interrupt Enable ICONFIG2 <IINVERT> 0xA1<5> IRBeam Polarity Inversion ICONFIG2 <IOUTPUT> 0xA1<4:3> ICONFIG2 <IRCDCMODE> Output Select 0xA1<2> DC Carrier Select ICONFIG2 <IDUTY> 0xA1<1:0> Duty Cycle Select ISNL <ISNL> 0xA2<7:0> Number of Repeated Sub-pattern Loops ISOFF <ISOFF> 0xA3<7:0> Pause between Sub-pattern Bursts IPNL <IPNL> 0xA4<7:0> Number of Complete Pattern Loops IPOFF <IPOFF> 0xA5<7:0> Pause between Pattern Bursts IBT <IBT> 0xA6<5:0> Carrier Selection Time ISTATUS <IINT> 0xA8<1> IRBeam Interrupt ISTATUS <IBUSY> 0xA8<0> IRBeam Busy ISTART <ISTARTREMCON> 0xA9<1> Remote Control Start Pattern Burst INTCLEAR <INTCLEAR_IINT> 0xDE<3> IRBeam Interrupt Clear Pertinent Control Registers: Resources associated with Remote Control. Page 62 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Carrier frequency, Duty cycle, and Pause (the delay between complete patterns) comprise the registers associated with timing. Carrier periods are selectable in 250ns increments in with register settings in the range of 8 to 255. Carrier frequencies are in the range of 16 kHz to 460 kHz. Typical carrier frequencies are listed in the table below. Protocols that do not use carriers can also be accommodated by enabling the DC Carrier Selection bit. The duty cycle of the carrier is selectable as: 50%, 37%, 25%, and 12%. Note that these duty cycles do not translate exactly to the actual LED duty cycle, depending on the external circuit. Finally, if desired, complete pattern rebursts are separated by a selectable delay of 0us to 2.55s, in 10us increments. Figure 74: Carrier Frequencies Desired Frequency (kHz) Generated Frequency (kHz) IBT 36 36.04 111 38 38.10 105 40 40.00 100 56 56.34 71 450 444.44 9 Carrier Frequencies: Typical carrier frequencies can be reproduced to closely match the desired value. Controls associated with the output are: Output select, Output Polarity Inversion, and LED Drive Strength. Output Select is used to choose output on the integrated LED or the GPIO pin. The polarity inversion control inverts the waveform on both the LED and the GPIO pin if enabled. The LED Drive Strength controls the current through the integrated LED which effectively sets its intensity. Controls associated with interrupts are: Pattern Burst Interrupt Enable, Pattern Burst Interrupt flag, Pattern Burst Interrupt Clear, Pattern Burst Interrupt Force, and Pattern Burst Busy. Following an entire pattern burst, including all repeats, loops, and delays, a pattern burst interrupt bit is set. This bit is readable from two locations: STATUS register and ISTATUS register. If the interrupt enable bit is set, then the INT pin will also activate when the burst is finished. To clear the interrupt, the host must write a zero to IRBeam Interrupt Clear (0xDE<3>). For debugging purposes the interrupt bits and pin can be forced to activate by setting the Pattern Burst Interrupt Force bit. The Pattern Burst Busy bit is automatically set whenever a pattern is actively being transmitted; it is reset once the remote control engine returns to the IDLE state. ams Datasheet [v1-12] 2015-May-14 Page 63 Document Feedback TMD4903 − Application Information Controls associated to define the number of complete pattern loops and sub-pattern repeats are: Number of Repeated Sub-pattern Loops and Number of Complete Pattern Loops. As depicted below, the number of “run-once” pattern loops sets the amount of additional iterations, up to 254. If the register is set to 0xFF then the sub-pattern is continuously repeated until the value is changed or IBEN bit is reset. Figure 75: Complete Pattern Loops Protocols with No Repeated Sub-Patterns IDLE START Loop IPNL Times “Run-once” Subpattern Pause IDLE Complete Pattern Loops: The red box represents a “run-once” pattern. The pattern begins at pattern ram address 0x00 and bursts until the end of the pattern is encountered. The complete pattern can be reiterated 1 to 254 times, or continuously. As depicted below, the number of repeated sub-pattern loops sets the amount of additional “repeated part” burst iterations, up to 254. If the register is set to 0xFF then the sub-pattern is continuously repeated until the value is changed or IBEN bit is reset. Page 64 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Figure 76: Number of Repeated Sub-Pattern Loops Protocols with Repeated Sub-Patterns Loop IPNL Times Loop ISNL Times IDLE START “Run-once” Subpattern Repeat Subpattern Pause IDLE Protocols with “Repeated” Sub-Patterns: The blue box represents a repeated part of a pattern. These sub-patterns begin at an address within the red box and burst until the end of the pattern is encountered. The repeated sub-pattern can be reiterated 1 to 254 times, or continuously. Digital Logic The Simplified Flow Diagram depicts the basic premise of how an entire waveform is generated. Protocols of the form described in Figure 75 and Figure 76 can be generated using the mechanism depicted below. Any functionality show in the red, blue, or green boxes can be activated or omitted via control register settings or special operators in pattern RAM to produce virtually any waveform. Typically, patterns are built by assembling pulses and gaps in a particular order. To this end the length of time for each pulse and gap, measured in multiples of carrier periods, as well as the order of each pulse/gap pair are specified in the equipment/button data. The remote control engine can directly accept the data in this format. Pulse/Gap order is stored in pattern RAM and pulse/gap time durations are stored in the Timewords table. ams Datasheet [v1-12] 2015-May-14 Page 65 Document Feedback TMD4903 − Application Information Figure 77: Simplified Flow Diagram IDLE N Simplified Flow Diagram for Remote Control (With Repeated Sub-Pattern) START ? Y Set RAM Address to 0x00 Set RAM Address to “Repeated” Start Location Burst “Pulse” for x Carrier Periods (LED ON) Burst “Pulse” for x Carrier Periods (LED ON) Burst “Gap” for y Carrier Periods (LED ON) Delay (0ms to 2.55s) Burst “Gap” for y Carrier Periods (LED ON) At the END of Pattern ? N Go to next RAM location Decrement Loop Counter Decrement Repeat Counter Y N N At the END of Pattern ? N Y Done Repeating ? Y Done Looping ? Y Interrupt Go to next RAM location IDLE Simplified Flow Diagram: The digital logic in the remote control engine has been tailored to fit the data format and protocol specifications for IR remote control. “Press and Release” type buttons (E.g. Power) are generated using the logic in the red box (logic in the blue box is not needed). “Press and Hold” type buttons (E.g. Volume+) are generated using logic in both the red and blue boxes. Page 66 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information The digital logic in the remote control engine has been tailored to fit the data format and protocol specifications for IR remote control. “Press and Release” type buttons (E.g. Power) are generated using the logic in the red box. “Press and Hold” type buttons (E.g. Volume+) are generated using logic in both the red and blue boxes. Figure 78 depicts how a command pattern with a repeated sub-pattern is created using the logic shown in the Simplified Flow Diagram. All of the “run-once” sub-pattern and the “first” instance of the “repeated” sub-pattern is actually run by the logic in the red box. The second instance of the “repeated” sub-pattern is run by the logic in the blue box. Figure 78: Pattern Generation by Logical Block Pattern Generation by Digital Logic Block Second of Repeat part LED Modulation First of Repeat part Generated by “red box logic” Generated by “blue box logic” “Complete” Pattern Pattern Generation: All of the “one-time” sub-pattern and the “first” instance of the “repeated” sub-pattern is actually run by the logic in the red box. The second instance of the “repeated” sub-pattern is run by the logic in the blue box. ams Datasheet [v1-12] 2015-May-14 Page 67 Document Feedback TMD4903 − Application Information Complete patterns can also be automatically reburst from 1 to 254 times or continuously. Complete patterns can also be separated by a pause, or time delay, as generated by the logic in the green block. The entire pattern consists of a multiple of complete patterns and pause delays. During this length of time the entire pattern is bursting the IBUSY bit is set. Upon completion the IBUSY bit is cleared and the interrupts are set. Figure 79: Entire Pattern Waveform Entire Pattern Waveform Pause Pause Pause “Entire” Pattern Entire Pattern: Complete patterns can also be separated by a pause, or time delay, as generated by the logic in the green block. The entire pattern consists of a multiple of complete patterns and pause delays. During the length of time the entire pattern is bursting, the PBUSY bit is set. Refer to the Remote Control Engine diagram which depicts the how the engine functions in great detail. Page 68 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Figure 80: Detailed Flow Diagram of the Remote Control Engine START Output Pattern PBEN = 1 IDLE Remote Control Engine START ? Y Start Get MSB Nibble from RAM Data (RDATA-MSBn) IBUSY = 1 COUNTERW = IPNL TIME_INDEX = MSB NIBBLE COUNTERR = ISNL Pause (if any) RAM_ADDRESS = 0 Get RAM Data Byte (RDATAn) N Start RDATAn == 0xFE && COUNTERR >=0 ? Y TDATAMSB == 0 ? Y RAM_ADDRESS = START LOCATION OF REPEATED PATTERN TIMERP = IPOFF Pause (if any) N COUNTERW-- N Activate Modulated Output N Y TIMERP > 0 Have TDATAMSB carrier periods been output ? Y RDATAn == 0xFF ? Y COUNTERW > 0 ? N N Get LSB Nibble from RAM Data (RDATA-LSBn) Y Delay 10us TIME_INDEX = LSB NIBBLE Output Pattern IBUSY = 0 IINT = 1 TIMERP-- TDATALSB == 0 ? Exit COUNTERR < 255 ? N Y N IIEN == 1 ? Deactivate Modulated Output N Y Y COUNTERR-- ASSERT INT PIN N RAM_ADDRESS++ Done Repeated Sub-Pattern Complete Waveform Have TDATALSB carrier periods been output ? Y Exit Remote Control Engine: Complete guide to the inner workings and use of the remote control functionality. ams Datasheet [v1-12] 2015-May-14 Page 69 Document Feedback TMD4903 − Application Information Electrical and Optical Output The electrical or optical output of the remote control engine can be realized in three ways: use of the integrated top-facing LED, use of the LDR pin to directly drive an external LED, or use of the GPIO pin to drive an external FET and IR LED. The LDR pin has a regulated current sink with selectable drive value. This is an attractive way to use an external LED without having an additional LED drive FET. If this method is to be used, then LEDA must be disconnected from the circuit. Since the cathode of the integrated LED is connected to the LDR pin internal to the module any current that is sourced through LEDA will reduce the current available on the external remote control LED. When the remote control functionality is not used the external LED must be electrically disconnected from the LDR pin to prevent it from illuminating. Figure 81: External IR LED Using the LDR Pin VLED VBUS VDD VDD 1µF GND SCL SDA VDD µP 22Ω µP 4 LEDA 1 3 VLED 6 GPIO TMD4903 7 2 5 1µF >4.7µF INT LDR 8 Remote Control Circuit Option #1 Recommended Connection: Option number one. If the LDR pin is not used as the pattern output, the GPIO pin can be used. With this method both the LEDA and external remote control IR LED may remain connected to the LED power supply, but an additional FET is needed to drive the remote control LED. Page 70 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Figure 82: External IR LED Using the GPIO Pin VBUS VDD VDD VLED 22Ω VDD 1µF GND SCL SDA 1 1µF 5 LDR 3 VLED 4 LEDA TMD4903 7 2 6 >4.7µF INT GPIO 8 Remote Control Circuit Option #2 Recommended Connection: Option number two. Example Waveform and Device Setup A practical example is included to describe how each register is used and how to setup the device to burst a real waveform. The physical waveform, as seen on an oscilloscope, is described by the depiction in Figure 80. The Figure 83 depicts the mechanics to precondition the remote control engine for proper operation. ams Datasheet [v1-12] 2015-May-14 Page 71 Document Feedback TMD4903 − Application Information Figure 83: Practical Example Example 1. Carrier Frequency: 38kHz (TCAR = 26us) Time Words Table 2. Duty Cycle = 25% 3. Non-repeat count=5 (LED ON-LED OFF) 334-177, 22-22, 22-60, 60-22, 22-1541 4. Repeat count=2 (LED ON-LED OFF) 334-88 22-3694 Run 2 times 5. Repeat compete pattern 3 times. 6. Delay 100us between complete patterns. Pattern Table ADDRESS T_DATA 0 0x01 x01 1 2 0x22 0x23 3 0x32 32 4 5 0x24 0x05 6 7 8 9 0x26 0xFE 0x05 x05 0xFF T_INDEX T_DATA 0 1 2 3 4 5 6 334 177 22 60 1541 88 3694 0x01, 0x01 0x03, 0x00 0x05, 0x00 0x07, 0x00 0x09, 0x06 0x0B, 0x00 0x0D, 0x0E 0x00, 0x4E 0x02, 0xB1 0x04, 0x16 0x06, 0x3C 0x08, 0x05 0x0A, 0x58 0x0C, 0x6E MSB points to index 0. Index 0 data is 334. LED will be on for 334 X TCAR IDLE START LED ON for 344 TCAR LED OFF for 177 TCAR LED ON for 22 TCAR LED OFF for 22 TCAR LED ON for 22 TCAR LED OFF for 60 TCAR LED ON for 60 TCAR LED OFF for 22 TCAR LED ON for 22 TCAR LED OFF for 1541 TCAR LED ON for 334 TCAR LED OFF for 88 TCAR LED ON for 22 TCAR LED OFF for 3694 TCAR LED ON for 334 TCAR LED OFF for 88 TCAR LED ON for 22 TCAR LED OFF for 3694 TCAR LED ON for 334 TCAR LED OFF for 88 TCAR LED ON for 22 TCAR LED OFF for 3694 TCAR Delay 100us LSB points to index 2. Index 2 data is 22. LED will be off for 22 X TCAR Byte following “0xFE” becomes the starting address of the repeated pattern. STOP LEDON for 572us LEDOFF for 96ms Carrier Frequency: IBT = 0x68 (26us/250ns) Duty Cycle: ICONFIG2 = 0x02 “Repeated sub-pattern” Repeat count=2: ISNL = 0x01 “Complete sub-pattern” Repeat count=3: IPNL = 0x02 Delay 100us between complete patterns: IPOFF = 0x0A (100us/10us) To run two times, must repeat once. To run complete pattern three times, must repeat twice. Pattern Delay 100us Pattern Delay 100us START: Write a 0x02 to ISTART. Output: I2C Address, Data IDLE Pause Pause Pause Practical Example: Device registers and RAM are loaded with values to generate a real remote control waveform. Page 72 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Application Information Protocol Accommodation Checklist The Remote Control pattern generation/transmission feature can be configured to broadcast virtually all IR communication protocols used for commanding consumer electronic devices. There are many different remote control protocols currently in use; and to meet the multitude of requirements the remote control engine has been designed to be flexible. In general, a protocol functions within the following transmission specifications can be accommodated: • Carrier periods are selectable in 250ns increments. Carrier frequencies are in the range of 15.625 kHz to 460 kHz. Protocols that do not use carriers can also be accommodated. • Duty cycle of the carrier is selectable: 50%, 37%, 25%, and 12%. Exact LED duty cycle depends on the external circuit. • Pulse (LED on) and Gap (LED off) widths are a multiple of carrier periods (TCAR). Pulse and Gap length is selectable from 0 to 65535 carrier periods. Patterns with exceptionally long pulses or gaps (I.e. longer than 65535 carrier periods) may be accommodated. This requires setting contiguous pattern ram locations, but results in a glitch-free long pulse/gap. • A dedicated “time word” RAM table contains sixteen, 16-bit words which are used to set pulse and gap widths. Simply stated, a pattern must contain sixteen or fewer unique pulse/gap widths. Note: patterns containing more than 16 unique pulse/gap widths may be accommodated by using the 16-bit timewords as “building blocks” to form longer pulse/gaps. For example, if a pattern has a pulse/gap of both 3T CAR and 6T CAR, then only the 3T CAR need be represented in the Time Word table; then the 6TCAR can be generated by indexing into the 3TCAR twice (This requires the use of additional pattern RAM). • A dedicated “pattern” RAM contains 256 bytes of data. Each byte indexes into the Timeword table to form a complete pulse and gap pair. A pattern that does not contain a “repeated” sub-pattern must have 255 or fewer pulse/gap pairs. A pattern that contains a “repeated” sub-pattern must have 254 or fewer pulse/gap pairs, not including the additional repetitions of the “repeated” sub-pattern. • Entire patterns can be reburst up to an additional 255 times and are separated by a selectable delay of 0us to 2.55s, in 10us increments. ams Datasheet [v1-12] 2015-May-14 Page 73 Document Feedback TMD4903 − Package Drawings & Markings Package Drawings & Markings Figure 84: TMD4903 Module Dimensions 7239,(: /(' '(7(&725 3,1 6,'(9,(: %277209,(: ; ; ; ; ; RoHS Green ; Note(s) and/or Footnote(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. Contacts are copper with NiPdAu plating. 4. This package contains no lead (Pb). 5. This drawing is subject to change without notice. 6. Measurement guarantee by lot acceptance testing using 20 units. Page 74 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − PCB Pad Layout PCB Pad Layout Suggested PCB pad layout guidelines for the surface mount module are shown. Flash Gold is recommended as a surface finish for the landing pads. Figure 85: Recommended PCB Pad Layout ; ; ; ; ; ; ; Note(s) and/or Footnote(s): 1. All linear dimensions are in millimeters. 2. Dimension tolerances are ±0.05mm unless otherwise noted. 3. This drawing is subject to change without notice. ams Datasheet [v1-12] 2015-May-14 Page 75 Document Feedback TMD4903 − Mechanical Data Mechanical Data Figure 86: Tape and Reel Mechanical Drawing Note(s) and/or Footnote(s): 1. All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001. 4. Each reel is 330 millimeters in diameter and contains 5000 parts. 5. ams packaging tape and reel conform to the requirements of EIA Standard 481−B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Page 76 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Soldering & Storage Information Soldering & Storage Information Soldering Information The module has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 87: Solder Reflow Profile Parameter Reference Average temperature gradient in preheating Device 2.5 °C/sec tsoak 2 to 3 minutes Time above 217 °C (T1) t1 Max 60 sec Time above 230 °C (T2) t2 Max 50 sec Time above Tpeak – 10 °C (T3) t3 Max 10 sec Tpeak 260 °C Soak time Peak temperature in reflow Temperature gradient in cooling Max -5 °C/sec Figure 88: Solder Reflow Profile Graph NottoScale Tpeak T3 T2 Temperaturein°C T1 Timeinseconds ams Datasheet [v1-12] 2015-May-14 t3 t2 Page 77 Document Feedback TMD4903 − Soldering & Storage Information Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions: • Shelf Life: 12 months • Ambient Temperature: <40°C • Relative Humidity: <90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Floor Life The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions: • Floor Life: 168 hours • Ambient Temperature: <30°C • Relative Humidity: <60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours. Page 78 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Ordering & Contact Information Ordering & Contact Information Figure 89: Ordering Information Ordering Code Address Interface Delivery Form TMD49033 0x39 I²C bus = 1.8V Interface Tape & Reel TMD49037 (1) 0x29 I²C bus = 1.8V Interface Tape & Reel Note(s) and/or Footnote(s): 1. Contact ams for availability. Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: [email protected] For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com ams Datasheet [v1-12] 2015-May-14 Page 79 Document Feedback TMD4903 − RoHS Compliant & ams Green Statement RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Page 80 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. ams Datasheet [v1-12] 2015-May-14 Page 81 Document Feedback TMD4903 − Document Status Document Status Document Status Product Preview Preliminary Datasheet Datasheet Datasheet (discontinued) Page 82 Document Feedback Product Status Definition Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs ams Datasheet [v1-12] 2015-May-14 TMD4903 − Revision Information Revision Information Changes from 1-11 (2015-Apr-23) to current revision 1-12 (2015-May-14) Page Updated Section title Updated text under General Description 1 Updated Figure 1 2 Updated Applications 2 Updated Figure 2 3 Updated Figure 4 4 Updated Figure 5 5 Updated Figure 10 9 Updated title of Figure 20 14 Updated text under I2C Protocol section 16 Updated Figure 23 17 Updated Figure 24 and added a note under it 18 Updated text under Detailed Description 19 Updated Figure 25 20 Updated Figure 26 23 Updated text under ALS Interrupt Threshold Registers 27 Updated text under Proximity Interrupt Threshold Registers 27 Updated Figure 32 28 Updated FIgure 33 29 Updated Proximity Configuration Register Zero section 30 Updated text under Proximity Configuration Register One 31 Updated Figure 37 32 Updated Figure 38 33 Updated Figure 39 33 Updated text under CRGB Data Registers 34 Updated text under Proximity Data Registers 35 ams Datasheet [v1-12] 2015-May-14 Page 83 Document Feedback TMD4903 − Revision Information Changes from 1-11 (2015-Apr-23) to current revision 1-12 (2015-May-14) Page Updated Figure 47 40 Updated Figure 49 41 Updated Figure 54 44 Updated text under Proximity Offset Registers 48 Added Autozero Configuration Register 49 Updated Figure 63 50 Added Calibration Configuration Register One 52 Updated Figure 67 55 Updated Figure 89 79 Note(s) and/or Footnote(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 2. Correction of typographical errors is not explicitly mentioned. Page 84 Document Feedback ams Datasheet [v1-12] 2015-May-14 TMD4903 − Content Guide Content Guide 1 2 2 3 General Description Key Benefits & Features Applications Block Diagram 4 4 Pin Assignment Pin Description 5 6 Absolute Maximum Ratings Electrical Characteristics 11 11 Timing Characteristics Timing Diagram 12 Typical Operating Characteristics 16 16 16 I²C Protocol I²C Write Transaction I²C Read Transaction 19 19 Detailed Description Sleep After Interrupt Operation 20 23 24 25 26 27 27 Register Description Enable Register (ENABLE 0x80) ALS Integration Time Register (ATIME 0x81) Proximity Sample Time Register (PTIME 0x82) Wait Time Register (WTIME 0x83) ALS Interrupt Threshold Registers (0x84 – 0x87) Proximity Interrupt Threshold Registers (0x88 – 0x8B) Interrupt Persistence Register (PERS 0x8C) Configuration Register Zero (CFG0 0x8D) Proximity Configuration Register Zero (PGCFG0 0x8E) Proximity Configuration Register One (PGCFG1 0x8F) Configuration Register One (CFG1 0x90) Revision ID Register (REVID 0x91) ID Register (ID 0x92) Status Register (STATUS 0x93) CRGB Data Registers (0x94 − 0x9B) Proximity Data Registers (0x9C – 0x9D) Status Register Two (STATUS2 0x9E) Configuration Register Two (CFG2 0x9F) IRBeam Configuration Register (ICONFIG 0xA0) IRBeam Configuration Register Two (ICONFIG2 0xA1) IRBeam Symbol Looping Register (ISNL 0xA2) IRBeam Inter-Symbol OFF Register (ISOFF 0xA3) IRBeam Packet Looping Register (IPNL 0xA4) IRBeam Inter-Packet OFF Register (IPOFF 0xA5) IRBeam Bit Time Register (IBT 0xA6) 28 29 30 31 32 32 33 33 34 35 36 37 38 39 40 40 41 41 42 ams Datasheet [v1-12] 2015-May-14 Page 85 Document Feedback TMD4903 − Content Guide 42 43 43 44 45 46 47 47 48 48 53 54 IRBeam Symbol Length Register (ISLEN 0xA7) IRBeam Status Register (ISTATUS 0xA8) IRBeam Start Register (ISTART 0xA9) Configuration Register Three (CFG3 0xAB) Configuration Register Four (CFG4 0xAC) Configuration Register Five (CFG5 0xAD) Status Register Three (STATUS3 0xB3) Control Register (CONTROL 0xBC) Auxiliary ID Register (AUXID 0xBD) Proximity Offset Registers (0xC0 − 0xC7) Autozero Configuration Register (AZ_CONFIG 0xD6) Calibration Register (CALIB 0xD7) Calibration Configuration Register Zero (CALIBCFG0 0xD8) Calibration Configuration Register One (CALIBCFG1 0xD9) Interrupt Enable Register (INTENAB 0xDD) Interrupt Clear Register (INTCLEAR 0xDE) 55 57 57 57 58 59 61 62 65 70 71 73 Application Information Remote Control General Description of RC Functionality Detailed Description of RC Functionality Block Diagram of Remote Control Functionality Pattern RAM Timeword RAM Control Registers Digital Logic Electrical and Optical Output Example Waveform and Device Setup Protocol Accommodation Checklist 74 75 76 Package Drawings & Markings PCB Pad Layout Mechanical Data 77 77 78 78 78 78 78 Soldering & Storage Information Soldering Information Storage Information Moisture Sensitivity Shelf Life Floor Life Rebaking Instructions 79 80 81 82 83 Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information 49 49 50 52 Page 86 Document Feedback ams Datasheet [v1-12] 2015-May-14