ONSEMI NCV7380D

NCV7380
Advance Information
LIN Transceiver
The NCV7380 is a physical layer device for a single wire data link
capable of operating in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor which uses
the network. The NCV7380 is designed to work in systems
developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in
ISO9141 systems.
Because of the very low current consumption of the NCV7380 in
recessive state, it’s suitable for ECU applications with low standby
current requirements, whereby no sleep/wake−up control from the
microprocessor is necessary.
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MARKING
DIAGRAM
8
1
Features
1
• Operating Voltage VS = 6.0 to 18 V
• Low Current Consumption of Typ. 24 A
• LIN−Bus Transceiver:
A
L
Y
W
♦
♦
•
•
•
•
•
•
•
•
Slew Rate Control for Good EMC Behavior
Fully Integrated Receiver Filter
♦ BUS Input Voltage −27 V to 40 V
♦ Integrated Termination Resistor for LIN Slave Nodes (30 k)
♦ Baud Rate up to 20 kBaud
♦ Will Work in Systems Designed for either LIN 1.3 or LIN 2.0
Compatible to ISO9141 Functions
High EMI Immunity
Bus Terminals Protect Against Short−Circuits and Transients in the
Automotive Environment
Bus Pin High Impedance During Loss of Ground and Undervoltage
Conditions
Thermal Overload Protection
High Signal Symmetry for use in RC–Based Slave Nodes up to 2%
Clock Tolerance when Compared to the Master Node
4.0 kV ESD Protection on all Pins
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
V7380
ALYW
SO−8
D SUFFIX
CASE 751
8
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
RxD 1
8
NC
NC 2
7
VS
VCC 3
6
BUS
TxD
5
GND
4
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV7380D
SO−8
95 Units/Rail
NCV7380DR2
SO−8
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
 Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. P3
1
Publication Order Number:
NCV7380/D
NCV7380
NCV7380
VS
Internal Supply
and
References
VCC
Biasing &
Bandgap
Thermal
Shutdown
POR
30 K
15 K
SLEW RATE
CONTROL
BUS Driver
TxD
BUS
GND
RxD
Receive
Comparator
Input
Filter
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin
Symbol
Description
1
RXD
2
NC
3
VCC
5.0 V supply input.
4
TXD
Transmit data from microprocessor to BUS, LOW in dominant state.
5
GND
Ground
6
BUS
LIN bus pin, LOW in dominant state.
Receive data from BUS to microprocessor, LOW in dominant state.
No connection.
7
VS
Battery input voltage.
8
NC
No connection.
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NCV7380
Electrical Specification
All voltages are referenced to ground (GND). Positive
currents flow into the IC.
The maximum ratings given in the table below are
limiting values that do not lead to a permanent damage of
the device but exceeding any of these limits may do so.
Long term exposure to limiting values may effect the
reliability of the device.
OPERATING CONDITIONS
Symbol
Min
Max
Unit
Battery Supply Voltage (Note 1)
Characteristic
VS
6.0
18
V
Supply Voltage
VCC
4.5
5.5
V
TA
−40
+125
°C
Operating Ambient Temperature
MAXIMUM RATINGS
Rating
Battery Supply Voltage
Symbol
VS
Condition
Min
t < 1 min
Load Dump, t < 500 ms
−0.3
03
Max
Unit
30
V
40
Supply Voltage
VCC
−
−0.3
+7.0
V
Transient Supply Voltage
VS.tr1
ISO 7637/1 Pulse 1 (Note 2)
−150
−
V
Transient Supply Voltage
VS..tr2
ISO 7637/1 Pulses 2 (Note 2)
−
100
V
Transient Supply Voltage
VS..tr3
ISO 7637/1 Pulses 3A, 3B
−150
150
V
BUS Voltage
VBUS
t < 500 ms , Vs = 18 V
−27
t < 500 ms ,Vs = 0 V
−40
V
40
Transient Bus Voltage
VBUS..tr1
ISO 7637/1 Pulse 1 (Note 3)
−150
−
V
Transient Bus Voltage
VBUS.tr2
ISO 7637/1 Pulses 2 (Note 3)
−
100
V
Transient Bus Voltage
VBUS.tr3
ISO 7637/1 Pulses 3A, 3B (Note 3)
−150
150
V
−
−0.3
7.0
V
Human body model, equivalent to
discharge 100 pF with 1.5 k
−4.0
4.0
kV
−
−500
500
mA
DC Voltage on Pins TxD, RxD
ESD Capability of Any Pin
Maximum Latch−Up Free Current at Any Pin
VDC
VESDHB
ILATCH
Maximum Power Dissipation
Ptot
At TA = 125°C
−
197
mW
Thermal Impedance
JA
In Free Air
−
152
°C/W
Storage Temperature
Tstg
−
−55
+150
°C
Junction Temperature
TJ
−
−40
+150
°C
Lead Temperature Soldering
Reflow: (SMD styles only)
Tsld
60 second maximum above 183°C
−5°C/+0°C allowable conditions
−
240 peak
°C
1. VS is the IC supply voltage including voltage drop of reverse battery protection diode, VDROP = 0.4 to 1.0 V, VBAT_ECU voltage range is 7.0 to
18 V.
2. ISO 7637 test pulses are applied to VS via a reverse polarity diode and > 2.0 F blocking capacitor.
3. ISO 7637 test pulses are applied to BUS via a coupling capacitance of 1.0 nF.
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NCV7380
ELECTRICAL CHARACTERISTICS (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
2.75
−
4.3
V
GENERAL
VCC Undervoltage Lockout
VCC_UV
Supply Current, Dominant
ISd
VS = 18 V, VCC = 5.5 V, TxD = L
−
1.0
3.0
mA
Supply Current, Dominant
ICCd
VS = 18 V, VCC = 5.5 V, TxD = L
−
0.8
1.5
mA
Supply Current, Recessive
ISr
VS = 18 V, VCC = 5.5 V, TxD = Open
−
10
20
A
Supply Current, Recessive
ICCr
VS = 18 V, VCC = 5.5 V, TxD = Open
−
14
30
A
Supply Current, Recessive
ISr + ICCr
VS = 12 V, VCC = 5.0 V, TxD = Open,
TA = 25°
−
24
−
A
VS > 6.0 V, TxD = L, EN = H
Thermal Shutdown
Tsd (Note 4)
−
155
−
180
°C
Thermal Recovery
Thys (Note 4)
−
126
140
150
°C
−
120
200
mA
−600
−
−200
A
BUS − Transmit
Short Circuit Bus Current
IBUS_LIM
(Notes 5 and 6)
VBUS = VS, Driver On
Pull Up Current Bus
IBUS_PU
(Notes 5 and 6)
VBUS = 0, VS = 12 V, Driver Off
Bus Reverse Current,
Recessive
IBUS_PAS_rec
(Notes 5 and 6)
VBUS > VS, 6.0 V < VBUS < 18 V,
Driver Off
−
−
5.0
A
Bus Reverse Current Loss of
Battery
IBUS_LOG
(Notes 5 and 6)
VS = 0 V, 0 V < VBUS < 18 V
−
−
5.0
A
Bus Current During Loss of
Ground
IBUS_LOG
(Notes 5 and 6)
VS = 12 V, 0 < VBUS < 18 V
−1.0
−
1.0
mA
Transmitter Dominant Voltage
VBUSdom_DRV_1
Load = 40 mA
−
−
1.2
V
Transmitter Dominant Voltage
VBUSdom_DRV_2
(Note 5)
VS = 6.0 V, Load = 500 −
−
1.2
V
Transmitter Dominant Voltage
VBUSdom_DRV_3
(Note 5)
VS = 18 V, Load = 500 −
−
2.0
V
Pulse Response via 10 k
VPULSE = 12 V, VS = Open
−
25
35
pF
Bus Input Capacitance
CBUS (Note 4)
BUS − Receive
Receiver Dominant Voltage
VilBUS
(Notes 5 and 6)
−
0.4 *VS
−
−
V
Receiver Recessive Voltage
VihBUS
(Notes 5 and 6)
−
−
−
0.6 *VS
V
Center Point of Receiver
Threshold
VBUS_CNT
(Notes 5 and 6)
VBUS_CNT = (VilBUS and VihBUS)/2
0.487
*VS
0.5 *VS
0.512
*VS
V
Receiver Hysteresis
ViBUS_HYS
(Notes 5 and 6)
VBUS_CNTt = (VihBUS − VilBUS)
−
0.16 *VS
−
V
4. No production test, guaranteed by design and qualification.
5. In accordance to LIN physical layer specification 1.3.
6. In accordance to LIN physical layer specification 2.0.
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NCV7380
ELECTRICAL CHARACTERISTICS (continued) (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
TXD
High Level Input Voltage
Vih
Rising Edge
−
−
0.7*VCC
V
Low Level Input Voltage
Vil
Falling Edge
0.3*VCC
−
−
V
VTxD = 0 V
10
15
20
k
IRxD = 2.0 mA
−
−
0.9
V
−1.0
−
1.0
A
−
−
5.0
s
−2.0
−
2.0
s
−
−
6.0
s
TxD Pull Up Resistor
RIH_TXD
RXD
Low Level Output Voltage
Leakage Current
Vol_rxd
Vleak_rxd
VRxD = 5.5 V, Recessive
Propagation Delay Transmitter
(Notes 9 and 11)
ttrans_pdf
ttrans_pdr
Bus Loads: 1.0 K/1.0 nF,
660 /6.8 nF, 500 /10 nF
Propagation Delay Transmitter Symmetry
(Notes 7 and 11)
ttrans_sym
Calculate ttrans_pdf − ttrans_pdr
AC CHARACTERISTICS
Propagation Delay Receiver
(Notes 7, 8, 9, 11 and 14)
trec_pdf
trec_pdr
CRxD = 20 pF
Propagation Delay Receiver Symmetry
(Notes 7 and 8)
trec_sym
Calculate ttrans_pdf − ttrans_pdr
−1.5
−
1.5
s
Slew Rate Rising and Falling Edge,
High Battery (Notes 7 and 12)
tSR_HB
Bus Loads: VS = 18 V,
1.0 K/1.0 nF, 660 /6.8 nF,
500 /10 nF
1.0
2.0
3.0
V/s
Slew Rate Rising and Falling Edge,
Low Battery (Notes 7 and 12)
tSR_LB
Bus Loads: VS = 7.0 V,
1.0 K/1.0 nF, 660 /6.8 nF,
500 /10 nF
0.5
2.0
3.0
V/s
tssym_HB
Bus Loads: VS = 18 V,
1.0 K/1.0 nF, 660 /6.8 nF,
500 /10 nF, Calculate
tsdom−tsrec
−5.0
−
5.0
s
D1
D2
Calculate tBUS_rec(min)/100 s
Calculate tBUS_rec(max)/100 s
0.396
−
−
−
−
0.581
s/s
s/s
trec_deb
BUS Rising and Falling Edge
1.5
−
4.0
s
Slope Symmetry, High Battery
(Notes 7 and 12)
Bus Duty Cycle (Notes 8 and 15)
Receiver Debounce Time
(Notes 10, 13 and 14)
7. In accordance to LIN physical layer specification 1.3.
8. In accordance to LIN physical layer specification 2.0.
9. Propagation delays are not relevant for LIN protocol transmission, only symmetry.
10. No production test, guaranteed by design and qualification.
11. See Figure 2 − Input/Output Timing.
12. See Figure 7 − Slope Time Calculation.
13. See Figure 3 − Receiver Debouncing.
14. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/s.
15. See Figure 8 − Duty Cycle Measurement and Calculation.
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NCV7380
TIMING DIAGRAMS
TxD
50%
ttrans_pdf
ttrans_pdr
VBUS
100%
95%
BUS
50%
50%
5%
0%
trec_pdf
RxD
trec_pdr
50%
Figure 2. Input/Output Timing
t < trec_deb
t < trec_deb
VBUS
60%
40%
t
VRxD
50%
t
Figure 3. Receiver Debouncing Filter
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NCV7380
TEST CIRCUITS FOR DYNAMIC AND STATIC CHARACTERISTICS
NCV7380
VSUP
RL
VCC
100 nF
100 nF
BUS
CL
TxD
2.7 K
RxD
GND
20 pF
Figure 4. Test Circuit for Dynamic Characteristics
NCV7380
100 nF
2 F
500
VSUP
VCC
BUS
TxD
GND
RxD
+
1 nF
Oscilloscope
Schaffner−
Generator
Puls3a,3b
12 V
Puls1,2,4
Figure 5. Test Circuit for Automotive Transients
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+
−
NCV7380
BUS Input/Output
Functional Description
All operation modes will be handled from the NCV7380
automatically.
The recessive BUS level is generated from the integrated
30 k pull up resistor in series with a diode. The diode
prevents reverse current on VBUS when VBUS > VS.
No additional termination resistor is necessary to use the
NCV7380 on LIN slave nodes. If this IC is used for LIN
master nodes, it is necessary to terminate the bus with an
external 1.0 k resistor in series with a diode to VBAT
(Figure 9).
Normal Mode
TxD Input
After power on, the IC switches automatically to normal
mode. Bus communication is possible. If there is no
communication on the bus line the power consumption of
the IC is very low and does not require microprocessor
control.
During transmission the signal on TxD will be
transferred to the BUS driver for generating a BUS signal.
To minimize the electromagnetic emission of the bus line,
the BUS driver has integrated slew rate control and wave
shaping.
Transmitting will be interrupted if thermal shutdown is
active.
The CMOS compatible input TxD directly controls the
BUS level:
TxD = low → BUS = low (dominant level)
TxD = high → BUS = high (recessive level)
The TxD pin has an internal pull up resistor connected to
VCC. This secures that an open TxD pin generates a
recessive BUS level.
Initialization
After power on, the chip automatically enters the
recessive state (TxD = Open). Both VCC and VS must be
present.
Operating Modes
Thermal Shutdown Mode
If the junction temperature TJ is higher than 155°C, the
NCV7380 could be switched into the thermal shutdown
mode (bus driver will be switched off, receiver is on).
If TJ falls below the thermal shutdown temperature (typ.
140°C) the NCV7380 will be switched to the normal mode.
LIN BUS Transceiver
The transceiver consists of a bus−driver (1.2 V @
40 mA) with slew rate control and current limit, and a
receiver with a high voltage comparator with filter
circuitry.
RxD Output
The signal on the BUS pin will be transferred
continuously to the RxD pin. Short spikes on the bus signal
are filtered with internal circuitry (Figure 3 and Figure 6).
VS
VBUS_CNT_max
60%
BUS
50%
VhHYS
40%
VBUS_CNT_min
t < trec_deb
t < trec_deb
RxD
Figure 6. Receive Impulse Diagram
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NCV7380
Operating Under Disturbance
The receive threshold values VBUS_CNT_max and
VBUS_CNT_min are symmetrical to 0.5*VS with a hysteresis
of 0.16*VS (typ). The LIN specific receive threshold is
between 0.4*VS and 0.6*VS.
The received BUS signal will be output to the RxD pin:
Loss of Battery
If VS and VCC are disconnected from the battery, the bus
pin is in high impedance state. There is no impact to the bus
traffic.
BUS < VBUS_CNT – 0.5 * VHYS
→ RxD = low (BUS dominant)
Loss of Ground
In case of an interrupted ground connection from VS and
VCC, there is no influence to the bus line.
BUS > VBUS_CNT + 0.5 * VHYS
→ RxD = high, floating (BUS recessive)
Short Circuit BUS to Battery
RxD is a buffered open drain output with a typical load
of:
Resistance: 2.7 k
Capacitance: < 20 pF
The transmitter output current is limited to 200 mA
(max) in case of short circuit to battery.
Short Circuit BUS to Ground
Negative voltages on the bus pin are limited to current
through the internal 30 k resistor and series diode from VS.
Data Rate
The NCV7380 is a constant slew rate transceiver. The
bus driver operates with a fixed slew rate range of 1.0 V/s
V/T 3.0 V/s. This principle provides very good
symmetry of the slope times between recessive to dominant
and dominant to recessive slopes within the LIN bus load
range (CBUS, Rterm).
The NCV7380 guarantees data rates up to 20 kbit within
the complete bus load range under worst case conditions.
The constant slew rate principle holds appropriate voltage
levels and can operate within the LIN Protocol
Specification for RC oscillator systems with a matching
tolerance up to 2%.
Thermal Overload
The NCV7380 is protected against thermal overloads. If
the chip temperature exceeds the thermal shutdown
threshold, the transmitter is switched off until thermal
recovery. The receiver continues to work during thermal
shutdown.
Undervoltage VCC
The VCC undervoltage lockout feature disables the
transmitter until it is above the undervoltage lockout
threshold to prevent undesirable bus traffic.
Application Hints
LIN System Parameter
Bus Loading Requirements
Parameter
Operating Voltage Range
Symbol
Min
Typ
Max
Unit
VBAT
8.0
−
18
V
Voltage Drop of Reverse Protection Diode
VDrop_rev
0.4
−
1.0
V
Voltage Drop of Bus Decouple Diode in the Master Node
VDrop_dec
0.4
−
1.0
V
Battery Offset Voltage
Vbatoff
−
−
0.1
VBAT
Ground Offset Voltage
Vgoff
−
−
0.1
VBAT
Master Termination Resistor
Rpu_master
900
1000
1100
Slave Termination Resistor
Rpu_slave
20
30
60
k
Number of System Nodes
N
2
−
16
−
BUS_length
−
−
40
m
CLINE
−
100
150
pF/m
Capacitance of Master Node
CMaster
−
220
−
pF
Capacitance of Slave Node
CSlave
195
220
300
pF
Network Total Capacitance
Ct1
1.0
4.0
10
nF
Network Total Resistance
Rt1
537
−
863
Time Constant of Overall System
τnet
1.0
−
5.0
s
Network Distance between any two ECU Nodes
Line Capacitance
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NCV7380
than 700 . Even if the total network capacitance is below
or equal to the maximum specified value of 10 nF, the
network time constant is higher than 7.0 s.
This problem can be solved only by adjusting the master
termination resistor to the required maximum network time
constant of 5.0 s (max).
The LIN bus output driver of the NCV7380 provides a
higher drive capability than necessary (40 mA @ 1.2 V)
within the LIN standard (33.6 mA @ 1.2 V). With this
driver stage the system designer can increase the maximum
LIN networks with a total network capacitance of more
than 10 nF. The total network resistance can be decreased
to:
Recommendations for System Design
The goal of the LIN physical layer standard is to have a
universal definition of the LIN system for plug and play
solutions in LIN networks up to 20 kbd bus speeds.
In case of small and medium LIN networks, it’s
recommended to adjust the total network capacitance to at
least 4.0 nF for good EMC and EMI behavior. This can be
done by setting only the master node capacitance. The
slave node capacitance should have a unit load of typically
220 pF for good EMC/EMI behavior.
In large networks with long bus lines and the maximum
number of nodes, some system parameters can exceed the
defined limits and the LIN system designer must intervene.
The whole capacitance of a slave node is not only the unit
load capacitor itself. Additionally, there is the capacitance
of wires and connectors, and the internal capacitance of the
LIN transmitter. This internal capacitance is strongly
dependent on the technology of the IC manufacturer and
should be in the range of 30 pF to 150 pF. If the bus lines
have a total length of nearly 40m, the total bus capacitance
can exceed the LIN system limit of 10 nF.
A second parameter of concern is the integrated slave
termination resistor tolerance. If most of the slave nodes
have a slave termination resistance at the allowed
maximum of 60 k, the total network resistance is more
Rtl_min (VBat_max VBUSdom)IBUS_max
(18 V 1.2 V)40 mA 420 NOTE: The NCV7380 meets the requirements for
implementation in RC−based slave nodes. The LIN
Protocol Specification requires the deviation of the slave
node clock to the master node clock after synchronization
must not differ by more than 2%.
Setting the network time constant is necessary in large
networks (primarily resistance) and also in small networks
(primarily capacitance).
MIN/MAX SLOPE TIME CALCULATION
(In accordance to the LIN System Parameter Table)
VBUS
100%
60%
60%
40%
40%
0%
Vdom
tsdom
tsrec
Figure 7. Slope Time and Slew Rate Calculation
(In accordance to LIN physical layer specification 1.3)
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
tslope VswingdVdt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because it’s
a passive edge. In case of low battery voltages and high bus
loads the rising edge is only determined by the network. If the
rising edge slew rate exceeds the value of the dominant one,
the slew rate control determines the rising edge.
dVdt 0.2 * Vswing(t40%−t60%)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
tslope 5 * (t40%−t60%)
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NCV7380
tBit
tBit
TxD
tdom(max)
VSUP
trec(min)
100%
74.4%
tdom(min)
58.1%
58.1%
42.2%
BUS
28.4%
trec(max)
GND
28.4%
0%
RxD
Figure 8. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0
Duty Cycle Calculation
voltage levels as specified in the LIN physical layer
specification 1.3.
The devices within the D1/D2 duty cycle range also
operates in applications with reduced bus speed of
10.4 KBit/s or below.
In order to minimize EME, the slew rates of the
transmitter can be reduced (by up to 2 times). Such
devices have to fulfill the duty cycle definition D3/D4 in
the LIN physical layer specification 2.0. Devices within
this duty cycle range cannot operate in higher frequency
20 KBit/s applications.
With the timing parameters shown in Figure 8 two duty
cycles, based on trec(min) and trec(max) can be calculated as
follows:
D1* = trec(min)/(2 x tBit)
D2* = trec(max)/(2 x tBit)
For proper operation at 20 KBit/s (bit time is 50 s) the
LIN driver has to fulfill the duty cycles specified in the AC
characteristics for supply voltages of 7...18 V and the three
defined standard loads.
Due to this simple definition there is no need to measure
slew rates, slope times, transmitter delays and dominant
*D1 and D2 are defined in the LIN protocol specification 2.0.
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NCV7380
Car Battery
Ignition
LIN BUS
2.2 F
1N4001
VBAT
VIN
100 nF
Voltage
Regulator
NCV8502
VOUT
10 k
Slave
ECU
Reset
47 nF
10 F
100 nF
VCC
VS
RxD
P
BUS
NCV7380
220 pF
TxD
GND
GND
2.2 F
1N4001
VBAT
VIN
Voltage
Regulator
NCV8501
VOUT
ECU Connector
to Single Wire
LIN Bus
2.7 K
10 k
100 nF
Master
ECU
10 k
ENABLE
Reset
10 F
47 nF
47 nF
2.7 K
VCC INH
VS
1K
RxD
P
GND
NCV7382*
BUS
TxD
EN
GND
220 pF
*The NCV7382 is a pin compatible transceiver with INH control.
Figure 9. Application Circuitry
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ECU Connector
to Single Wire
LIN Bus
100 nF
NCV7380
ESD/EMC Remarks
ESD Test
General Remarks
The NCV7380 is tested according to MIL883D (human
body model).
Electronic semiconductor products are sensitive to
Electro Static Discharge (ESD). Always observe Electro
Static Discharge control procedures whenever handling
semiconductor products.
EMC
The test on EMC impacts is done according to ISO
7637−1 for power supply pins and ISO 7637−3 for data and
signal pins.
POWER SUPPLY PIN VS
Test Pulse
Condition
Duration
1
t1 = 5.0 s/US = −100 V/tD = 2.0 ms
5000 Pulses
2
t1 = 0.5 s/US = 100 V/tD = 0.05 ms
5000 Pulses
3a/b
US = −150 V/US = 100 V
Burst 100 ns/10 ms/90 ms Break
1h
5
Ri = 0.5 , tD = 400 ms
tr = 0.1 ms/UP + US = 40 V
10 Pulses Every 1 Min
DATA AND SIGNAL PINS BUS
Test Pulse
Condition
Duration
1
t1 = 5.0 s/US = −100 V/tD = 2.0 ms
1000 Pulses
2
t1 = 0.5 s/US = 100 V/tD = 0.05 ms
1000 Pulses
3a/b
US = −150 V/US = 100 V
Burst 100 ns/10 ms/90 ms Break
1000 Burst
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NCV7380
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
Y
M
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 8 0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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NCV7380/D