DATA SHEET MOS FIELD EFFECT TRANSISTOR μ PA2451C N-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING 6 2 5 3 4 2.0±0.1 1 0.25 +0.1 -0.05 0.5±0.1 0.5±0.1 The μ PA2451C is a switching device, which can be driven directly by a 2.5 V power source. The μ PA2451C features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on. 1.85±0.1 PACKAGE DRAWING (Unit: mm) DESCRIPTION FEATURES 0.8 MAX. 4.4±0.1 • 2.5 V drive available • Low on-state resistance RDS(on)1 = 20.0 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A) RDS(on)2 = 21.0 mΩ MAX. (VGS = 4.0 V, ID = 4.0 A) RDS(on)3 = 25.0 mΩ MAX. (VGS = 3.1 V, ID = 4.0 A) RDS(on)4 = 32.0 mΩ MAX. (VGS = 2.5 V, ID = 4.0 A) • Built-in G-S protection diode against ESD 5.0±0.1 0.05 +0 -0.05 (0.15) 0.145±0.05 7 (0.9) (1.45) ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 30.0 V Gate to Source Voltage (VDS = 0 V) VGSS ±12.0 V ID(DC) ±8.2 A ID(pulse) ±60.0 A Drain Current (DC) Note1 Drain Current (pulse) Note2 Total Power Dissipation (2 units) Note1 PT1 2.5 W Total Power Dissipation (2 units) Note3 PT2 0.7 W Channel Temperature Tch 150 °C Storage Temperature Tstg −55 to +150 °C (0.5) (2.2) Each lead has same dimensions. 5,6: Source 2 1,2: Source 1 4: Gate 2 3: Gate 1 7: Drain EQUIVALENT CIRCUIT Drain1 2 Notes 1. Mounted on ceramic board of 50 cm x 1.1 mmt 2. PW ≤ 10 μs, Duty Cycle ≤ 1% 2 3. Mounted on FR-4 board of 50 cm x 1.1 mmt Gate1 LEAD PLATING μ PA2451CTL-E1-A Note μ PA2451CTL-E2-A Note Body Diode Gate Protection Diode Source1 ORDERING INFORMATION PART NUMBER Drain2 PACKING Gate2 Body Diode Gate Protection Diode Source2 PACKAGE Reel Sn-Bi 3000 p/reel 6PIN HWSON (4521) Note Pb-free (This product does not contain Pb in the external electrode and other parts.) Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G18793EJ1V0DS00 (1st edition) Date Published July 2007 NS Printed in Japan 2007 μ PA2451C ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 30.0 V, VGS = 0 V 1.0 μA Gate Leakage Current IGSS VGS = ±12.0 V, VDS = 0 V ±10.0 μA VGS(off) VDS = 10.0 V, ID = 1.0 mA 0.50 1.50 V | yfs | VDS = 10.0 V, ID = 4.0 A 6.0 RDS(on)1 VGS = 4.5 V, ID = 4.0 A 12.0 17.5 20.0 mΩ RDS(on)2 VGS = 4.0 V, ID = 4.0 A 12.5 18.0 21.0 mΩ RDS(on)3 VGS = 3.1 V, ID = 4.0 A 14.0 21.0 25.0 mΩ RDS(on)4 VGS = 2.5 V, ID = 4.0 A 15.5 25.5 32.0 mΩ Input Capacitance Ciss VDS = 10.0 V, 605 pF Output Capacitance Coss VGS = 0 V, 87 pF Reverse Transfer Capacitance Crss f = 1.0 MHz 40 pF Turn-on Delay Time td(on) VDD = 15.0 V, 40 ns Rise Time tr ID = 4.0 A, 75 ns Turn-off Delay Time td(off) VGS = 4.0 V, 140 ns Fall Time tf RG = 6 Ω 85 ns Total Gate Charge QG VDD = 24.0 V, 6.3 nC Gate to Source Charge QGS VGS = 4.0 V, 1.5 nC QGD ID = 8.2 A 2.3 nC VF(S-D) IF = 8.2 A, VGS = 0 V 0.86 V Gate to Source Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note Gate to Drain Charge Body Diode Forward Voltage Note S Note Pulsed: PW ≤ 350 μs, Duty Cycle ≤ 2% TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE D.U.T. D.U.T. VGS RL VGS RG PG. Wave Form VDD 0 VGS 10% PG. 90% τ τ = 1 μs Duty Cycle ≤ 1% 2 90% VDS VDS 10% 0 10% Wave Form td(on) tr ton RL 50 Ω VDD 90% VDS VGS 0 IG = 2 mA td(off) tf toff Data Sheet G18793EJ1V0DS μ PA2451C ELECTRICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 3 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 120 100 80 60 40 20 Mounted on ceramic board of 2 50 cm x 1.1 mmt, 2 units 2.5 Mounted on FR-4 board of 50 cm2 x 1.1 mmt, 2 units 2 1.5 1 0.5 0 0 0 25 50 75 100 125 150 175 0 TA - Ambient Temperature - °C 25 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 1000 it ed Lim ) n) S( o .5 V 4 RD S= (V G ID(pulse) PW =1 i0 1i 0 1i m 10 i 0m i μs s s ID(DC) 1i 0 1 0.1 0.01 ms i DC (2 uni ts ) Single Pulse Mounted on ceramic board of 50 cm2 x 1.1 mmt PD (FET1):PD (FET2) = 1:1 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(ch-A) - Transient Thermal Resistance - °C/W ID - Drain Current - A 100 1000 Mounted on FR-4 board of 2 50 cm x 1.1 mmt 100 Mounted on ceramic board of 50 cm2 x 1.1 mmt 10 1 Single Pulse PD (FET1):PD (FET2) = 1:1 0.1 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G18793EJ1V0DS 3 μ PA2451C DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 10 VDS = 10.0 V Pulsed VGS = 4.5 V 4.0 V 3.1 V 2.5 V 30 ID - Drain Current - A ID - Drain Current - A 40 20 10 1 TA = −25°C 25°C 75°C 125°C 0.1 0.01 Pulsed 0.001 0 0.2 0.6 0.8 1 0 1.2 1 1.5 2 2.5 3 VDS - Drain to Source Voltage - V GATE TO SOURE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S 1.4 1.2 1 0.8 0.6 VDS = 10.0 V ID = 1.0 mA 0.4 0 50 100 150 10 TA = −25°C 25°C 75°C 125°C 1 0.1 VDS = 10.0 V Pulsed 0.01 0.01 0.1 1 10 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 40 VGS = 2.5 V 3.1 V 4.0 V 30 20 4.5 V 10 Pulsed 0 0.1 1 10 100 ID - Drain Current - A 4 0.5 VGS - Gate to Source Voltage - V -50 RDS(on) - Drain to Source On-state Resistance - mΩ 0.4 RDS(on) - Drain to Source On-state Resistance - mΩ VGS(off) - Gate to Source Cut-off Voltage - V 0 40 ID = 4.0 A Pulsed 30 20 10 0 0 2 4 6 8 10 VGS - Gate to Source Voltage - V Data Sheet G18793EJ1V0DS 12 μ PA2451C CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 40 1000 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE VGS = 2.5 V 3.1 V 30 20 4.0 V 4.5 V 10 ID = 4.0 A Pulsed 0 Ciss 100 Coss Crss VGS = 0 V f = 1.0 MHz 10 -50 0 50 100 150 0.1 SWITCHING CHARACTERISTICS VGS - Gate to Drain Voltage - V td(on), tr, td(off), tf - Switching Time - ns 4 td(off) tf td(on) tr 100 DYNAMIC INPUT CHARACTERISTICS VDD = 15.0 V VGS = 4.0 V RG = 6 Ω 100 10 VDS - Drain to Source Voltage - V Tch - Channel Temperature - °C 1000 1 10 VDD = 6.0 V 15.0 V 24.0 V 3 2 1 ID = 8.2 A 0 0.1 1 10 100 ID - Drain Current - A 0 2 4 6 8 QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE IF - Diode Forward Current - A 100 10 1 0.1 VGS = 0 V Pulsed 0.01 0 0.2 0.4 0.6 0.8 1 1.2 VF(S-D) - Source to Drain Voltage - V Data Sheet G18793EJ1V0DS 5 μ PA2451C <Notes for using this device safely> When you use this device, in order to prevent a customer’s hazard and damage, use it with understanding the following contents. If used exceeding recommended conditions, there is a possibility of causing failure of the device and characteristic degradation. 1. When you mount the device on a substrate, carry out within our recommended soldering conditions of infrared reflow. If mounted exceeding the conditions, the characteristic of a device may be degraded and it may result in failure. 2. When you wash the device mounted the substrate, carry out within our recommended conditions. If washed exceeding the conditions, the characteristic of a device may be degraded and it may result in failure. 3. When you use ultrasonic wave to substrate after the device mounting, prevent from touching a resonance generator directly. If it touches, the characteristic of a device may be degraded and it may result in failure. 4. Please refer to Figure 1 as an example of the land pattern. Optimize the land pattern in consideration of density, appearance of solder fillets, common difference, etc in an actual design. Figure 1. Example of the land pattern Unit: mm 3.86 0.30 1.16 0.50 2.04 0.83 6 Data Sheet G18793EJ1V0DS μ PA2451C 5. This device is very thin device and should be handled with caution for mechanical stress. The rate of distortion applied to the device should become below 2000 με. Note1 If the rate of distortion exceeds 2000 με, the characteristic of a device may be degraded and it may result in failure. Figure 2. Direction of substrate and stress The substrate that mounted the device is on a stand with a support width of 24 mm. The device is turned downward. The stress is applied from a top. Substrate: 33 x 6 mm, t = 0.5 mm, FR-4 The direction of a device: Stress Bend Measurement position Support width 24 mm Device Figure 3. Example of the bend and the rate of distortion Note2 The rate of distortion - μ ε 6000 5000 4000 3000 2000 Recommended condition 1000 0 0 0.2 0.4 0.6 0.8 1 Bend - mm Note 1. Definition of rate of distortion(written as ε in this document) ε = (l − l0)/l0 l0: Distance for two arbitrary points before receiving stress. l: Distance above-mentioned when receiving stress. 2. The relation of the distortion and the bend changes with several conditions, such as a size of substrate and so on. Data Sheet G18793EJ1V0DS 7 μ PA2451C • The information in this document is current as of July, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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