NJU3754 PRELIMINARY 11-BIT PARALLEL TO SERIAL CONVERTER PACKAGE OUTLINE GENERAL DESCRIPTION The NJU3754 is an 11-bit parallel to serial converter especially applying to MCU input port expander. It can operate from 2.7V to 5.5V. The NJU3754 requires only 3-port of MCU for data transmission and realizes the effective input port assignment. The status of the input ports is output through a latch circuit, a shift register and a 3-state buffer as the serial data synchronizing with the serial clock. The hysteresis input circuit of the serial clock terminal realizes 5MHz and more operation. Furthermore, pull-up resistors on chip of P0 to P10 terminals reduce external components for key-scan circuit, etc. NJU3754V PIN CONFIGURATION FEATURES 11-Bit Parallel In Serial Out 3-line Serial Interface Output Hysteresis Input 0.5V typ at 5V Maximum Operating Frequency 5MHz and more Operating Voltage 2.7 to 5.5V C-MOS Technology Package Outline SSOP16 P0 P1 P2 P3 P4 P5 P6 VSS 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD CE CLK SO P10 P9 P8 P7 BLOCK DIAGRAM VSS VDD P0 SO Shift Register P2 Latch Circuit P1 P9 P10 Control Circuit Ver.2004-03-15 CE CLK -1- NJU3754 TERMINAL DESCRIPTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL P0 P1 P2 P3 P4 P5 P6 VSS P7 P8 P9 P10 SO CLK CE VDD I/O I I I I I I I I I I I O I I - FUNCTION Parallel Data Input Terminals (with pull-up resistors) Ground Parallel Data Input Terminals (with pull-up resistors) Serial Data Output Terminal Serial Clock Input Terminal Chip Enable Input Terminal Power Supply Terminal (2.7 to 5.5V) FUNCTIONAL DESCRIPTION At the falling edge of CE terminal, the status of P0 to P10 terminal is latched and transferred to the shift register. At the mean time, the P0 data is output from SO terminal. While CE terminal is “L”, the data from P1 to P10 in the shift register are synchronized with the falling edge of CLK terminal and output from SO terminal. When CE terminal is “H”, SO terminal is high impedance. Note 1) If the 11th falling edge and later are input to CLK terminal while CE is “L”, the 12th and the following data are invalid. CE CLK SO P0~P10 -2- P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Invalid Valid Ver.2004-03-15 NJU3754 NJU3555 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage Range VDD -0.3 ~ +7.0 V Input Voltage Range VI VSS-0.3 ~ VDD+0.3 V Power Dissipation PD 300 (SSOP) mW Operating Temperature Range Topr -40 ~ +85 °C Storage Temperature Range Tstg -65 ~+150 °C Note 2) All voltage are relative to VSS=0V reference. Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also Note 4) recommended that the IC is used in the range specified in the DC electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. To stabilize the IC operation, place decoupling capacitor between VDD-VSS. DC ELECTRICAL CHARACTERISTICS PARAMETER Operating Voltage Operating Current Input Voltage SYMBOL (VDD=2.7~5.5V, VSS=0V, Ta=25°C, unless otherwise noted) CONDITION MIN TYP MAX UNIT VDD IDD VIH VDD=5.5V P0~P10=Open CE=H, CLK=L SO=No load P0~P10, CLK, CE Terminals VIL High-level Input Current IIH Low-level Input Current 1 IIL1 Low-level Input Current 2 IIL2 VDD=5V, VI=5V P0~P10, CLK, CE Terminals VDD=5V, VI=0V CLK, CE Terminals VDD=5V, VI=0V P0~P10 Terminals VOH IOH=-0.4mA VOL IOL=+3.2mA ITSL SO Terminal CE=H Output Voltage 3-State Leakage Current Ver.2004-03-15 SO Terminal 2.7 - 5.5 V - - 10 µA 0.7VDD - VDD V VSS - 0.3VDD V - - 1 µA -1 - - µA -100 -40 -15 µA VDD-0.4 - VDD V VSS - 0.4 V -2 - 2 µA -3- NJU3754 SWITCHING CHARACTERISTICS PARAMETER SYMBOL (VDD=2.7~5.5V, VSS=0V, Ta=25°C, unless otherwise noted) CONDITION MIN TYP MAX UNIT CLK Cycle Time tCYC CLK 200 - - ns CLK Pulse Width (H) tWCH CLK 90 - - ns CLK Pulse Width (L) tWCL CLK 90 - - ns CE Pulse Width (H) tWEH CE 100 - - ns CE Set-up Time before CLK Falling tSS CE - CLK 100 - ns CE Hold Time after CLK Falling tHS CLK - CE 100 - ns Parallel Data Set-up Time tSPL P0~P10 - CE 50 - - ns Parallel Data Hold Time tHPL CE - P0~P10 50 - - ns SO Delay Time after CE Falling tDSL CE - SO - - 50 ns SO Delay Time after CLK Falling tDSS CLK - SO - - 50 ns SO Hold Time after CE Rising tDSZ CE - SO - - 20 ns (Note 6) (Note 6) (Note 6) Rise Time tR CLK Terminal - - 20 ns Fall Time tF CLK, CE Terminals - - 20 ns Note 5) A 15kΩ pull-up or pull-down resistor and a 50pF capacitor on the SO terminal. Note 6) All timings are based on 30% and 70% voltage level of VDD. -4- Ver.2004-03-15 NJU3754 NJU3555 TIMING CHARTS CE tSPL P0~P10 tHPL VALID tSS tHS tCYC CLK tDSL tWCH tWCL tF tR SO tDSS tWEH CE tDSZ SO Ver.2004-03-15 -5- NJU3754 APPLICATION CIRCUIT P0 P1 P2 P3 CE MCU CLK P4 P5 P6 P7 NJU3754 P8 P9 SO P10 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -6- Ver.2004-03-15