SM9503A Radio Controlled Clock Receiver IC OVERVIEW Radio controlled clock FEATURES ■ ■ ■ Operating supply voltage range: 1.2 to 3.6V Operating current consumption: 36µA (typ) @1.5V Standby current consumption: 0.1µA (max) @1.5V High sensitivity: 0.3µVrms (typ) input @60kHz input Low frequency standard wave range: 35kHz to 80kHz AGC gain hold function External crystal filter connection Some versions by a compensation capacitor to cancel the crystal parallel capacitor BiCMOS process Package:16-pin VSOP, Chip form (Top view) pre lim ina ■ PINOUT ■ ■ ■ VDD NC PON VSSA OUT XO1 VSS XO2 HLDN XI 16-pin VSOP CF9503A Chip form 9 CP CB PACKAGE DIMENSIONS (Unit: mm) 4.4 ± 0.2 SM9503AV 8 LF + 0. 0.15 − 1 0.05 0.275TYP 5.1 ± 0.2 1.15 ± 0.1 Package IN2 IN1 ORDERING INFORMATION Device 16 6.4 ± 0.2 ■ ■ 1 NC 0.65 0.10 + 0.1 0.22 − 0.05 0 to 10 ° 0.10 ± 0.05 ■ 0.5 ± 0.2 *1: ry The SM9503A is a BiCMOS IC RCC*1 receiver IC. It accepts low frequency standard wave input received from an external antenna, amplifies it, detects the data signal, and outputs a digital time code signal. 0.12 M NIPPON PRECISION CIRCUITS INC.—1 SM9503A PAD LAYOUT (CF9503A) (Unit: µm) IN2 IN1 NC VSSA XO1 XO2 XI (0,0) 11 12 10 VDDA ina ry NC (1430,2360) 13 9 VDD 14 8 PON 15 7 OUT DA9503 NPC 6 VSS 16 5 HLDN 17 4 CP 3 CB 1 2 LF lim Chip size: 1.43 × 2.36mm Chip thickness: 300 ± 30µm PAD size: 100µm × 100µm Chip base: VSS PAD NAME and DIMENSIONS (CF9503A) Pad number Pad dimensions [µm] Pad name X Y XI 170 280.6 2 LF 447.5 220 3 CB 1230 274.2 4 CP 1230 543.2 5 HLDN 1230 823.4 6 VSS 1230 1042 7 OUT 1230 1266.2 8 PON 1230 1535.2 9 VDD 1230 1759.4 10 VDDA 1259.4 2110 11 IN2 908.4 2110 12 NC 170 2055.8 13 IN1 170 1786.8 14 NC 170 1506.6 15 VSSA 170 1276 16 XO1 170 829.8 17 XO2 170 560.8 pre 1 NIPPON PRECISION CIRCUITS INC.—2 SM9503A BLOCK DIAGRAM HLDN CP VSS OUT PON CB LF VDDA ina ry VDD Bias Decoder Peak/Bottom Hold Det. LPF AGC Control CC IN1 AGC Amp Post Amp IN2 XO1 XO2 XI lim VSSA Rectifier PIN DESCRIPTION Pad number Pin number Name I/O1 A/D2 1 7 XI I A Crystal filter input connection 8 LF O A Rectifier LPF capacitor connection 9 CB O A Bottom-hold detector capacitor connection 4 10 CP O A Peak-hold detector capacitor connection 5 11 HLDN Ipu D AGC gain hold control (active LOW) 6 12 VSS − A (−) Negative supply input (substrate potential) 7 13 OUT O D Time code output (active LOW) 8 14 PON Ipu D Standby-mode control input (active LOW) 9 15 VDD − A (+) Positive supply input 10 − VDDA − A (+) Positive supply input (AGC amplifier) 11 16 IN2 I A Antenna input 2 12 1 NC × × No connection (must be open) 13 2 IN1 I A Antenna input 1 14 3 NC × × No connection (must be open) 15 4 VSSA − A (−) Negative supply input (AGC amplifier) 16 5 XO1 O A Crystal filter output 1 17 6 XO2 O A Crystal filter output 2 2 pre 3 Description 1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin 2. A: analog signal, D: digital signal NIPPON PRECISION CIRCUITS INC.—3 SM9503A SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Symbol Supply voltage range VDD Input voltage range VIN Power dissipation PD Storage temperature range Tstg Condition Rating Unit −0.3 to 7.0 V ina ry Parameter −0.3 to VDD + 0.3 V 16-pin VSOP 150 mW 16-pin VSOP −55 to 125 °C Chip form −65 to 150 °C Rating Unit 1.2 to 3.6 V −20 to 70 °C Recommended Operating Conditions VSS = 0V Parameter Symbol VDD Operating temperature range Topr pre lim Supply voltage range Condition NIPPON PRECISION CIRCUITS INC.—4 SM9503A Electrical Characteristics VDD = 1.2 to 3.6V, VSS = 0V, Ta = −20 to 70°C unless otherwise noted. Rating Parameter Symbol Condition Unit min typ max 1.2 – 3.6 V VDD Maximum operating current consumption1 IDDM VDD = 1.5V, Ta = 25°C, no input signal, PON: VSS, OUT: Open – 50 80 µA Normal operating current consumption1 IDDT VDD = 1.5V, Ta = 25°C, 0.1mVrms input amplitude (differential input), 500ms pulsewidth, PON: VSS, OUT: Open – 36 – µA Standby mode current consumption IST PON, HLDN: VDD or Open – – 0.1 µA IN1−IN2 differential input, FIN = 60kHz – 0.3 1.0 µVrms Minimum input voltage range VFMIN Maximum input voltage range VFMAX ina ry Operating supply voltage IN1−IN2 differential input, FIN = 60kHz 80 – – mVrms Input frequency FIN IN1−IN2 differential input 35 – 80 kHz Startup time2 tON When supply is applied – – 8 sec tPON From standby mode – – 8 sec VIL PON, HLDN – – 0.2 V VIH PON, HLDN VDD – 0.2 – – V IIL VIN = 0V, PON, HLDN −1 – – µA IIH VIN = VDD, PON, HLDN – – 1 µA Startup time (PON)2 Input voltage Input current Gain hold time VOL IOL = 5µA, OUT – – 0.2 V VOH IOH = − 5µA, OUT VDD – 0.2 – – V tHLD ≤ ± 3dB variation 1 – – sec lim Output voltage Fall time output propagation delay3 tDN – – 160 ms Rise time output propagation delay3 tUP – – 200 ms T200 100 200 300 ms 400 500 650 ms LOW-level output pulsewidth4 (200ms) LOW-level output pulsewidth4 (500ms) T500 LOW-level output pulsewidth4 (800ms) T800 TBD 800 TBD ms LOW-level output pulsewidth4 (900ms) T900 TBD 900 TBD ms Noise rejection ratio5 S/N – – 9 dB pre FIN = 60kHz, NPC standard crystal, NPC standard jig 1. Measured using the standard circuit. 2. The time taken under stable wave input conditions from when power is applied or standby is released, using PON, until stable digital output occurs within ratings. 3. The time taken, with 10:1 input signal amplitude ratio and 500ms pulsewidth, from when a change in signal input occurs until the output OUT changes. Note that this characteristic is very dependent on the antenna and crystal filter characteristics. The standard crystal used here has the following equivalent circuit coefficients. L1 C1 R1 f [kHz] L1 [kH] C1 [fF] R1 [kΩ] C0 [pF] 60 TBD TBD TBD TBD C0 4. Values obtained when using the NPC standard crystal employed here. Note that these values are dependent on the crystal characteristics, and should be considered as reference values. 5. Time averaged rms values, where the noise is white noise and the measurement bandwidth is determined by the crystal filter equivalent used in the standard circuit. NIPPON PRECISION CIRCUITS INC.—5 SM9503A 50Ω + − ina ry STANDARD CIRCUIT NC IN2 IN1 VDDA NC VDD VSSA PON XO1 OUT XO2 100kΩ 60kHz VSS XI HLDN LF CP CB 0.22µF 1µF 1µF 0.1µF lim TYPICAL APPLICATION CIRCUIT ANT NC IN2 IN1 VDDA NC VDD VSSA PON XO1 OUT pre XO2 100kΩ 60kHz VSS XI HLDN LF CP 0.22µF CONTROLLER CB 1µF 1µF 0.1µF NIPPON PRECISION CIRCUITS INC.—6 SM9503A FUNCTIONAL DESCRIPTION AGC Amplifier and Gain Hold Function Crystal Filter Circuit ina ry The input voltage from the antenna is amplified by the AGC amplifier. The gain can be monitored by the voltage on pin CP, and can be changed by varying the CP voltage. An external capacitor Cp can be connected to CP to stabilize the voltage, but the gain tracking time is dependent on the capacitance. When HLDN is open (or HIGH), the gain automatically adjusts to follow the post-amplifier detector signal. When HLDN is LOW, the immediately preceding gain is held for an interval determined by the Cp capacitance. External crystals are used as filters. The center frequency and bandwidth of the filters is determined by the crystal characteristics. If the center frequency is lower than the target frequency, it is necessary to add CL capacitor for the adjustment frequency. If Q of the crystal filter is higher and the output delay is larger, it is necessary to add RL to adjust it. Adding a compensation capacitor CC, it is possible to select built-in or external, cancels the high-frequency components pass through the crystal parallel capacitance. Compensation capacitors are built in, and wiring them inside makes possible to select versions of the required capacitances from 0.5pF to 2.0pF. µ CC CC AGC Amp Post Amp XO2 XI Post Amp XO1 lim XO1 AGC Amp XO2 XI CC CL RL The case of using the external compensation capacitor CL RL The case of using built-in compensation capacitor Detector Circuit pre The amplified signal is full-wave rectified and passed through a lowpass filter detector. The detector output is input to peak hold (pin CP) and bottom hold (pin CB) circuits to form the decoder reference potentials and peak hold potential for AGC control. VDD potential VDD potential VDD potential Amplifier Rectifier LPF Peak/ Bottom Hold Bottom hold Peak hold NIPPON PRECISION CIRCUITS INC.—7 SM9503A Decoder Circuit The detector output and peak/bottom hold mid-level potential reference are used to decode the time code signal, which is output on pin OUT. The output is active-LOW, so that the output is LOW when the input amplitude is HIGH. Rectifier LPF ina ry VDD potential LPF waveform VDD potential Decoder VDD potential OUT output Bottom hold Peak/ Bottom Hold VSS potential Mid-level potential Peak hold Standby Function When PON is open (or HIGH), the device is in standby mode and the current consumption is reduced. Receiver operation starts when PON goes LOW. Mode Open (or HIGH) Standby HIGH Operating Time code pre LOW OUT lim PON NIPPON PRECISION CIRCUITS INC.—8 pre lim ina ry SM9503A Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: [email protected] NP0410BE 2004.11 NIPPON PRECISION CIRCUITS INC.—9