SM5170AV PLL Synthesizer IC NIPPON PRECISION CIRCUITS INC. OVERVIEW The SM5170AV is a PLL synthesizer IC developed for application in pagers. It incorporates independently-controlled reference frequency and FIN input frequency dividers, and operates from a low-voltage supply to realize low power dissipation. It features a charge pump that operates at 3 V, making possible a wide range of VCO designs. FEATURES ■ ■ Supply voltages • VDD1 = 0.95 to 1.2 V (prescaler, counters) • VDD2 = 2.0 to 3.3 V (charge pump) FIN input frequency • fFIN = 300 MHz (VDD1 = 0.95 V) • fFIN = 330 MHz (VDD1 = 1.0 V) ■ ■ ■ ■ ■ Reference frequency • fXIN = 25 MHz (VDD1 = 0.95 V) 20 to 262140 reference frequency divider ratio range (with 1/4 prescaler built-in) 1056 to 131071 FIN input frequency divider ratio range −10 to 60 °C operating temperature range 16-pin VSOP PINOUT (Top view) XIN 1 VDD2 DB DO VSS FIN VDD1 16 8 TEST NC 5170AV XOUT OPR LE DATA CLK LD 9 NC ORDERING INFORMATION D e vice P ackag e S M 5 1 7 0 AV 16-pin V S O P NIPPON PRECISION CIRCUITS—1 SM5170AV PACKAGE DIMENSIONS Unit: mm 4.4 0.2 6.4 0.2 16-pin VSOP + 0..1005 1.15 0.1 0.275typ 5.1 0.2 0.65 0.10 0.05 0 0.15 - 0 10 0.10 + 0.10 0.22− 0.05 0.5 0.2 0.12 M BLOCK DIAGRAM VDD1 AREA(1V) XIN 1/4 Prescaler 16Bit R−Counter Boost Signal Generator DB XOUT VDD2 AREA(3V) 16Bit R−Latch Latch Selector 22Bit Shift Register CLK DATA LE Level Shifter Phase Detector Charge Pump DO Lock Detector LD 17Bit N−Latch OPR VDD1 AREA(1V) FIN Dual Modulus Prescaler 5Bit Swallow Counter 12Bit Main Counter NIPPON PRECISION CIRCUITS—2 SM5170AV PIN DESCRIPTION Number Name I/O Supply Description 1 XIN I 1V 2 XOUT O 1V Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can be connected to XIN. The clock is output on XOUT. Feedback resistor built-in for AC-coupled inputs. 3 VDD2 – 3V Phase comparator, charge pump and booster signal 3 V supply 4 DB O 3V Booster signal output for faster locking 5 DO O 3V Phase comparator output pin. Built-in charge pump and tristate output means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter. 6 VSS – – 7 FIN I 1V FIN input frequency divider input pin. Feedback resistor built-in for AC-coupled inputs. 8 VDD1 – 1V Reference frequency and FIN input frequency prescaler and counter 1 V supply 9 NC – – 10 LD O 1V Unlock signal output pin. (Unlocked when LOW). The function of LD can be turned OFF using the LD input control bit (LD should be tied LOW when not used). 11 CLK I 3V Control data clock input pin 12 D ATA I 3V Control data input pin 13 LE I 3V Control data latch enable signal input pin 14 OPR I 3V Pow er-save control pin. Start when HIGH, standby mode when LOW . 15 NC – – 16 TEST I 1V Ground pin No connection No connection Test pin. Pull-down resistor built-in. Leave open or connect to ground for normal operation. SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V P arameter Supply voltage Input voltage range Symbol Condition Rating Unit VDD1 VDD1 −0.3 to 2.0 V VDD2 VDD2 −0.3 to 4.6 V V IN1 FIN, XIN, T E S T V S S − 0.3 to V D D 1 + 0.3 V V IN2 OPR, CLK, DATA, LE V S S − 0.3 to V D D 2 + 0.3 V Storage temperature range T stg −40 to 125 °C Pow er dissipation PD 150 mW Rating Unit Recommended Operating Conditions VSS = 0 V P arameter Supply voltage Operating temperature range Symbol Condition VDD1 VDD1 0.95 to 1.2 V VDD2 VDD2 2.0 to 3.3 V −10 to 60 °C T opr NIPPON PRECISION CIRCUITS—3 SM5170AV Electrical Characteristics VSS = 0 V, VDD1 = 0.95 to 1.2 V, VDD2 = 2.0 to 3.3 V, Ta = −10 to 60 °C P arameter Symbol Rating Condition min typ max VDD1 operating current consumption ID D 1 Note 1. – 1.1 1.9 VDD2 operating current consumption ID D 2 Note 2. – 0.003 – VDD1 standby current Ist1 Note 3. – 0.7 – VDD2 standby current Ist2 Note 4. – 0.01 10.0 V D D 1 = 0.95 to 1.2 V 300 – – V D D 1 = 1.0 to 1.2 V 330 – – Unit mA µA FIN maximum operating input frequency fm a x 1 300 mVp-p sine w ave XIN maximum operating input frequency fm a x 2 300 mVp-p sine wave (external input) 25 – – MHz FIN minimum operating input frequency fmin1 300 mVp-p sine wave – – 40 MHz MHz XIN minimum operating input frequency FIN input amplitude XIN input amplitude MHz fmin2 300 mVp-p sine wave (external input) – – 9 V FIN1 fFIN = 300 MHz, AC coupling 0.3 – – V FIN2 fFIN = 330 MHz, V D D 1 = 1.0 to 1.2 V, A C coupling 0.3 – – V XIN fX I N = 25 MHz, AC coupling (external input) 0.3 – – Vp-p Vp-p OPR, CLK, DATA, LE LOW -level input voltage V IL – – 0.3 V OPR, CLK, DATA, LE HIGH-level input voltage V IH VDD2 − 0.3 – – V FIN LOW -level input current IIL1 XIN LOW -level input current IIL2 V IL = 0 V FIN HIGH-level input current IIH1 XIN HIGH-level input current IIH2 D B L OW -level output voltage VDOL V IH = V D D 1 – – 60 µA – – 10 µA – – 60 µA – – 10 µA 0.5 V Note 5. DB HIGH-level output voltage VDOH Note 6. VDD2 − 0.5 D O L OW -level output current ID O L Note 7. 1.0 DO HIGH-level output current ID O H Note 8. 1.0 D O , DB tristate output high-impedance leakage current IO Z L VOL = 0 V – IO Z H VOH = VDD2 D ATA → CLK setup time tS U 1 CLK → LE setup time tS U 2 Hold time See the timing diagra m s . tH V – – mA – – mA – 100 nA – – 100 nA 2 – – µs 2 – – µs 2 – – µs 1. V D D 1 = 1.0 to 1.05V, V D D 2 = 2.7 to 3.3 V, fFIN = 310 MHz (300 mVp-p sine wave), fX I N = 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator frequency, OPR = HIGH, no output load, typ condition : V D D 1 = 1.0 V 2. V D D 1 = 0.95 to 1.2 V, V D D 2 = 2.7 to 3.3 V, fFIN = 310 MHz (300 mVp-p sine wave), fX I N = 14.4 MHz (300 mVp-p sine wave), 25 kHz comparator frequency, OPR = HIGH, no output load, typ condition : V D D 2 = 3.0 V 3. V D D 1 = 1.0 V, V D D 2 = 3.0 V, OPR = LOW , no input/output load (i.e. CLK = DATA = LE = 0 V) 4. V D D 1 = 0 V, V D D 2 = 2.7 to 3.3 V, OPR = LOW , no input/output load (i.e. CLK = DATA = LE = 0 V), typ condition : V D D 2 = 3.0 V 5. DB output is derived from the V D D 2 supply. DB-pin condition select bit = (00001) 2 , V D D 2 = 2.7 to 3.3 V, no load 6. DB output is derived from the V D D 2 supply. DB-pin condition select bit = (11111) 2 , V D D 2 = 2.7 to 3.3 V, no load 7. DO output is derived from the V D D 2 supply. V D D 2 = 2.7 to 3.3 V, V O L = 0.4 V 8. DO output is derived from the V D D 2 supply. V D D 2 = 2.7 to 3.3 V, V O H = V D D 2 − 0.4 V DATA, CLK, and LE timing DATA CLK LE VIH tSU1 VIH tH VIH tSU2 VIH NIPPON PRECISION CIRCUITS—4 SM5170AV FUNCTIONAL DESCRIPTION Frequency Divider Data The input data should be specified keeping in mind the VDD2 supply. The data is input using CLK, DATA and LE pins into the shift register and latch which operate from the VDD2 supply. The VDD1 supply level, however, is not needed and can be ON or OFF. the shift register on the rising edge of the clock signal. Accordingly, the data should change state on the falling edge of the clock signal. Data is transferred from the shift register to the latch when the latch enable (LE) signal goes HIGH. Accordingly, the latch enable signal should be held LOW while data is being written to the shift register. The control data input uses a 3-line 24-bit serial interface comprising the clock (CLK), data input (DATA) and latch enable (LE). The data is input with the MSB first. The last two bits (23rd + 24th) are used as the latch select control bits. Data is written to CLK 1 2 3 4 5 6 7 8 9 10 11 The clock and data input signals are both ignored when the latch enable signal goes HIGH. Also, the CLK, DATA and LE inputs should be tied LOW when not setting data. 12 13 14 15 16 17 18 19 20 21 22 23 DATA MSB 24 LSB Control bits LE Figure 1. Frequency divider data format Input Data Description Latch select DATA MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LSB 24 Control bits Figure 2. Latch select data format The last two data bits determine the status of the shift register data latch. Bit 23 Bit 24 Latch 0 0 S w allow counter and main counter frequency divider ratio latch select 0 1 Reference frequency counter divider ratio data and LD output latch select FIN input frequency Divider (N-counter) Structure The FIN input frequency divider generates a comparator frequency signal (FV), which is input to the phase comparator, by dividing the VCO signal input on pin FIN. Frequency settings Counter set ranges Prescaler Swallow counter Main counter FIN input frequency divider ratio Prescaler Swallow counter Main counter FIN input frequency divider ratio range The phase comparator is comprised of dual modulus prescalers, a 5-bit swallow counter and a 12-bit main counter. P and P + 1 S M N = (P + 1) × S + P × (M − S) N = P × M + S (where M > S) P = 32, P + 1 = 33 S = 0 to 31 M = 32 to 4095 N = 1056 to 131071 NIPPON PRECISION CIRCUITS—5 SM5170AV Swallow counter and main counter data The swallow counter and main counter which determine the FIN input frequency divider ratio are set by MSB 1 2 3 4 2 11 2 10 29 28 bits 1 to 12 and bits 13 to 17, respectively. The voltage signal output on pin DB is set by bits 18 to 22. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 27 26 25 24 23 22 21 20 24 23 22 21 20 24 23 22 21 20 Main Counter (12bit : 32 to 4095) 23 LSB 24 Swallow Counter (5bit : 0 to 31) DBpin Condition Select bits Control bits Figure 3. Swallow counter and main counter frequency divider data format FIN input frequency divider example If the VCO output is (fVCO), the output frequency (fLO) is 251.3 MHz, and the channel bandwidth (fCH: Phase comparator frequency (fR)) is 25 kHz, then the FIN input frequency divider ratio N is given by: f LO f VCO 251.3 N = ---------- = -------------- = ------------- = 10052 f CH fN 0.025 = 32 × 314 + 4 Therefore, the swallow counter count is 4 (00100)2 and the main frequency divider counter count is 314 (000100111010)2 . DB fast-lockup data The output voltage on pin DB provides an additional boost to charge the external lowpass filter capacitor for faster lockup times. One of 31 possible output voltage level signals is selected by bits 18 to 22. ator signal FR is generated after OPR goes HIGH, or after LE goes LOW when data is written. The DB output subsequently becomes high impedance. Note that if bits 18 to 22 are all set to 0, this function is not activated and DB remains in the high impedance state. The DB level signal output occurs during 2 clock cycles when the reference frequency divider comparInput data format example FIN input frequency divider = 10052, DB is high impedance: MSB 1 2 11 0 2 2 10 0 3 29 0 4 28 1 5 27 0 6 26 0 7 25 1 8 24 1 9 23 1 10 22 0 11 21 1 Main Counter (12bit : 32 to 4095) 12 20 0 13 24 0 14 23 0 15 22 1 16 21 0 17 20 0 18 24 0 19 23 0 20 22 0 21 21 0 22 20 0 23 LSB 24 0 0 Swallow Counter (5bit : 0 to 31) DBpin Condition Select bits Control bits Figure 4. Swallow counter and main counter frequency divider data example NIPPON PRECISION CIRCUITS—6 SM5170AV Reference Frequency Divider (R-counter) Structure The reference frequency divider generates a comparator frequency signal (FR), which is input to the phase comparator, by dividing the reference oscillator frequency input either from an external signal on XIN or from a crystal oscillator connected between XIN and XOUT. The reference frequency divider is comprised of a fixed divide-by-4 prescaler and a 16-bit reference counter. Frequency settings Prescaler Reference counter Reference frequency divider ratio Counter set ranges Prescaler Reference counter Reference frequency divider ratio range A (= 4) B R=A×B=4×B A=4 B = 5 to 65535 R = 20 to 262140 Reference counter frequency data and LD setting The reference counter which determines the reference frequency divider ratio is set by bits 1 to 16. The lock detect signal output is set by bit 20. MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 15 2 14 2 13 2 12 2 11 2 10 29 28 27 26 25 24 23 22 21 20 Reference Counter (16bit : 5 to 65535) 17 18 19 20 21 22 23 LSB 24 Not used (set to 000) LDpin Set bit Test bits (set to 00) Control bits Figure 5. Reference counter data and LD output setting format Reference frequency divider example If the VCO output is (fVCO), the crystal oscillator frequency is 14.4 MHz and the channel bandwidth (fCH: comparator frequency (fR)) is 25 kHz, then the reference frequency divider ratio R is given by: Xtal Xtal 14.4 R = ----------- = ----------- = ------------- = 576 = 4 × 144 f CH fR 0.025 Therefore, the reference counter count is 144 (0000000010010000)2 . LD output The output on LD is set by bit 20. Bit 20 LD output 1 Nor mal unlock signal output (normal operation) 0 Unlock signal output OFF, LOW -level output Bits 15 to 19, bits 21 to 22 Bits 15 to 19 have no meaning, and should be set to 0. Bits 21 and 22 are factory test bits and should also be set to 0. NIPPON PRECISION CIRCUITS—7 SM5170AV Input data format example Reference frequency divider = 144, LD normal operation: MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 LSB 24 2 15 0 2 14 0 2 13 0 2 12 0 2 11 0 2 10 0 29 0 28 0 27 1 26 0 25 0 24 1 23 0 22 0 21 0 20 0 0 0 0 1 0 0 0 1 Reference Counter (16bit : 5 to 65535) Not used (set to 000) LDpin Set bit Test bits (set to 00) Control bits Figure 6. Reference counter data and LD output setting example Standby Mode The SM5170AV enters standby mode when OPR goes LOW. In this mode, the states and functions shown in the table occur. Block State DO and DB Floating (high impedance) LD L O W -level output Phase comparator Reset Input FIN Feedback resistor is cutoff (HIGH level) Input XIN Feedback resistor is cutoff (HIGH level) N counter Reset R counter Reset Latch data Stored (while V D D 2 is within rating) In standby mode, some current flows into VDD1. Therefore, it is necessary to reduce VDD1 to 0 V to fully reduce current consumption and reduce power dissipation. Note that if both the VDD1 and VDD2 supplies are reduced to 0 V, the latch contents will be erased. In this case, VDD1 only should be reduced to 0 V. Standby mode is released when VDD1 rises and OPR goes HIGH. Phase Comparator Timing Diagram FR FV DO LD Figure 7. Phase comparator timing The DO output circuit polarity is configured for connection to an external passive filter. The signals compared are FV and FR, which are the internal FIN input frequency divider output signal and reference frequency divider output signal, respectively. NIPPON PRECISION CIRCUITS—8 SM5170AV INPUT/OUTPUT EQUIVALENT CIRCUITS XIN, XOUT DO Lagging Phase Correction Signal From Internal Circuits XIN XOUT To Internal Counter DO Leading Phase Correction Signal LD From Internal Circuits FIN From Internal Circuits LD DB From Internal Circuits From Internal Circuits DB From Internal Circuits FIN To Internal Counter From Internal Circuits From Internal Circuits From Internal Circuits OPR, CLK, DATA, LE CLK DATA LE OPR TEST To Internal Circuits TEST To Internal Circuits NIPPON PRECISION CIRCUITS—9 SM5170AV NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9808CE 1999.8 NIPPON PRECISION CIRCUITS—10