MICROSEMI ARF476FL

Common Source
Push-Pull Pair
ARF476FL
S
D
G
S
S
G
RF POWER MOSFET
S
S
D
D
S
ARF476FL
D
S
N - CHANNEL PUSH - PULL PAIR
G
G
S
165V 450W 150MHz
The ARF476FL is a matched pair of RF power transistors in a common source configuration. It is designed for high voltage
push-pull or parallel operation in narrow band ISM and MRI power amplifiers up to 150 MHz.
• Specified 150 Volt, 128 MHz Characteristics:
•
Output Power = 900 Watts Peak
•
Gain = 15dB (Class AB)
•
Efficiency = 50% min
• Extended Flange - 3mm Creep Distance.
• High Voltage Breakdown and Large SOA
for Superior Ruggedness.
• Low Thermal Resistance.
MAXIMUM RATINGS
Symbol
All Ratings: TC = 25°C unless otherwise specified.
Parameter
ARF476FL
VDSS
Drain-Source Voltage
500
VDGO
Drain-Gate Voltage
500
ID
VGS
PD
TJ,TSTG
TL
UNIT
Volts
10
Amps
Gate-Source Voltage
±30
Volts
Total Device Dissipation @ TC = 25°C
910
Watts
Continuous Drain Current @ TC = 25°C
(each device)
-55 to 175
Operating and Storage Junction Temperature Range
°C
300
Lead Temperature: 0.063" from Case for 10 Sec.
STATIC ELECTRICAL CHARACTERISTICS (each device)
Characteristic / Test Conditions
MIN
BVDSS
Drain-Source Breakdown Voltage (VGS = 0V, ID = 250 µA)
500
VDS(ON)
On State Drain Voltage
Symbol
IDSS
1
(I D(ON) = 5A, VGS = 10V)
TYP
MAX
2.9
4
Zero Gate Voltage Drain Current (VDS = VDSS, VGS = 0V)
100
Zero Gate Voltage Drain Current (VDS = 50V, VGS = 0, TC = 125°C)
500
IGSS
Gate-Source Leakage Current (VGS = ±30V, VDS = 0V)
g fs
Forward Transconductance (VDS = 15V, ID = 5A)
3
g fs1 g fs2 Forward Transconductance Match Ratio (V = 15V, I = 5A)
/
DS
D
0.9
VGS(TH)
Gate Threshold Voltage (VDS = VGS, ID = 200mA)
∆VGS(TH)
Gate Threshold Voltage Match (VDS = VGS, ID = 200mA)
±100
2
3.6
UNIT
Volts
µA
nA
mhos
1.1
3.3
4
0.2
Volts
THERMAL CHARACTERISTICS
Characteristic
MIN
TYP
MAX
RθJC
Junction to Case
0.15
0.165
RθJHS
Junction to Sink (Use High Efficiency Thermal Grease and Planar Heat Sink Surface.)
0.30
0.33
CAUTION: These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed.
Microsemi Website - http://www.microsemi.com
UNIT
°C/W
050-4931 B 6-2007
Symbol
DYNAMIC CHARACTERISTICS (per section)
Symbol
ARF476FL
Test Conditions
Characteristic
MIN
TYP
MAX
780
830
VDS = 50V
125
130
f = 1MHz
7
9
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
td(on)
Turn-on Delay Time
VGS = 15V
5.1
10
Rise Time
VDD = 250V
4.1
8
ID = ID[Cont.] @ 25°C
12
18
RG = 1.6 Ω
4.0
7
MIN
TYP
MAX
14
16
dB
50
55
%
tr
td(off)
tf
VGS = 0V
Turn-off Delay Time
Fall Time
FUNCTIONAL CHARACTERISTICS
Symbol
GPS
Characteristic
Test Conditions
Common Source Amplifier Power Gain
η
Drain Efficiency
ψ
Electrical Ruggedness VSWR 5:1
f = 128 MHz
Idq = 15mA
VDD = 150V
Pout = 900W
PW = 3ms
10% duty cycle
Per transistor section unless otherwise specified.
3000
12V
25
10V
20
9V
15
8V
10
500
Coss
100
50
Crss
10
7V
5
0
0
5
10
15
20
25
30
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 1, Typical Output Characteristics
1
.1
1
10
100 200
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 2, Typical Capacitance vs. Drain-to-Source Voltage
30
1.10
VDS> ID (ON) x RDS (ON)MAX.
250 µSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
TJ = -55°C
20
TJ = +25°C
15
10
TJ = -55°C
VGS(th), THRESHOLD VOLTAGE
(NORMALIZED)
ID, DRAIN CURRENT (AMPERES)
Ciss
1000
11V
CAPACITANCE (pf)
ID, DRAIN CURRENT (AMPERES)
30
5
1.05
1.00
0.95
TJ = +125°C
0
ns
0
2
4
6
8
10
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 3, Typical Transfer Characteristics
0.90
-50
-25
UNIT
No Degradation in Output Power
Microsemi Reserves the right to change, without notice, the specifications and information contained herein.
25
pF
(Push-Pull Configuration)
1 Pulse Test: Pulse width < 380 µS, Duty Cycle < 2%.
050-4931 B 6-2007
UNIT
0
25
50
75 100 125 150
TC, CASE TEMPERATURE (°C)
Figure 4, Typical Threshold Voltage vs Temperature
ARF476FL
0.18
0.16
D = 0.9
0.14
0.7
0.12
0.10
0.5
0.08
PDM
Note:
0.3
0.04
t2
SINGLE PULSE
Duty Factor D = t1/t2
Peak TJ = PDM x ZθJC + TC
0.1
0.02
0.05
10-5
10-4
10-3
10-2
10-1
1.0
RECTANGULAR PULSE DURATION (SECONDS)
FIGURE 5a, MAXIMUM EFFECTIVE TRANSIENT THERMAL IMPEDANCE, JUNCTION-TO-CASE vs PULSE DURATION
TJ (°C)
TC (°C)
0.0755
0.0893
Dissipated Power
(Watts)
0.0135F
ZEXT
0
t1
ZEXT are the external thermal
impedances: Case to sink, sink to
ambient, etc. Set to zero when modeling
only the case to junction.
0.161F
Figure 5b, TRANSIENT THERMAL IMPEDANCE MODEL
Table 1 - Typical Series Equivalent Large Signal Input - Output Impedance
Freq. (MHz)
30
60
90
120
150
Zin (Ω) gate to gate
5.2 -j10
1.37 -j5.2
.53 -j2.6
.25 -j1.0
.25 +j0.2
ZOL (Ω) drain - drain
41 -j20
26 -j25
16 -j23
10 -j20
6.7 -j17
Zin - Gate -gate shunted with 25Ω IDQ = 15mA each side
ZOL - Conjugate of optimum load for 600 Watts peak output at Vdd = 150V
25% duty cycle and PW = 5ms
050-4931 B 6-2007
0.06
ARF476FL
128MHz Test amplifier
Po = 900W @150V
3ms pulse 10% Duty Cycle
Vg1
C6
C5
C3
L1
C2
C1
TL5
TL1
C7
C8
+
Vdd
-
L3
C11
C10
TL3
T2
T1
J1
L2
R3
R1
+
T3
J2
TL2
C4
R4
R2
C9
C1 25pF poly trimmer
C2 750pF ATC 700B
C3-4 2200pF NPO 500V chip
C5-10 10nF 500V chip
C11 1000uF 250V electroytic
L1 30nH 1.5t #18 enam .375" dia
L2 680nH 12t #24 enam .312" dia
L3 2t #20 on Fair-Rite 2643006302 bead, ~ 2uH
Vg2
DUT
TL4
TL6
R1-2 3.1Ω : 3 parallel 22Ω 1W 2512 SMT
R3-4 2.2kΩ 1/4W axial
T1 1:1 balun 50Ω coax on Fair-Rite 2843000102 core
T2 4:1 25Ω coax on 2843000102 Fair-Rite balun core
T3 1:1 coax balun RG-303 on 2861006802 Fair-Rite core
TL1-2 Printed line L= 0.75" w =.23"
TL3-6 Printed line L= 0.65" w =.23"
0.23" wide stripline on FR-4 board is ~ 30&!Zo
Peak Output Power vs. Vdd and Duty Cycle
1.2
900
800
1
Max
Duty Cycle
700
0.8
600
500
0.6
Po Watts
400
300
0.4
200
0.2
100
0
Notes:
The value of L1 must be adjusted as the supply voltage is
changed to maintain resonance in the output circuit. At
128MHz its value changes from approximately 40nH at
100V to 30nH at 150V.
With the 50Ω drain-to-drain load, the duty cycle above
100V must be reduced to insure power dissipation is
within the limits of the device. Maximum pulse length
should be 100mS or less. See transient thermal
impedance, figure 5.
0
80
100
120
140
160
Thermal Considerations and Package Mounting:
.100
.100
.100
Drain Supply Voltage Vdd
.325 +/- .010
1.000
.125R
4 pls
.080
.125dia
4 pls
.570
ARF476FL
.320
The package design clamps the ceramic base to the heatsink. A
clamped joint maintains the required mounting pressure while allowing for thermal expansion of both the base and the heat sink.
Four 4-40 (M3) screws provide the required mounting force. T = 6
in-lb (0.68 N-m).
1.250
.175
.150
.150
.325
.175
The rated power dissipation is only available when the package
mounting surface is at 25°C and the junction temperature is 175°C
.
The thermal resistance between junctions and case mounting surface is 0.16°C/W. When installed, an additional thermal impedance
of 0.15°C/W between the package base and the mounting surface
is typical. Insure that the mounting surface is smooth and flat.
Thermal joint compound must be used to reduce the effects of
small surface irregularities. Use the minimum amount necessary to
coat the surface. The heatsink should incorporate a copper heat
spreader to obtain best results.
050-4931 B 6-2007
.200
.300
.005 .040
1.500
HAZARDOUS MATERIAL WARNING
The white ceramic portion of the device between leads
and mounting surface is beryllium oxide, BeO. Beryllium
oxide dust is toxic when inhaled. Care must be taken during handling and mounting to avoid damage to this area.
These devices must never be thrown away with general
industrial or domestic waste.
Microsemi’s products are covered by one or more of U.S.patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522
5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. US and Foreign patents pending. All Rights Reserved.