CD4042BM/CD4042BC Quad Clocked D Latch General Description Features The CD4042BM/CD4042BC quad clocked ‘‘D’’ latch is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors. The outputs Q and Q either latch or follow the data input depending on the clock level which is programmed by the polarity input. For polarity e 0; the information present at the data input is transferred to Q and Q during 0 clock level; and for polarity e 1, the transfer occurs during the 1 clock level. When a clock transition occurs (positive for polarity e 0 and negative for polarity e 1), the information present at the input during the clock transition is retained at the outputs until an opposite clock transition occurs. Y Connection Diagram Truth Table Dual-In-Line Package Y Y Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Clock polarity control Fully buffered data inputs Q and Q outputs 3.0V to 15V 0.45 VDD (typ.) Fan out of 2 driving 74L or 1 driving 74LS Clock Polarity Q 0 L 1 K 0 0 1 1 D Latch D Latch Order Number CD4042B TL/F/5966 – 1 Top View Logic Diagrams TL/F/5966 – 2 TL/F/5966 – 3 TL/F/5966 – 4 C1995 National Semiconductor Corporation TL/F/5966 RRD-B30M105/Printed in U. S. A. CD4042BM/CD4042BC Quad Clocked D Latch March 1988 Absolute Maximum Ratings (Notes 1 and 2) Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4042BM CD4042BC b 0.5V to a 18V b 0.5V to VDD a 0.5V b 65§ C to a 150§ C 3V to 15V 0V to VDD b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4042BM (Note 2) Symbol Parameter b 55§ C Conditions Min IDD Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VOH VIL VIH IOL IOH IIN lIOl k 1 mA, VIH e VDD, VIL e 0V VDD e 5V VDD e 10V VDD e 15V Max High Level Input Voltage lIOl k 1 mA VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V lIOl k 1 mA VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V Min a 125§ C Max 1 2 4 0.02 0.02 0.02 1 2 4 30 60 120 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.5 6.75 Min Units Typ High Level Output Voltage lIOl k 1 mA, VIH e VDD, VIL e 0V VDD e 5V 4.95 VDD e 10V 9.95 VDD e 15V 14.95 Low Level Input Voltage a 25§ C Max 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 V V V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.5 8.25 3.5 7.0 11.0 V V V Low Level Output Current VIH e VDD, VIL e 0V (Note 4) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA High Level Output Current VIH e VDD, VIL e 0V (Note 4) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.64 b 1.6 b 4.2 b 0.51 b 1.3 b 3.4 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA Input Curent VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V b 0.1 0.1 b 10 b 5 b 0.1 10b5 0.1 b 1.0 1.0 mA mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: Being a latch, the CD4042BM/CD4042BC is not clock rise and fall time sensitive. Note 4: IOH and IOL are tested one output at a time. 2 DC Electrical Characteristics CD4042BC (Note 2) Symbol Parameter b 40§ C Conditions Min IDD Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VOH VIL VIH IOL IOH IIN lIOl k 1 mA, VIH e VDD, VIL e 0V VDD e 5V VDD e 10V VDD e 15V Max High Level Input Voltage lIOl k 1 mA VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V lIOl k 1 mA VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V a 85§ C Max 4 8 16 0.02 0.02 0.02 4 8 16 30 60 120 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 1.5 3.0 4.0 5 10 15 2.25 4.5 6.75 Min Units Typ High Level Output Voltage lIOl k 1 mA, VIH e VDD, VIL e 0V VDD e 5V 4.95 VDD e 10V 9.95 VDD e 15V 14.95 Low Level Input Voltage a 25§ C Min Max 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 V V V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.5 8.25 3.5 7.0 11.0 V V V Low Level Output Current VIH e VDD, VIL e 0V (Note 4) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.52 1.3 3.6 0.44 1.1 3.0 0.88 2.25 8.8 0.36 0.9 2.4 mA mA mA High Level Output Current VIH e VDD, VIL e 0V (Note 4) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.52 b 1.3 b 3.6 b 0.44 b 1.1 b 3.0 b 0.88 b 2.25 b 8.8 b 0.36 b 0.9 b 2.4 mA mA mA Input Curent VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V b 0.3 0.3 b 10 b 5 b 0.3 10b5 0.3 b 1.0 1.0 mA mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: Being a latch, the CD4042BM/CD4042BC is not clock rise and fall time sensitive. Note 4: IOH and IOL are tested one output at a time. 3 AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, Input tr e tf e 20 ns, unless otherwise specified Symbol Parameter Conditions Typ Max Units tPHL, tPLH Propagation Delay Time Data In to Q VDD e 5V VDD e 10V VDD e 15V Min 175 75 60 350 150 120 ns ns ns tPHL, tPLH Propagation Delay Time Data In to Q VDD e 5V VDD e 10V VDD e 15V 150 75 50 300 150 100 ns ns ns tPHL, tPLH Propagation Delay Time Clock to Q VDD e 5V VDD e 10V VDD e 15V 250 100 80 500 200 160 ns ns ns tPHL, tPLH Propagation Delay Time Clock to Q VDD e 5V VDD e 10V VDD e 15V 250 115 90 500 230 180 ns ns ns tH Minimum Hold Time VDD e 5V VDD e 10V VDD e 15V 60 30 25 120 60 50 ns ns ns tSU Minimum Setup Time VDD e 5V VDD e 10V VDD e 15V 0 0 0 50 30 25 ns ns ns tW Minimum Clock Pulse Width VDD e 5V VDD e 10V VDD e 15V 100 50 30 200 100 60 ns ns ns tTHL, tTLH Transition Time VDD e 5V VDD e 10V VDD e 15V 125 60 50 250 125 100 ns ns ns CIN Input Capacitance Any Input 5.0 7.5 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: Being a latch, the CD4042BM/CD4042BC is not clock rise and fall time sensitive. Note 4: IOH and IOL are tested one output at a time. 4 Switching Time Waveforms TL/F/5966 – 5 5 CD4042BM/CD4042BC Quad Clocked D Latch Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4042BMJ or CD4042BCJ NS Package Number J16A Molded Dual-In-Line Package (N) Order Number CD4042BMN or CD4042BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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