N LM9810/20 10/12-Bit Image Sensor Processor Analog Front End General Description The LM9810 and LM9820 are high performance Analog Front Ends (AFEs) for image sensor processing systems. The LM9810/20 performs all the analog and mixed signal functions (correlated double sampling, color specific gain and offset correction, and analog to digital conversion) necessary to digitize the output of a wide variety of CIS and CCD sensors. The LM9810 has a 10 bit 6MHz ADC, and the LM9820 has a 12 bit 6MHz ADC. The LM9810 and LM9820 are pin-for-pin and functionally compatible. Features • • • • Key Specifications • • • • Applications • • • • • 6 million pixels/s conversion rate Digitally programmed gain and offset for red, green and blue pixels Correlated Double Sampling for lowest noise TTL/CMOS input/output compatible Color Flatbed Document Scanners Color Sheetfed Scanners Multifunction Imaging Products Digital Copiers General Purpose Linear CCD Imaging Output Data Resolution Pixel Conversion Rate Supply Voltage Power Dissipation 10/12 Bits 6MHz 5V±5% 300mW Connection Diagrams VREFVREFMID VREF+ RefBypass OSR OSG OSB AGND VA SampCLK 1 2 3 4 5 6 7 8 9 10 LM9810 & LM9820 20 19 18 17 16 15 14 13 12 11 DGND VD MCLK D5 D4 D3 D2 (SCLK) D1 (Latch) D0 (SDI) NewLine Ordering Information Commercial (0°C ≤ TA ≤ +70°C) LM9810CCWM LM9810CCWMX LM9820CCWM LM9820CCWMX Package 20 Pin Wide SOIC 20 Pin Wide SOIC, Tape & Reel 20 Pin Wide SOIC 20 Pin Wide SOIC, Tape & Reel TRI-STATE® is a registered trademark of National Semiconductor Corporation. ©1997,1998 National Semiconductor Corporation 1 http://www.national.com LM9810/20 10/12-Bit Image Sensor Processor Analog Front End July 1998 Block Diagram MCLK SampCLK OSR M U X OSG ADC Clock 0 to 2V Sampler x3 PGA VSIG 10/12 bit 6MHz ADC M U X 6 D5-D0 OSB 2 Vsignal VREF+ or VREF- Mux Select x3 Boost Gain of 1 or 3 1 Sampling Mode Offset DAC Offset 6 D2,D1,D0 programming interface .93 to 3 PGA Gain 5 3 VREF+ VREFMID VREF- Bandgap Voltage Reference Vreference RefBypass SampCLK Configuration Register NewLine Sampling Mode, Offset & Gain for R,G,B DGND AGND VD VA http://www.national.com Absolute Maximum Ratings (Notes 1 & 2) Operating Ratings (Notes 1 & 2) (V+=VA=VD) Positive Supply Voltage With Respect to GND=AGND=DGND Voltage On Any Input or Output Pin Input Current at any pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Soldering Information Infrared, 10 seconds (Note 6) Storage Temperature Operating Temperature Range TMIN=0°C≤TA≤TMAX=+70°C VA Supply Voltage +4.75V to +5.25V VD Supply Voltage +4.75V to +5.25V ≤ 100mV |VA-VD| OSR, OSG, OSB Input Voltage Range -0.05V to VA + 0.05V NewLine, SampCLK, D0-D2, MCLK Input Voltage Range -0.05V to VD + 0.05V 6.5V -0.3V to V++0.3V ±25mA ±50mA (Note 4) 2000V 300°C -65°C to +150°C Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7, 8, & 12) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) CCD/CIS Source Requirements for Full Specified Accuracy and Dynamic Range (Note 12) VOS PEAK Sensor’s Maximum Peak Differential Signal Range Gain = 0.933 Gain = 3.0 Gain = 9.0 2.1 0.65 0.21 V V V 5 pF Analog Input Characteristics OSR, OSG, OSB Input Capacitance OSR, OSG, OSB Input Leakage Current Measured with OS = 3.5VDC CDS disabled, selected OS input 20 CDS disabled, unselected OS input 10 25 µA (max) nA Coarse Color Balance PGA Characteristics Monotonicity 5 bits (min) V/V (min) V/V (max) G0 (Minimum PGA Gain) PGA Setting = 0 0.93 .90 .96 G31 (Maximum PGA Gain) PGA Setting = 31 3.0 2.96 3.15 V/V (min) V/V (max) x3 Boost Gain x3 Boost Setting On (bit B5 of Gain Register is set) 3.0 2.93 3.05 V/V (min) V/V (max) ±0.4 1.67 % (max) Gain Error at any gain (Note 13) Internal Reference Characteristics VREFMID Mid Supply Output Voltage 2.5 V VREF+ Positive Reference Output Voltage 3.5 V VREF- Negative Reference Output Voltage 1.5 V ∆VREF Differential Reference Voltage VREF+ - VREF- 2.0 V 3 http://www.national.com LM9810 Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. All LSB limits are in units of the LM9810’s 10 bit ADC. (Notes 7, 8, & 12) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) ADC Characteristics 10 bits (min) INL Integral Non-Linearity Error (Note 11) Resolution with No Missing Codes ±0.35 ±1.5 LSB (max) DNL Differential Non-Linearity ±0.25 ±1.0 LSB (max) Full Channel Linearity (Note 14) INL Integral Non-Linearity Error (Note 11) ±0.9 LSB DNL Differential Non-Linearity ±0.40 LSB Static Offset DAC Characteristics Monotonicity 6 bits (min) Offset DAC LSB size PGA gain = 1 5 3.4 6.4 LSB (min) LSB (max) Offset DAC Adjustment Range PGA gain = 1 ±150 ±140 LSB (min) 502 468 532 LSB (min) LSB (max) System Characteristics (see section 1.7.1, Internal Offsets) C Analog Channel Gain Constant (ADC Codes/V) Includes voltage reference variation, gain setting = 1 VOS1 Pre-Boost Analog Channel Offset Error, CCD Mode 4.4 -7.2 +15.7 LSB (min) LSB (max) VOS1 Pre-Boost Analog Channel Offset Error, CIS Mode 4.5 -6.5 +15.2 LSB (min) LSB (max) VOS2 Pre-PGA Analog Channel Offset Error -10 -28 +5.3 LSB (min) LSB (max) VOS3 Post-PGA Analog Channel Offset Error -11 -30.6 +7.3 LSB (min) LSB (max) LM9820 Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. All LSB limits are in units of the LM9820’s 12 bit ADC. (Notes 7, 8, & 12) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) ADC Characteristics 12 bits (min) INL Integral Non-Linearity Error (Note 11) Resolution with No Missing Codes ±1.1 ±4.0 LSB (max) DNL Differential Non-Linearity ±0.6 +1.75 -1.0 LSB (max) Full Channel Linearity (Note 14) INL Integral Non-Linearity Error (Note 11) ±3.4 LSB DNL Differential Non-Linearity ±0.65 LSB 4 http://www.national.com LM9820 Electrical Characteristics (Continued) The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. All LSB limits are in units of the LM9820’s 12 bit ADC. (Notes 7, 8, & 12) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) 6 bits (min) Static Offset DAC Characteristics Monotonicity Offset DAC LSB size PGA gain = 1 20 14 26 LSB (min) LSB (max) Offset DAC Adjustment Range PGA gain = 1 ±590 ±575 LSB (min) 2008 1873 2129 LSB (min) LSB (max) System Characteristics (see section 1.7.1, Internal Offsets) C Analog Channel Gain Constant (ADC Codes/V) Includes voltage reference variation, gain setting = 1 VOS1 Pre-Boost Analog Channel Offset Error, CCD Mode 17.6 -32.1 +68.9 LSB (min) LSB (max) VOS1 Pre-Boost Analog Channel Offset Error, CIS Mode 18 -22.2 +57 LSB (min) LSB (max) VOS2 Pre-PGA Analog Channel Offset Error -40 -94.3 +16.4 LSB (min) LSB (max) VOS3 Post-PGA Analog Channel Offset Error -44 -121 +28 LSB (min) LSB (max) DC and Logic Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) D0-D2, MCLK, NewLine, SampCLK Digital Input Characteristics VIN(1) Logical “1” Input Voltage VD=5.25V 2.0 V (max) VIN(0) Logical “0” Input Voltage VD=4.75V 0.8 V (min) IIN Input Leakage Current VIN=VD VIN=DGND CIN Input Capacitance 0.1 -0.1 µA(max) µA(max) 5 pF D0-D5 Digital Output Characteristics VD=4.75V, IOUT=-360µA VD=4.75V, IOUT=-10µA VOUT(1) Logical “1” Output Voltage VOUT(0) Logical “0” Output Voltage VD=5.25V, IOUT=1.6mA TRI-STATE® Output Current (D0-D5 only) VOUT=DGND VOUT=VD 0.1 -0.1 IOUT 2.4 4.4 V (min) V (min) 0.4 V (max) µA µA Power Supply Characteristics IA Analog Supply Current Operating Standby with input clocks stopped Standby with input clocks running 45 0.8 3.0 57 0.9 mA (max) mA (max) mA ID Digital Supply Current (Note 15) Operating Standby with input clocks stopped Standby with input clocks running 220 110 220 320 200 µA (max) µA (max) µA 5 http://www.national.com AC Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, tMCLK=1/fMCLK, tr=tf=5ns, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8) Limits (Note 10) Units (Limits) Maximum MCLK Frequency 24 MHz (min) MCLK Duty Cycle 40 60 % (min) % (max) Symbol fMCLK Parameter tMCLK MCLK period tSCNL SampCLK falling edge before NewLine falling edge tSampCLK Conditions Typical (Note 9) 41 SampCLK period ns (min) 3 tMCLK(min) 4 tMCLK(min) tSampLo Low time for SampCLK 50 ns (min) tSampHi High time for SampCLK 50 ns (min) tSampSU SampCLK falling edge before rising edge of MCLK 4 ns (min) tDDO falling edge of MCLK before new valid data 40 ns (max) tHDO hold time of current data from falling edge of MCLK 15 ns (min) tSCLK D2(SCLK) Serial Clock Period tDSU Input data setup time before D2(SCLK) rising edge 0 ns (min) tDH Input data hold time after D2(SCLK) rising edge 3 ns (min) tSCLKLA D2(SCLK) rising edge after bit B0 before D1(Latch) rising edge 3 ns (min) tLASCLK D1(Latch) rising edge before next D2(SCLK) rising edge 3 ns (min) High time for D1(Latch) 3 tMCLK (min) 3 tSampCLK (min) tLA tLANL 1 D1(Latch) rising edge before NewLine falling edge tMCLK(min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN<GND or VIN>VA or VD), the current at that pin should be limited to 25mA. The 50mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, ΘJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / ΘJA. T Jmax = 150°C for this device. The typical thermal resistance (ΘJA) of this part when board mounted is 84°C/W for the M20B SOIC package. Note 5: Human body model, 100pF capacitor discharged through a 1.5kΩ resistor. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear Data Book for other methods of soldering surface mount devices. 6 http://www.national.com Note 7: Two diodes clamp the OS analog inputs to AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up. VA TO INTERNAL CIRCUITRY OS Input AGND Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin. Note 9: Typicals are at TJ=TA=25°C, fMCLK = 24MHz, and represent most likely parametric norm. Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 11: Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC. Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output voltage for a white (full scale) image with respect to the reference level, VREF . VRFT is defined as the peak positive deviation above VREF of the reset feedthrough pulse. The maximum correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the LM9810/20 can correct for using its internal PGA. CCD Output Signal VRFT VWHITE VREF Note 13: Gain PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula code 32 V ---- = G + X PGA --------------------------- where X = ( G – G ) ------ . PGA V 0 31 0 31 32 Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and an offset register setting of 0 (000000b). Note 15: The digital supply current (ID) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (D5 - D0). The current required to switch the digital data bus can be calculated from: Isw = 2*Nd*Psw*CL*VD/tSampCLK where Nd is total number of data pins, Psw is the probability of each data bit switching, CL is the capacitive loading on each data pin, VD is the digital supply voltage and tSampCLK is the period of the SampCLK signal. Since Nd is 6, Psw should be .5, and VD is nominally 5V, the switching current can usually be calculated from: Isw = 30*CL/tSampCLK. For example, if the capacitive load on each digital output pin (D5 - D0) is 20pF and the period of tSampCLK is 1/6MHz or 167ns , then the digital switching current would be 7.2mA. The calculated digital switching current will be drawn through the VD pin and should be considered as part of the total power budget for he LM9810/20. 7 http://www.national.com Pin Descriptions Analog Power VA This is the positive supply pin for the analog supply. It should be connected to a voltage source of +5V and bypassed to AGND with a 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. AGND This is the ground return for the analog supply. Digital Power Analog Inputs. These inputs (for Red, Green, and Blue) should be tied to the sensor’s OS (Output Signal) through DC blocking capacitors. RefBypass Internally generated reference voltage bypass pin. It should be bypassed to AGND through a .05uF monolithic capacitor. VREF+, VREFMID, VREF- SampCLK NewLine DGND This is the ground return for the digital supply. D5-D0 LM9810 Output Mode (NewLine Low) Voltage reference bypass pins. They should each be bypassed to AGND through a .05uF monolithic capacitor. Input & Timing Control MCLK This is the positive supply pin for the digital supply. It should be connected to a voltage source of +5V and bypassed to DGND with a 0.1µF monolithic capacitor. Digital I/O Analog I/O OSR, OSG, OSB, VD Master Clock. The ADC conversion rate will be a maximum of ¼ of MCLK. Nominally 24MHz. Sample Clock. SampCLK controls the conversion rate of the ADC (up to ¼ of the MCLK rate) and sample timing. The signal level is sampled while SampCLK is low and held on the rising edge of SampCLK. When CDS is enabled, the falling edge of SampCLK causes the CCD reference level to be held. If CDS is not enabled, VREF+ or VREF- is held on the falling edge of SampCLK, depending on the programmed signal polarity. SampCLK is also used with NewLine to clamp the external coupling capacitors. New Line signal. Used to indicate the start of active pixels on a new line, to allow clamping of the AC coupling caps, and to allow programming of the configuration register. When NewLine is high and SampCLK is low, the OS inputs will be connected to either VREF+ or VREF-. On the first rising edge of MCLK after NewLine goes low, the internal mux and the offset and gain settings will be set to the appropriate values for the first color of the next line set in the color mode setting in the Sampler and Color Mode Register. When NewLine is low, D[5-0] transmit the pixel conversion data from the ADC. When NewLine is high, D[5-0] enter TRISTATE and D2, D1 and D0 act as a serial interface for programming the configuration registers. Data Input/Output pins. When NewLine is low, the 10 or 12 bit conversion results of the ADC are multiplexed to D5-D0. When NewLine is high, the output drivers enter TRISTATE and D2, D1 & D0 act as a serial interface for writing to the configuration registers. MCLK0, MCLK1, MCLK2, MCLK3 D5 b9, b9, b3, b3 D4 b8, b8, b2, b2 D3 b7, b7, b1, b1 D2 b6, b6, b0, b0 D1 b5, b5, 0, 0 D0 b4, b4, 0, 0 LM9820 Output Mode (NewLine Low) MCLK0, MCLK1, MCLK2, MCLK3 D5 b11, b11, b5, b5 D4 b10, b10, b4, b4 D3 b9, b9, b3, b3 D2 b8, b8, b2, b2 D1 b7, b7, b1, b1 D0 b6, b6, b0, b0 Input Mode (NewLine High) D5-D3 Don’t Care D2 (SCLK) Serial Data Clock. D1 (Latch) Latch and shift enable signal. When D1(Latch) is low, data is shifted into D0(SDI). When D1(Latch) goes high, the last nine bits shifted into D0(SDI) will be used to program the addressed configuration register. To avoid erroneous writes to the configuration registers, D1(Latch) should be pulled low when NewLine is high. D0 (SDI) 8 Serial input data. Data is valid on D2(SCLK) rising edge. Three address bits followed by six data bits (MSB first) should be shifted into D0 before D1(Latch) goes high. http://www.national.com Timing Diagrams Diagram 1: Pixel Conversion Timing and Latency Diagram 2: SampCLK and Output Data Timing (NewLine low) Diagram 3: Timing for Programming the Configuration Registers 9 http://www.national.com Timing Diagrams NewLine RS OS O ptic al B lack P ixel O ptica l B lack Pix el First A ctive P ixe l CLAMP OFF Clamp Signal (Internal) Clamp On SampCLK Diagram 4: CCD Clamping Timing Ø1 (Even/Odd Mode) Ø2 (Even/Odd Mode) Ø1 (Standard Mode) Ø2 (Standard Mode) CCD Reset signal OS SampCLK Diagram 5: CDS Timing 10 http://www.national.com Table 1: Configuration Register Address Table Address (Decimal) Address (Binary) Data Bits A2 A1 A0 0 0 0 B5 B4 B3 B3 B2 B1 Mode1 Mode0 Sampler and Color Mode 0 CDS Polarity N/A Mode2 Red DAC Offset Setting 1 0 0 1 Polarity MSB LSB Green DAC Offset Setting 2 0 1 0 Polarity MSB LSB Blue DAC Offset Setting 3 0 1 1 Polarity MSB LSB Red Gain Setting 4 1 0 0 x3 MSB LSB Green Gain Setting 5 1 0 1 x3 MSB LSB Blue Gain Setting 6 1 1 0 x3 MSB LSB Production Test and Power Down 7 1 1 1 Test Test 11 Test Test Test PD http://www.national.com Table 2: Configuration Register Parameters Parameter (Address) Control Bits Result Sampler and Color Mode (0) CDS Enable (0) B5 0 1 CDS Enabled Single Ended (CDS disabled) Signal Polarity (0) B4 0 1 Negative Polarity Positive Polarity B2 0 B1 0 B0 0 Line Rate Color - Mux, Gain & Offset change at the line rate: *1st line: Mux = OSR, Gain & Offset = R 2nd line: Mux = OSG Gain & Offset = G 3rd line: Mux = OSB Gain & Offset = B repeat… * state of the first line after a write to this register Color Mode (0) 0 0 1 Single Input Color - Mux selects OSB input. Gain & Offset change at the pixel rate: Gain & Offset = R,G,B,R,G,B… 0 1 0 RESERVED 0 1 1 Monochrome Mux selects OSR input. Gain & Offset = R 1 0 0 Monochrome Mux selects OSG input. Gain & Offset = G 1 0 1 Monochrome Mux selects OSB input. Gain & Offset = B 0 Bayer - Mux selects OSB input. Gain & Offset change at the pixel rate: *1st line: Gain & Offset = G,R,G,R,... 2nd line: Gain & Offset = B,G,B,G,… repeat… * state of the first line after a write to this register 1 Green Stripe - Mux selects OSB input. Gain & Offset change at the pixel rate: *1st line: Gain & Offset = R,G,B,G,R,G,B,... 2nd line: Gain & Offset = B,G,R,G,B,G,R,… repeat… * state of the first line after a write to this register 1 1 1 1 12 http://www.national.com Table 2: Configuration Register Parameters (Continued) Parameter (Address) Control Bits Result Red, Green and Blue Offset DAC Settings (1, 2 & 3) Offset Polarity (1,2 & 3) B5 0 1 Offset Value (1,2 & 3) B4(MSB) B3 B2 B1 B0(LSB) B4 (MSB) 0 0 0 ••• 1 1 0 0 0 ••• 1 1 B3 B2 B1 Typical Offset Values (1,2 & 3) B5 (SIGN) 0 0 0 ••• 0 0 1 1 1 ••• 1 1 0 0 0 ••• 1 1 0 0 0 ••• 1 1 0 0 0 ••• 1 1 0 0 0 ••• 1 1 0 0 1 ••• 1 1 0 0 1 ••• 1 1 Positive Offset Negative Offset LM9810: Offset = 5LSBs * Offset Value * PGA Gain LM9820: Offset = 20LSBs * Offset Value * PGA Gain Typical Offset (with PGA Gain = 1) B0 (LSB) 0 1 0 ••• 0 1 0 1 0 ••• 0 1 LM9810 LSBs 0.00 +5 +10 ••• +150 +155 0 -5 -10 ••• -150 -155 LM9820 LSBs 0.00 +20 +40 ••• +600 +620 0 -20 -40 ••• -600 -620 Red, Green and Blue Gain Settings (4,5 & 6) Boost Gain Enable (4,5 & 6) B5 0 1 PGA Gain Value (4,5 & 6) B4 Boost Gain = 1V/V Boost Gain = 3V/V B3 B2 Gain (4,5 & 6) Typical Gain Values (4, 5 & 6) B1 B0 PGA Gain (V/V) =.933 + 0.0667 * (PGA Gain Value) Gain = Boost Gain * PGA Gain B5 (x3) 0 0 0 ••• 0 0 0 ••• 1 1 1 ••• 1 1 1 B4 (MSB) 0 0 0 ••• 1 1 1 ••• 0 0 0 ••• 1 1 1 B3 B2 B1 0 0 0 ••• 1 1 1 ••• 0 0 0 ••• 1 1 1 0 0 0 ••• 1 1 1 ••• 0 0 0 ••• 1 1 1 0 0 1 ••• 0 1 1 ••• 0 0 1 ••• 0 1 1 13 B0 (LSB) 0 1 0 ••• 1 0 1 ••• 0 1 0 ••• 1 0 1 Typical Gain (V/V) 0.93 1.00 1.13 ••• 2.87 2.93 3.00 ••• 2.79 3.00 3.20 ••• 8.60 8.80 9.00 http://www.national.com Table 2: Configuration Register Parameters (Continued) Parameter (Address) Control Bits Result Production Test and Power Down (7) Production Test (7) B5 Power Down Enable (7) B0 0 1 B4 B3 B2 B1 Should all be set to zero for normal operation Normal Operation Power Down 14 http://www.national.com Applications Information reduced ([VSIGNAL+VRESIDUAL]-VRESIDUAL = VSIGNAL). This is the principal of Correlated Double Sampling. 1.0 Programming the LM9810/20 If the LM9810/20 is programmed for correlated double sampling (bit B5 of register 0 is cleared), then the falling edge of SampCLK should occur toward the end of period 3 and the rising edge of SampCLK should occur towards the end of period 4. While SampCLK is high, the Reference level (VRESIDUAL) is sampled, and it is held at the falling edge of SampCLK. While SampCLK is low, the signal level (VSIGNAL+ VRESIDUAL) is sampled and it is held at the rising edge of SampCLK. The output from the sampler is the potential difference between the two samples, or VSIGNAL. 1.1 Writing to the Configuration Register When NewLine is high, D2, D1 & D0 act as a serial interface for writing to the configuration registers. D2 is the input serial clock (SCLK), D0 is the input data pin (SDI), and D1 is the latch and shift enable signal (Latch). When D1(Latch) is low, serial data is shifted into D0(SDI), and must be valid on each rising edge of D2(SCLK). Three register address bits followed by six data bits should be shifted into D0(SDI), MSB first. When D1(Latch) transitions from low to high, the last 6 data bits will be stored into the configuration register addressed by the previous 3 address bits (as shown in Diagram 3). D1(Latch) must remain high for at least 3 cycles of the serial clock on D2(SCLK) to write to the configuration register. 1.3 CIS Mode The LM9810/20 supports CIS (Contact Image Sensor) devices by offering a sampling mode for capturing positive going signals, as opposed to the CCD’s negative going signal. The output signal of a CIS sensor (Figure 2) differs from a CCD signal in two primary ways: its output increases with increasing signal strength, and it does not usually have a reference level as an integral part of the output waveform of every pixel. 1.2 CDS Mode The LM9810/20 uses a high-performance CDS (Correlated Double Sampling) circuit to remove many sources of noise and error from the CCD signal. It also supports CIS image sensors with a single sampling mode. OS (CIS) Figure 1 shows the output stage of a typical CCD and the resulting output waveform: VDD Q1 C1 RS (RESET) OS (CCD) e(from shift register) Q2 1 OS 2 3 4 5 SampCLK VSS Figure 2: CIS When the LM9810/20 is in CIS mode (Register 0, B5=1), it uses either VREF+ or VREF- depending on the signal polarity setting (B4 of the Sampling and Color Mode register) as the reference (or black) voltage for each pixel. If the signal polarity is set to one, then VREF- will be held on the falling edge of SampCLK and the OS signal will be held on the rising edge of SampCLK. If it is set to zero, then VREF+ will be held on the falling edge of SampCLK and the OS signal will be held on the rising edge of SampCLK. The rising edge of SampCLK should occur near the end of period 4, and at least 50ns after the falling edge of SampCLK. Ø1 RS OS 1 2 3 4 5 SampCLK Figure 1: CDS Capacitor C1 converts the electrons coming from the CCD’s shift register to an analog voltage. The source follower output stage (Q2) buffers this voltage before it leaves the CCD. Q1 resets the voltage across capacitor C1 between pixels at intervals 2 and 5. When Q1 is on, the output signal (OS) is at its most positive voltage. After Q1 turns off (period 3), the OS level represents the residual voltage across C1 (VRESIDUAL). VRESIDUAL includes charge injection from Q1, thermal noise from the ON resistance of Q1, and other sources of error. When the shift register clock (Ø1) makes a low to high transition (period 4), the electrons from the next pixel flow into C1. The charge across C1 now contains the voltage proportional to the number of electrons plus VRESIDUAL, an error term. If OS is sampled at the end of period 3 and that voltage is subtracted from the OS at the end of period 4, the VRESIDUAL term is canceled and the noise on the signal is 1.4 Multiplexer/Channel Switching The offset and gain settings automatically switch after each ADC conversion according to the color mode setting in the Sampler and Color Mode register (register 0). For example, if the color mode (bits B2,B1 & B0) is set to 001, the offset and gain will alternately switch between the R, G and B settings after each conversion. The input multiplexer never changes during a line, but if the color mode is set to Line Rate Color (000), the mux will automatically switch after each new line. The offset and gain settings will always start with the first channel of the programmed mode after a falling edge on NewLine. For 15 http://www.national.com example, the R offset and gain settings will be used for the first conversion following a falling edge on NewLine if the color mode is set to Single Input Color (001). 1.7 Offset DAC The Offset DAC removes the DC offsets generated by the sensor and the LM9810/20’s analog signal chain (see section 1.7.1, Internal Offsets). The DAC value for each color (registers 1,2 and 3) should be set during calibration to the lowest value that still results in an ADC output code greater than zero for all the pixels when scanning a black line. With a PGA gain of 1V/V, each LSB of the offset DAC typically adds the equivalent of 5 LM9810 LSBs or 20 LM9820 LSBs, providing a total offset adjustment range of ±150 LM9810 LSBs or ±590 LM9820 LSBs. The Offset DAC’s output voltage is given by: For the Single Input Color, Bayer and Green Stripe modes, the mux will always connect the OSB input to the sampler. The offset and gain settings will alternate values every pixel according to the order indicated by the Sampler and Color Mode register (see Table 2). The first falling edge of NewLine following a write to the Sampler and Color Mode register will ready the offset and gain to cycle through the colors of the first line of the programmed color mode. Each subsequent falling edge of NewLine will switch the offset and gain settings to the first color of the next line. The LM9810/20’s unused OS inputs should not be left unconnected. All three OS inputs should be tied together on the LM9810/20 side of the clamp capacitor (see Figure 3). V DAC = 9.75mV ⋅ (value in B4 - B0) Equation 2: Offset DAC Output Voltage In terms of output codes, the offset is given by: Offset = 5LSBs ⋅ (value in B4 - B0) ⋅ PGA Gain CCLAMP OS SENSOR DOS Equation 3: LM9810 Offset Equation OSB NC OSG Offset = 20LSBs ⋅ (value in B4 - B0) ⋅ PGA Gain OSR Equation 4: LM9820 Offset Equation The offset is positive if bit B5 is cleared and negative if B5 is set. Since the analog offset is added before the PGA gain, the value of the PGA gain must be considered when selecting the offset DAC values. LM9810/20 Figure 3: OS Connections for single output sensors For the Line Rate Color mode, the mux will cycle through the OSR, OSG and OSB inputs after each falling edge of NewLine. The R, G 1.7.1 Internal Offsets and B offset & gain settings will be used when the mux is set to the OSR, OSG and OSB input, respectively. OSR and the R offset & gain settings will always be used on the first line following a write register 0. Figure 4 is a model of the LM9810/20’s internal offsets. Equation 5 shows how to calculate the expected output code given the input voltage (VIN), the LM9810/20 internal offsets (VOS1, VOS2, VOS3), the programmed offset DAC voltage (VDAC), the programmed gains (GB, GPGA) and the analog channel gain constant C. 1.5 Data Latency The latency through the LM9810/20 is 8 SampCLK periods plus one MCLK period. The data output on D5 - D0 (MSBs b11 - b6 or b9 - b4) represents data whose reference signal was sampled 8 tSampCLK + tMCLK + tSampSU earlier (see Diagram 1). C is a constant that combines the gain error through the AFE, reference voltage variance, and analog voltage to digital code conversion into one constant. Ideally, C = 2048 codes/V (4096 codes/2V) for the LM9820 and 512 codes/V (1024 codes/2V) for the LM9810. Manufacturing tolerances widen the range of C (see Electrical Specifications). 1.6 Programmable Gain The output of the Sampler drives the input of the x3 Boost gain stage. The gain of the x3 Boost gain is 3V/V if bit B5 of the current color’s gain register (registers 4,5, and 6) is set, or 1V/V if bit B5 is cleared. The output of the x3 gain stage is the input to the offset DAC and the output of the offset DAC is the input to the PGA (Programmable Gain Amplifier). The PGA provides 5 bits of gain correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The x3 Boost gain stage and the PGA can be combined for an overall gain range of .93V/V to 9.0V/V (-.6 to 19dB). The gain setting for each color (registers 4, 5 and 6) should be set during calibration to bring the maximum amplitude of the strongest pixel to a level just below the desired maximum output from the ADC. The PGA gain is determined by the following equation: x3 Boost 1V/V or 3V/V VIN + Σ GB + VOS1 PGA 0.93V/V to 3V/V + + Σ + Σ GPGA Σ + + + VOS3 VOS2 VDAC ADC DOUT Offset DAC Figure 4: Internal Offset Model V PGA Gain ---- = 0.933 + .0667 (value in bits B4-B0) V Equation 1: PGA Gain D OUT = ( ( ( V IN + V OS1 )G B + V DAC + V OS2 )G PGA + V OS1 )C Equation 5: Output code calculation with internal offsets If the x3 Boost gain is enabled then the overall signal gain will be three times the PGA gain. Equation 6 is a simplification of the output code calculation, neglecting the LM9810/20’s internal offsets. 16 http://www.national.com the LM9810/20 is operating in CDS mode. In CDS mode, the LM9810/20 leakage current should be no more than 20nA. With CDS disabled, which will likely be the case when CIS sensors are used, the LM9810/20 leakage current can be as high as 25uA at the maximum conversion rate. D OUT = ( V IN G B + V DAC )G PGA C Equation 6: Simplified output code calculation 1.8 Power Down Mode 2.1.1 CDS mode Minimum Clamp Capacitor Calculation: Setting the Power Down (bit B0 of register 7) puts the device in a low power standby mode. The analog sections are turned off to conserve power. The digital logic will continue to operate if MCLK continues, so for minimum power dissipation MCLK should be stopped when the LM9810/20 enters the Power Down mode. Recovery from Power Down typically takes 50µs (the time required for the reference voltages to settle to 0.5 LSB accuracy). The following equation takes the maximum leakage current into the OS input, the maximum allowable droop, the number of pixels on the sensor, and the pixel conversion rate, fSampCLK, and provides the minimum clamp capacitor value: C 2.0 Clamping CLAMP MIN i = --------- dt dV leakage current (A) number of pixels = --------------------------------------------------- -------------------------------------------f SampCLK max droop(V) Equation 7: CDS mode CCLAMP MIN Calculation To perform a DC restore across the AC coupling capacitors at the beginning of every line, the LM9810/20 implements a clamping function. When NewLine is high and SampCLK is low, all three OS inputs will be connected to either VREF+ or VREF-, depending on B4 of the Sampling and Color Mode register. If B4 is set to one (positive signal polarity), then the OS inputs will be connected to VREF. If B4 is set to zero (negative signal polarity), then they will be connected to VREF+. For example, if the OS input leakage current is 20nA worst-case, the sensor has 2700 active pixels, the conversion rate is 2MHz (tSampCLK = 500ns), and the max droop desired is 0.1V, the minimum clamp capacitor value is: 20nA 2700 C CLAMP MIN = -------------- --------------0.1V 2MHz = 270pF Equation 8: CDS mode CCLAMP MIN Example 2.1 Clamp Capacitor Selection This section explains how to select appropriate clamp capacitor values. CCLAMP OS SENSOR DOS 2.1.2 CIS mode Minimum Clamp Capacitor Calculation: If CDS is disabled, then the maximum LM9810/20 OS input leakage current can be calculated from: OS I leakage = V SAT f SampCLK C SAMP NC VREF+ or VREF- Equation 9: CIS mode Input Leakage Current Calculation LM9810/20 where VSAT is the peak pixel signal swing of the CIS OS output and CSAMP is the capacitance of the LM9810/20’s internal sampling capacitor (2pF). Inserting this into Equation 7 results in: Figure 5: OS Clamp Capacitor and Internal Clamp i C CLAMP MIN = --------- dt dV V SAT t SampCLK = ---------------------------C SAMP ------------------------------------ num pixels t SampCLK max droop(V) The output signal of many sensors rides on a DC offset (greater than 5V for many CCDs) which is incompatible with the LM9810/20’s 5V operation. To eliminate this offset without resorting to additional higher voltage components, the output of the sensor is AC coupled to the LM9810/20 through a DC blocking capacitor, CCLAMP. The sensor’s DOS output, if available, is not used. The value of this capacitor is determined by the leakage current of the LM9810/20’s OS input and the output impedance of the sensor. The leakage through the OS input determines how quickly the capacitor value will drift from the clamp value of VREF+ or VREF-, which then determines how many pixels can be processed before the droop causes errors in the conversion (±0.1V is the recommended limit for CDS operation). The output impedance of the sensor determines how quickly the capacitor can be charged to the clamp value during the black reference period at the beginning of every line. Equation 10: CIS mode CCLAMP MIN Calculation with CSAMP equal to 2pF and VSAT equal to 2V (the LM9810/20’s maximum input signal), then Equation 10 reduces to: 4p(F)(V) C CLAMP MIN = ------------------------------------ num pixels max droop(V) Equation 11: CIS mode CCLAMP MIN Calculation In CIS mode (CDS disabled), the max droop limit must be much more carefully chosen, since any change in the clamp capacitor’s DC value will affect the LM9810/20’s conversion results. If a droop of one 10 bit LSB across a line is considered acceptable, then the allowed droop voltage is calculated as: 2V/1024, or The minimum clamp capacitor value is determined by the maximum droop the LM9810/20 can tolerate while converting one sensor line. The minimum clamp capacitor value is much smaller for CDS mode applications than it is for CIS mode applications. The LM9810/20 input leakage current is considerably less when 17 http://www.national.com approximately 2mV. If there are 2700 active pixels on a line then: required before the capacitor settles to the desired accuracy: C Initial Error Voltage CLAMP lines = R CLAMP ------------------------- ln ---------------------------------------------------- Final Error Voltage t CLAMP 4p(F)(V) = ---------------------- 2700 C CLAMP MIN 2mV = 5.4uF Equation 16: Number of Lines Required for Clamping Equation 12: CIS mode CCLAMP MIN Calculation Example Using the values shown before and a clamp capacitor value of 0.01µF, this works out to be: 5V 0.01µF lines = 1550 ------------------- ln ------------ = 13.5 lines 0.1V 4.5µs Equation 17: Clamping Lines Required Example 2.1.3 Maximum Clamp Capacitor Calculation: The maximum size of the clamp capacitor is determined by the amount of time available to charge it to the desired value during the optical black portion of the sensor output. The internal clamp is on when NewLine is high and SampCLK is low. If the applied SampCLK is low for half its cycle, then the available charge time per line can be calculated using: In this example, a 0.01µF capacitor takes 14 lines after power-up to charge to its final value. On subsequent lines, the only error will be the droop across a single line which should be significantly less than the initial error. If the LM9810/20 is operating in CDS mode and multiple lines are used to charge up the clamping capacitors after power-up, then a clamp capacitor value of 0.01µF should be significantly greater than the calculated CCLAMP MIN value and can virtually always be used. Number of optical black pixels t CLAMP = ------------------------------------------------------------------------------2f SampCLK Equation 13: Clamp Time Per Line Calculation For example, if a sensor has 18 black reference pixels and fSampCLK is 2MHz with a 50% duty cycle, then tCLAMP is 4.5µs. If the LM9810/20 is operating in CIS mode, then significantly larger clamp capacitors must be used. Fortunately, the output impedance of most CIS sensors is significantly smaller than the output impedance of CCD sensors, and RCLAMP will be dominated by the 50Ω from the LM9810/20’s internal clamp switch. With a smaller RCLAMP value, the clamp capacitors will charge faster. The following equation takes the number of optical black pixels, the amount of time (per pixel) that the clamp is closed, the sensor’s output impedance, and the desired accuracy of the final clamp voltage and provides the maximum clamp capacitor value that allows the clamp capacitor to settle to the desired accuracy within a single line: 3.0 Performance Considerations t 1 C CLAMP MAX = ------ -------------------------------R ln(accuracy) t CLAMP 1 = -------------------------- -------------------------------R CLAMP ln(accuracy) Equation 14: CCLAMP MAX for a single line of charge time 3.1 Power Supply The LM9810/20 should be powered by a single +5V source. The analog supplies (VA) and the digital supply (VD) are brought out individually to allow separate bypassing for each supply input. They should not be powered by two or more different supplies. Where tCLAMP is the amount of time (per line) that the clamp is on, RCLAMP is the output impedance of the CCD plus 50Ω for the LM9810/20’s internal clamp switch, and accuracy is the ratio of the worst-case initial capacitor voltage to the desired final capacitor voltage. If tCLAMP is 4.5µs, the output impedance of the sensor is 1500Ω, the worst case voltage change required across the capacitor (before the first line) is 5V, and the desired accuracy after clamping is to within 0.1V (accuracy = 5/0.1 = 50), then: 4.5µs 1 CCLAMP MAX = ------------------ --------------1550Ω ln(50) = 728pF Equation 15: CCLAMP MAX Example The final value for CCLAMP should be less than or equal to CCLAMP MAX, but no less than CCLAMP MIN. In systems with separate analog and digital +5V supplies, all the supply pins of the LM9810/20 should be powered by the analog +5V supply. Each supply input should be bypassed to its respective ground with a 0.1µF capacitor located as close as possible to the supply input pin. A single 10µF tantalum capacitor should be placed near the VA supply pin to provide low frequency bypassing. To minimize noise, keep the LM9810/20 and all analog components as far as possible from noise generators, such as switching power supplies and high frequency digital busses. If possible, isolate all the analog components and signals (OS, reference inputs and outputs, VA, AGND) on an analog ground plane, separate from the digital ground plane. The two ground planes should be tied together at a single point, preferably the point where the power supply enters the PCB. In some cases, depending primarily on the choice of sensor, CCLAMP MAX may actually be less than CCLAMP MIN, meaning that the capacitor can not be charged to its final voltage during the black pixels at the beginning of a line and hold it’s voltage without drooping for the duration of that line. This is usually not a problem because in most applications the sensor is clocked continuously as soon as power is applied. In this case, a larger capacitor can be used (guaranteeing that the CCLAMP MIN requirement is met), and the final clamp voltage is forced across the capacitor over multiple lines. This equation calculates how many lines are 3.2 SampCLK Timing SampCLK is used to time the stages of the LM9810/20’s sampler, offset DAC and programmable gain amplifier. To allow for optimum input signal sampling times, SampCLK may be applied asynchronously to MCLK. The LM9810/20’s ADC is synchronized with the its AFE (including the sampler, the offset DAC and the PGA) by MCLK. The LM9810/20’s internal ADC clock is created through a combi- 18 http://www.national.com nation of the applied SampCLK and MCLK signals. MCLK is used to synchronize the applied SampCLK signal. The internal ADC clock will go low after the falling edge of SampCLK is clocked by a rising of MCLK. The ADC clock will stay low for two MCLK cycles and then go high. It will stay high until the next falling edge of SampCLK is clocked by MCLK. Figure 6 illustrates this SampCLK, MCLK, and ADC clock timing relationship. MCLK SampCLK ADC Clock (internal) D5 - D0 b11 - b6 b5 - b0 Figure 6: LM9810/20 Relative Event Timing The LM9810/20 is a densely designed, mixed-signal, monolithic semiconductor. In creating the timing for the LM9810/20, it must be considered that internal events, such as ADC sampling, and output data bus switching can potentially affect coincident events such as input signal sampling or offset DAC settling. One event can interfere with another by coupling noise on shared resources such as the supply lines, internal voltage references, or the silicon substrate. To optimize the performance of the LM9810/20, SampCLK should be timed so that the input signal hold times do not coincide with output data switching and ADC clock transitions. In other words, the rising and falling edges of SampCLK should not be placed close to ADC clock edges or to output data transitions. SampCLK edges should be at least 20ns away from ADC clock edges to avoid interference between the ADC and the sampler. SampCLK edges should also be placed at least 40ns after output data transition times to avoid transition noise coupling. Figure 6 is an example of SampCLK timing that will meet these requirements at the maximum MCLK frequency of 24MHz. In diagram 6, SampCLK transitions occur on MCLK falling edges which will keep them more than 20ns away from ADC transitions, and 40ns after output data transitions. 19 http://www.national.com Physical Dimensions inches (millimeters) 20 pin (.300” Wide) Molded Small Outline Package 20 http://www.national.com LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. N 2. 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