HOLTEK HT47C06L

HT47C06L
R-F Type Low Voltage 8-Bit Mask MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 1.2V~2.2V
· One LCD driver with 13´3 or 14´2 segments
· Eight bidirectional I/O lines
· HALT function and wake-up feature reduce power
· On-chip 32kHz~128kHz RC oscillator (External R)
consumption
· RC type A/D converter
· Two-level subroutine nesting
· Watchdog timer
· Bit manipulation instruction
· 1K´16 program memory ROM
· 16-bit table read instruction
· 32´8 data memory RAM
· Up to 31ms instruction cycle with128kHz system clock
· One time base (TB)
· 63 powerful instructions
· One buzzer output (BZ, BZ)
· All instructions in one or two machine cycles
· One EL carrier output
· 44-pin QFP package
· One externally adjustable low voltage detector
General Description
The advantages of low power consumption, I/O flexibility,
timer functions, oscillator options, RC type A/D converter,
LCD driver, HALT and wake-up functions, enhance the
versatility of these device to suit a wide range of Resistor
to Frequency application possibilities such as sensor signal processing, remote metering, and particularly suitable for use as clinical thermometer MCU device.
The HT47C06L is an 8-bit, high performance RISC architecture microcontroller device specifically designed
for applications that interface directly to analog signals,
such as those from sensors. Its single cycle instruction
and two-stage pipeline architecture make it suitable for
high speed applications.
Rev. 1.00
1
June 15, 2007
HT47C06L
Block Diagram
S y s te m
In te rru p t
C ir c u it
P ro g ra m
R O M
S T A C K 1
S T A C K 0
P ro g ra m
C o u n te r
M
M P
U
Y S
)
T E
IN T C
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T im e r A
A /D
In s tr u c tio n
R e g is te r
C lo c k ( fS
T N 1
T N 0
R C
T y p e
A /D
C o n v e rte r
T im e r B
D A T A
M e m o ry
X
C lo c k
T N 1
T N 0
T O N
R C IN
R R E F
R S E N
T im e B a s e
W D T
M U X
In s tr u c tio n
D e c o d e r
L C D
P A
P A
P A
P A
P A
P A
P A
P A
S h ifte r
P A
O S C 1
B P
R C O s c illa to r
O S C 2
A C C
L C D
M e m o ry
C 1
C 2
D o u b le
V o lta g e
V C C
L V D
7
6
5
4
3
0 /B Z
1 /B Z
2 /E L
L V D
V D D
L C D D r iv e r
C O M 0 ~
C O M 1
C lo c k
B Z /B Z
P o rt A
S T A T U S
A L U
T im in g
G e n e ra to r
fS Y S = 3 2 k H z
S y s te m
V S S
R E S
T R IM 1
S E G 0 ~
S E G 1 2
C O M 2 /
S E G 1 3
T R IM 2
Pin Assignment
C 1
C
C
C
D
S
2
1
P
P
P
P
P
S E G 0
V C C
C 2
N
N
N
V D
O S C
O S C
R E
P A 0
P A 1
P A 2
L
N C
V D
/B Z
/B Z
/E L
A 3
A 4
A 5
A 6
A 7
N C
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
3 3
2
3 2
3
3 1
4
3 0
5
2 9
H T 4 7 C 0 6 L
4 4 Q F P -A
6
7
2 8
2 7
8
2 6
9
2 5
1 0
2 4
1 1
2 3
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1
2
4
3
5
6
8
7
9
1 0
1 1
S E
C O
C O
C O
N C
N C
R R
R S
R C
V S
N C
S
G 1 2
M 2 /S E G 1 3
M 1
M 0
E F
E N
IN
Rev. 1.00
2
June 15, 2007
HT47C06L
Pad Description
Pad Name
RES
I/O
I
Function
Schmitt trigger reset input. Active low
I/O
I/O
Bidirectional 2-bit input/output port. Each bit can be a wake-up input. The PA0 and PA1 are
pin-shared with the BZ and BZ, respectively. Once the PA0 and PA1 are selected as buzzer
driving outputs, the output signals come from an internal buzzer clock generator.
Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (mask option).
PA2/EL
I/O
Bidirectional 1-bit input/output port. This bit can be a wake-up input. The PA2 is pin-shared
with the EL carrier output. Once the PA2 is selected as EL carrier output, the output signal
comes from an internal EL carrier clock generator. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (mask option).
PA3~PA7
I/O
Bidirectional 5-bit input/output port. Each bit can be a wake-up input.
Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (mask option).
VSS
¾
Negative power supply, ground
VCC, C1, C2
¾
Voltage doubler, VCC=2´VDD
VCC: LCD power supply voltage, connect a capacitor between VCC and VSS.
C1, C2: Switching pins for VCC, connect a capacitor between C1 and C2.
COM0~COM1,
COM2/SEG13
O
The 1/3 LCD duty cycle configuration option will determine whether pin COM2/SEG13 is
configured as a SEG13 segment driver or as a common COM2 output driver for the LCD
panel. COM0~COM1 are the LCD common outputs.
SEG0~SEG12
O
LCD driver outputs for LCD panel segments.
VDD
¾
Positive power supply
LVD
¾
Low voltage detector. Connect a resistor between VSS and LVD.
RCIN
I
RC type A/D converter input pin for RC oscillation.
RREF
O
RC type A/D converter output pin for reference resistor oscillation.
RSEN
O
RC type A/D converter output pin for sensor resistor oscillation.
OSC1
OSC2
¾
System oscillator pin, connect a resistor between OSC1 and OSC2.
PA0/BZ
PA1/BZ
TRIM1~TRIM2
I
TEST mode input pin. Let open in normal mode.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+2.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
June 15, 2007
HT47C06L
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
¾
¾
1.2
1.5
2.2
V
VCC
LCD Voltage
¾
VCC=2´VDD
2.4
3
4.4
V
VLVD
Low Voltage Detector Voltage
¾
*RLVD=30kW
1.25
1.3
1.35
V
No load, fSYS=32kHz,
A/D Off, LVD disabled
¾
10
20
mA
No load, fSYS=32kHz,
A/D On, LVD disabled,
*R=30kW, *C=2200pF
¾
30
60
mA
No load, fSYS=128kHz,
A/D Off, LVD disabled
¾
15
30
mA
No load, fSYS=128kHz,
A/D On, LVD disabled,
*R=30kW, *C=2200pF
¾
35
70
mA
IDD
Operating Current
1.5V
ILVD
LVD Current
1.5V LVD enabled
¾
50
100
mA
ISTB1
Standby Current
(LVD Disabled, LCD Off)
No load, system HALT
1.5V
A/D Off, LVD Off
¾
¾
1
mA
No load, fSYS=32kHz,
A/D Off, LVD disabled
¾
5
10
mA
ISTB2
Standby Current
(LCD On)
No load, fSYS=128kHz,
A/D Off, LVD disabled
¾
8
16
mA
1.5V
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.8VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
IOL1
I/O Port Sink Current
1.5V VOL=0.15V
(PA0/BZ, PA1/BZ, PA2/EL, PA3~PA7)
0.5
0.8
¾
mA
IOH1
I/O Port Source Current
1.5V VOH=1.35V
(PA0/BZ, PA1/BZ, PA2/EL, PA3~PA7)
-0.3
-0.6
¾
mA
IOL2
I/O Port Sink Current
(RREF, RSEN)
1.5V VRREF, RSEN=0.15V
4
7
¾
mA
IOH2
I/O Port Source Current
(RREF, RSEN)
1.5V VRREF, RSEN=1.35V
-3
-5
¾
mA
IOL3
Common Output Sink Current
1.5V VOL=0.3V (1/2 bias)
50
100
¾
mA
IOH3
Common Output Source Current
1.5V VOH=2.7V(1/2 bias)
-50
-100
¾
mA
IOL4
Segment Output Sink Current
1.5V VOL=0.3V (1/2 bias)
50
100
¾
mA
IOH4
Segment Output Source Current
1.5V VOH=2.7V(1/2 bias)
-50
-100
¾
mA
RPH
Pull-high Resistance
1.5V VIL=0V
75
150
300
kW
Note:
*R stands for the RC type A/D converter resistance
*C stands for the RC type A/D converter capacitance
*RLVD value may be different for different lots
Rev. 1.00
4
June 15, 2007
HT47C06L
A.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
Conditions
VDD
Min.
Typ.
Max.
Unit
25
¾
154
kHz
fSYS
System Clock
1.5V
tRES
External Reset Low Pulse Width
1.5V
¾
100
¾
¾
ms
fAD
A/D Converter Frequency
1.5V
¾
¾
¾
50
kHz
External R
Functional Description
Execution Flow
Program Counter - PC
The HT47C06L system clock is derived from a built-in
RC oscillator with external resistor. The system clock is
internally divided into four non-overlapping clocks (T1,
T2, T3 and T4). One instruction cycle consists of four
system clock cycles.
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 1024
addresses.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
This pipelining scheme ensures that instructions are effectively executed in one cycle. Exceptions to this are instructions that change the contents of the program
counter, such as subroutine calls or jumps, in which
case, two cycles are required to complete the instruction.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
In s tr u c tio n C lo c k
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
Timer/event Counter Interrupt
0
0
0
0
0
0
0
1
0
0
Time Base Interrupt
0
0
0
0
0
0
1
0
0
0
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter + 2
Program Counter
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
S9~S0: Stack register bits
Rev. 1.00
@7~@0: PCL bits
5
June 15, 2007
HT47C06L
· Table location
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, etc., the microcontroller manages program
control by loading the address corresponding to each instruction.
Any location within the program memory can be used
as a look-up table where programmers can store fixed
data. The instructions TABRDC [m] (the current page,
1 page=256 words) and TABRDL [m] (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH(08H). Only the destination of the lower-order
byte in the table is well-defined, the higher-order byte
of the table word are transferred to the TBLH. The table higher-order byte (TBLH) is a read only register.
The table pointer (TBLP) is a read/write register(07H),
which indicates the table location. Before accessing
the table, the location must be placed in the TBLP.
The TBLH is read only and cannot be restored. If the
main routine and the ISR (interrupt service routine)
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the ISR. Errors
can occur. In other words using the table read instruction in the main routine and the ISR simultaneously
should be avoided. However, if the table read instruction has to be applied in both the main routine and the
ISR, the interrupt is supposed to be disabled prior to
the table read instruction. It will not be enabled until
the TBLH has been backed up. All table related instructions need two cycles to complete the operation.
These areas may function as normal program memory depending upon the requirements.
For conditional skip instructions, once the condition has
been met, the next instruction, which has already been
fetched during the current instruction execution, is discarded and a dummy cycle replaces it while the proper
instruction is obtained. Otherwise proceed with the next
instruction.
The lower byte of the program counter (PCL) is available for program control and is a readable and writeable
register (06H). Moving data into the PCL performs a
short jump. The destination will be within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory - ROM
The program memory is used to store the program instructions, which are to be executed. It also contains
data, table information and interrupt entries, and is organized into 1024´16 bits, addressed by the program
counter and table pointer registers.
Certain locations within the program memory are reserved for special usage:
· Location 000H
0 0 0 H
This area is reserved for use by the chip reset for program initialization. After a chip reset is initiated, the
program will jump to this location and begin execution.
0 0 4 H
0 0 8 H
· Location 004H
This area is reserved for the timer/event counter interrupt service program. If timer interrupt results from a
timer/event counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program
will jump to this location and begin execution.
D e v ic e In itia liz a tio n P r o g r a m
T im e r /e v e n t C o u n te r In te r r u p t S u b r o u tin e
T im e B a s e In te r r u p t S u b r o u tin e
P ro g ra m
R O M
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 008H
This area is reserved for the time base interrupt service program. If a time base interrupt occurs, and if the
interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
L o o k - u p T a b le ( 2 5 6 w o r d s )
3 F F H
1 6 b its
N o te : n ra n g e s fro m
0 to 3
Program Memory
Instruction(s)
Table Location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *9~*0: Bits of table location
@7~@0: Bits of table pointer
P9~P8: Bits of current program counter
Rev. 1.00
6
June 15, 2007
HT47C06L
Stack Register - STACK
some dedicated bits, each bit in the data memory can be
set and reset by the SET [m].i and CLR [m].i instruction,
respectively. They are also indirectly accessible through
memory pointer registers (MP0;01H, MP1;03H).
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into two levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledge
signal, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the stack pointer will
point to the top of the stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent two return addresses is stored).
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
T B C
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
0 E H
S p e c ia l P u r p o s e
D a ta M e m o ry
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
P A
P A C
1 4 H
1 5 H
Data Memory - RAM
1 6 H
1 7 H
The data memory has a capacity of 52´8 bits and is divided into two functional groups: special function registers and general-purpose data memory (32´8). Most are
read/write, but some are read only.
1 8 H
1 9 H
1 A H
1 B H
The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0 (MP0;
01H), the indirect addressing register 1 (02H), the memory
pointer register 1 (MP1;03H), the bank pointer (BP;04H),
the accumulator (ACC;05H), the program counter
lower-order byte register (PCL;06H), the table pointer
(TBLP;07H), the table higher-order byte register
(TBLH;08H), the time base control register (TBC;09H), the
status register (STATUS;0AH), the interrupt control register 0 (INTC;0BH), the I/O registers (PA;12H), I/O port control register (PAC;13H), the timer/event counter A
higher-order byte register (TMRAH; 20H), the timer/event
counter A lower-order byte register (TMRAL; 21H), the
timer/event counter control register (TMRC; 22H), the
timer/event counter B higher-order byte register (TMRBH;
23H), the timer/event counter B lower-order byte register
(TMRBL; 24H), the RC oscillator type A/D converter control register (ADCR; 25H).
1 C H
1 D H
1 E H
1 F H
2 0 H
T M R A H
2 1 H
T M R A L
2 2 H
T M R C
2 3 H
T M R B H
2 4 H
T M R B L
2 5 H
2 6 H
A D C R
5 F H
6 0 H
7 F H
: U n u s e d
R e a d a s "0 0 "
G e n e r a l- P u r p o s e
D a ta M e m o ry
(3 2 B y te s )
RAM Mapping (Bank 0)
Indirect Addressing Register
The remaining space before the 60H are reserved for future expanded usage and reading these location will return the result 00H. The general-purpose data memory,
addressed from 60H to 7FH, is used for data and control
information under instruction command.
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation to [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H indirectly will return a result of 00H.
Writing indirectly results in no operation.
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for
Rev. 1.00
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
7
June 15, 2007
HT47C06L
register will not change the TO or PDF flags. In addition it should be noted that operations related to the
status register may give different results from those
intended. The TO and PDF flags can only be
changed by the watchdog timer overflow, system
power-up, clearing the watchdog timer and executing the HALT instruction.
The function of data movement between two indirect addressing registers are not supported. The memory
pointer registers, MP0 and MP1, are both 8-bit registers
which can be used to access the data memory by combining corresponding indirect addressing registers.
MP0 only can be applied to data memory, while MP1
can be applied to the data memory and the LCD display
memory.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Accumulator
In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
status are important and if the subroutine can corrupt
the status register, precautions must be taken to save it
properly.
The accumulator is closely related with operations carried out by the ALU. It is mapped to location 05H of the
data memory and is the place where all immediate results from the ALU are stored. Data movement between
two data memory locations must pass through the accumulator.
Interrupts
Arithmetic and Logic Unit - ALU
The HT47C06L provides an internal timer/event counter
interrupt and an internal time base interrupt. The interrupt control register (INTC;0BH) contains the interrupt
control bits to set the enable/disable and interrupt request flags.
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Once an interrupt subroutine is serviced, all other interrupts will be blocked by clearing the EMI bit. This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval, but
only the interrupt request flag is recorded. If another interrupt requires servicing while the program is in the interrupt service routine, the programmer should set the
EMI bit and the corresponding bit of the INTC to allow interrupt nesting. If the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate
service is desired, the stack must be prevented from becoming full.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified locations in the pro-
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
can also change the status register.
Status Register - STATUS
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by
executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by
a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
STATUS (0AH) Register
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June 15, 2007
HT47C06L
Bit No.
Label
Function
0
EMI
Controls the master or global interrupt (1=enabled; 0=disabled)
1
ETI
Controls the timer/event counter interrupt (1=enabled; 0=disabled)
2
ETBI
Controls the time base interrupt (1=enabled; 0=disabled)
3
¾
Unused bit, read as ²0²
4
TF
Timer/event counter interrupt request flag (1=active; 0=inactive)
5
TBF
6~7
¾
Time base interrupt request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC (0BH) Register
If an RC oscillator is used, it requires that an external resistor is connected between OSC1 and OSC2. The RC
oscillator provides the most cost effective solution. However, the oscillation frequency may vary with VDD, temperature and process variations on the chip itself. It is
therefore not suitable for applications involving timing
sensitive operations or where accurate oscillator frequencies are required.
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program
which corrupts the desired control sequence, the contents must be saved first.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag (TF;
bit 4 of INTC), caused by a timer A or timer B overflow.
When the interrupt is enabled, and the stack is not full
and the TF bit is set, a subroutine call to location 04H will
occur. The related interrupt request flag (TF) will be reset
and the EMI bit cleared to disable further interrupts.
O S C 1
O S C 2
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC), caused
by a regular time base signal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a
subroutine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit
cleared to disable further interrupts.
R C
System Oscillator
Watchdog Timer - WDT
The WDT clock source (fS) is fSYS. The timer is designed to
prevent software malfunctions or sequences from jumping to unknown locations with unpredictable results. The
Watchdog timer can be disabled by mask option. If the
Watchdog timer is disabled, all the executions related to
the WDT result in no operation.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not.
The ²HALT² instruction is executed, WDT still counts if fOSC
is on and can wake-up from HALT mode due to the WDT
time-out.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Timer/event counter interrupt
1
04H
Time base interrupt
2
08H
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
wherein only the program counter and stack pointer are
reset to zero. To clear the contents of the WDT, three
methods are adopted. The first is an external hardware
reset (a low level on the RES pin), the second is via software instructions, and the third is via a ²HALT² instruction. The software instruction is CLR WDT. Any
execution of the CLR WDT instruction will clear the
WDT. The WDT may reset the chip due to time-out.
Vector
The WDT time-out period ranges from fS/215~fS/216. The
²CLR WDT² instruction only clears the last two-stage of
the WDT.
Oscillator Configuration
There is one external RC oscillator.
One method to generating the system clock is using an
external RC network. The HALT mode turned off the
system oscillator and ignores an external signal to conserve power.
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HT47C06L
· The WDT will be cleared and resume counting.
Multi-function Timer
· All I/O ports maintain their original status.
The HT47C06L provides a multi-function timer for the
WDT and time base but with different time-out periods.
The multi-function timer consists of an 8-stage divider
and a 7-bit prescaler, with the clock source coming from
fSYS. The multi-function timer also provides a selectable
frequency signal (ranges from fS/23 to fS/26) for LCD
driver circuits, and a selectable frequency signal
(ranges from fS/22 to fS/25) for the buzzer output by options. It is recommended to select a near 4kHz signal to
LCD driver circuits for proper display.
· The PDF flag is set and the TO flag is cleared.
· The LCD driver can be turned off or on depending on
the LCD option.
· The time base will stop or keep running depending on
the LCD option.
Port A wake-up and external interrupt wake-up methods
can be considered as a continuation of normal execution. Awakening from an I/O port stimulus, the program
will resume execution at the next instruction. If awakening from an external interrupt, two possibilities may
occur. If the external interrupt is disabled or the external
interrupt is enabled but the stack is full, the program will
resume execution at the next instruction. If the external
interrupt is enabled and the stack is not full, a regular interrupt response takes place.
Time Base - TB
The time base is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by
software programming. Writing data to RT2, RT1 and
RT0 (bits 2, 1, 0 of TBC;09H) yields various time-out
periods. If a time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC) is set. But if the interrupt is enabled, and the stack is not full, a subroutine
call to location 08H occurs. When the HALT instruction
is executed, the time base still works and can wake-up
from HALT mode if fOSC is on. If the TBF is set to ²1² before entering the HALT mode, the wake-up function will
be disabled.
RT2
RT1
RT0
Time Base
Divided Factor
0
0
0
28
0
0
1
29
0
1
0
210
0
1
1
211
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
If an external interrupt request flag is set to ²1² before
entering the HALT mode, the wake-up function of the related interrupt will be disabled.
If the wake-up results from an external interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by more than one cycle. However, if
the wake-up results in the next instruction execution following the ²HALT², the execution will be performed immediately.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT mode.
Reset
There are three ways in which a reset may occur.
· RES reset during normal operation
· RES reset during HALT mode
· WDT time-out reset during normal operation
The WDT time-out reset during HALT mode is different
from other chip reset conditions, since it can perform a
warm reset that just resets the program counter and
stack pointer leaving the other circuits in their original
state. Some registers remain unchanged during other
reset conditions. Most registers are reset to the ²initial
condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish
between different ²chip resets².
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The fOSC and fSYS will still work or stop depending on
the LCD option, but T1 will be turned off.
· The contents of the on-chip RAM and registers remain
unchanged.
S y s te m
C lo c k ( fS
Y S
)
fS
fS /2
8
fS /2
8 - s ta g e D iv id e r
L C D D r iv e r fS /2 3 ~ fS /2
1 5
fS /2
7 - b it P r e s c a le r
T F F
R
8 to 1 M u x .
R T 0 ~ R T 2
6
B u z z e r fS /2 2~ fS /2
5
1 6
T F F
R
T im e - o u t R e s e t
1 5
1 6
fS /2 ~ fS /2
W D T C le a r
T im e B a s e O u t
Multi-function Timer
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HT47C06L
H A L T
W a rm
W D T
T im e - o u t
R e s e t
W D T
V
D D
V D D
E x te rn a l
R E S
fS
R e s e t
C o ld
R e s e t
R E S
R E S
S S T
1 0 - b it R ip p le
C o u n te r
Y S
tS S T
S S T T im e - o u t
C h ip
R e s e t
P o w e r - o n D e te c tio n
R e s e t C ir c u it
R e s e t C o n fig u r a tio n
TO PDF
0
0
u
R e s e t T im in g C h a r t
RESET Conditions
Item
Condition After Reset
System power-up
Program Counter Reset to 000H
u
RES or LVR reset during normal operation
Interrupts
All interrupts will be disabled
0
1
RES reset or LVR reset wake-up from HALT
mode
Prescaler, Divider
All timer counter prescaler, divider
will be cleared
1
u
WDT time-out during normal operation
WDT, Time Base
1
1
WDT wake-up from HALT mode
Clear after master reset, WDT begins counting
Note: ²u² stands for unchanged
Timer/event
Counter
All timer counters will be turned off
The following table indicates the way in which the various functional units are affected after a reset occurs.
Input/output Ports All I/O ports will be setup as inputs
Stack Pointer
Stack pointer will point to the top of
the stack
The states of the registers are summarized in the following table:
Register
Reset
(Power On)
WDT time-out
(Normal Operation)
RES reset
(Normal Operation)
RES reset
(HALT)
WDT time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
000H
000H
000H
000H
000H*
TBLP
xxxx xxxx
uuuu uuuu
uuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBC
---- -111
---- -111
---- -111
---- -111
---- -uuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
--00 -000
--00 -000
--00 -000
--00 -000
--uu -uuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
-000 1---
-000 1---
-000 1---
-000 1---
-uuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
---x 0000
---x 0000
---x 0000
---x 0000
---u uuuu
Note:
²*² refers to warm reset
²u² means unchanged
²x² means unknown
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HT47C06L
The TMRC is the timer/event counter control register,
which defines the timer/event counter options. The
timer/event counter control register defines the operating mode, counting enable or disable and active edge.
Writing to timer B location puts the starting value in the
timer/event counter preload register, while reading timer
A yields the contents of the timer/event counter. Timer B
is the timer/event counter preload register.
Timer/Event Counter
One 16-bit timer/event counter or RC type A/D converter is implemented in the HT47C06L. The ADC/TM
bit (bit 1 of ADCR register) determines whether timer A
and timer B are composed of one 16-bit timer/event
counter or composed of an RC type A/D converter.
The TMRAL, TMRAH, TMRBL, TMRBH composed of
one 16-bit timer/event counter, when ADC/TM bit is ²0².
The TMRBL and TMRBH are timer/event counter
preload registers for lower-order byte and higher-order
byte respectively.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source (A/D clock) comes
from an external (RCIN) pin. The timer mode functions
as a normal timer with the clock source coming from the
internal clock (fSYS). Finally, the pulse width measurement mode can be used to count the high or low level
duration of the external signal (A/D clock from
pad:RCIN). The counting is based on the system clock
(fSYS).
The timer/event counter clock source comes from system
clock (fSYS) or external source (A/D clock from pad:RCIN).
The external clock input allows the user to count external
events, count external RC type A/D clock, measure time intervals or pulse widths, or generate an accurate time base.
There are six registers related to the timer/event counter
operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC
([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR
([25H]). Writing to TMRBL only writes the data into a low
byte buffer, and writing to TMRBH will write the data and
the contents of the low byte buffer into the time/event
counter preload register (16-bit) simultaneously. The
timer/event counter preload register is changed by writing
to TMRBH operations and writing to TMRBL will keep the
timer/event counter preload register unchanged.
In the event count, A/D clock or internal timer mode,
once the timer/event counter starts counting, it will count
from the current contents in the timer/event counter
(TMRAH and TMRAL) to FFFFH. Once overflow occurs,
the counter is reloaded from the timer/event counter
preload register (TMRBH and TMRBL) and at the same
time generates the corresponding interrupt request flag
(TF; bit 4 of INTC).
In the pulse width measurement mode with the TON
and TE bits equal to one, once the RCIN has received a
transient from low to high (or high to low if the TE bit is
0) it will start counting until the A/D Clock returns to the
original level and resets the TON. The measured result
will remain in the timer/event counter even if the activated transient occurs again. In other words, only one
cycle measurement can be done. Until setting the TON,
Reading TMRAH will also latch the TMRAL into the low
byte buffer to avoid false timing problem. Reading
TMRAL returns the contents of the low byte buffer. In
other words, the low byte of the timer/event counter can
not be read directly. It must read the TMRAH first to
make the low byte contents of timer/event counter be
latched into the buffer.
S y s te m
C lo c k ( fS
Y S
)
T M 1
T M 0
A D C /T M = 0
T E
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
T N 0
A D C /T M
R
A D E N
T O N
( A D C R B it- 2 ) M o d e
D a ta B u s
T im e r /e v e n t c o u n te r
( 1 6 b it T im e r A )
to F c o n v e rte r
T im e r /e v e n t c o u n te r
P r e lo a d R e g is te r
( 1 6 b it T im e r B )
A D E N
M O D E
O v e r flo w
R e lo a d
R R E F
R S E N
3 0 k W
2 2 0 0 p F
C o n tro l
2 0 k W ~ 6 0 k W
A /D
C lo c k
R C IN
Timer/Event Counter
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HT47C06L
In the case of timer/event counter Off condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter turns On, data written to the
timer/event counter preload register is kept only in the
timer/event counter preload register. The timer/event
counter will still operate until overflow occurs.
the cycle measurement will function again as long as it
receives further transient pulse. Note that in this operation mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflow, the counter is reloaded from the timer/event counter preload register
and issues interrupt request just like the other two
modes.
When the timer/event counter (reading TMRAH) is read,
the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration.
To enable the counting operation, the timer on bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will automatically be
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by instructions.
It is strongly recommended to load first the desired
value into TMRBL, TMRBH, TMRAL, and TMRAH registers then turn on the related timer/event counter for
proper operation. Because the initial value of TMRBL,
TMRBH, TMRAL and TMRAH are unknown.
Bit No.
Label
Function
0~2
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
TON
To enable/disable timer counting
(0=disabled; 1=enabled)
5
6
TM0
TM1
To define the operating mode (TM1, TM0)
10=Timer mode (Internal clock: fSYS)
01=Event counter mode (External clock: A/D clock from pad RCIN)
11=Pulse width measurement mode (RCIN, fSYS)
00=Unused
7
¾
Unused bit, read as ²0²
TMRC (22H) Register
Example for Timer/event counter mode (disable interrupt):
clr tmrc
clr adcr.1
; set timer mode
clr intc.4
; clear timer/event counter interrupt request flag
mov a, low (65536-1000)
; give timer initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 01010000b
mov tmrc, a
; timer clock source=fSYS and timer on
p10:
clr wdt
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HT47C06L
multaneously. The timer A or timer B is changed by writing TMRAH/TMRBH operations and writing TMRAL/
TMRBL will keep the timer A or timer B unchanged.
RC Type A/D Converter
An RC type A/D converter is implemented in the
HT47C06L. The A/D converter contains two 16-bit programmable count-up counters and the timer A clock
source comes from the system clock (fSYS=32kHz). The
timer B clock source comes from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH are composed of the A/D converter when ADC/TM bit (bit 1 of
ADCR register) is ²1².
Reading TMRAH/TMRBH will also latch the
TMRAL/TMRBL into the low byte buffer to avoid false
timing problem. Reading TMRAL/TMRBL returns the
contents of the low byte buffer. In other words, the low
byte of timer A or timer B cannot be read directly. It must
read the TMRAH/TMRBH first to make the low byte contents of timer A or timer B be latched into the buffer.
The A/D converter timer B clock source may come from
RREF~RCIN oscillation, RSEN~RCIN oscillation or
RCIN external clock input. The timer A clock source is
the system clock by setting (TM1, TM0=1, 0).
The bit2 of ADCR decides which resistor and capacitor
compose an oscillation circuit and input to TMRBH and
TMRBL.
The TM0 and TM1 bits of TMRC define the timer A clock
source. It is recommended that the timer A clock source
use the system clock.
There are six registers related to the A/D converter, i.e.,
TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR.
The internal timer clock is input to TMRAH and TMRAL,
the A/D clock is input to TMRBH and TMRBL. The
OVB/OVA bit (bit 0 of ADCR register) determines
whether timer A or timer B overflows, then the TF bit is
set and timer interrupt occurs. When the A/D converter
mode timer A or timer B overflows, the TON bit is reset
and stop counting. Writing TMRAH/TMRBH makes the
starting value be placed in the timer A or timer B and
reading TMRAH/TMRBH retrieves the contents of the
timer A or timer B. Writing TMRAL/TMRBL only writes
t h e d a t a i n t o a l o w b y t e b u ff e r, a n d w r i t i n g
TMRAH/TMRBH will write the data and the contents of
the low byte buffer into the timer A or timer B (16-bit) si-
S y s te m
C lo c k ( fS
When the TON bit (bit 4 of the TMRC) is set to ²1² the
timer A and timer B will start counting until timer A or
timer B overflows, the timer/event counter generates the
interrupt request flag (TF ; bit 4 of INTC) and the timer A
and timer B stop counting and reset the TON bit to ²0² at
the same time.
If the TON bit is ²1², the TMRAH, TMRAL, TMRBH and
TMRBL cannot be read or written to. Only when the
timer/event counter is off and when the instruction
²MOV² is used can those four registers be read or written to.
)
Y S
A D C /T M = 1
T M 1
T M 0
D a ta B u s
T E
O V B /O V A = 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
In te rru p t
T im e r A
T O N
T M 0
A D C /T M
T O N
(A D C R
R
A D E N
to F c o n v e rte r
O V B /O V A = 1
A D E N
B it- 2 ) M o d e
T im e r B
M O D E
R e s e t T O N
R R E F
D a ta B u s
R S E N
3 0 k W
C R E F
2 2 0 0 p F
C o n tro l
2 0 k W ~ 6 0 k W
A /D
C lo c k
* A D E N is a c tiv e w h e n T O N = 1 in A /D m o d e fo r T im e r A & B ( A D C /T M = 1 ) o r
w h e n T O N = 1 a n d c lo c k s o u r c e is A /D c lo c k in T M R m o d e fo r T im e r A & B ( A D C /T M = 0 )
* A D C /T M
is b it 1 o f A D C R r e g is te r
R C IN /T M R
RC Type A/D Converter
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HT47C06L
Bit No.
Label
Function
0
OVB/OVA
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from timer A or timer B overflow.
(0= timer A overflow; 1= timer B overflow)
In the timer/event counter mode, this bit is void.
1
ADC/TM
Determines whether the 16-bit timer/event counter or RC type A/D converter is enabled.
(0= timer/event counter is enabled; 1= A/D converter is enabled)
2
MODE
3
BON
Low voltage detector disabled/enabled (0=disabled; 1=enabled)
4
BLF
Low voltage flag (0=battery power is good; 1=low battery)
5~7
¾
Defines the A/D converter operating mode
0= RREF~CREF oscillation (reference resistor and reference capacitor)
1= RSEN~CREF oscillation (resistor sensor and reference capacitor)
Unused bit, read as ²0²
ADCR (25H) Register
Example for RC type AD converter mode (Timer A overflow):
clr tmrc
clr adcr.1
clr intc.4
mov a, low (65536-1000)
mov tmrbl, a
mov a, high (65536-1000)
mov tmrbh, a
; set timer mode
; clear timers/event counter interrupt request flag
; give timer A initial value
; count 1000 time and then overflow
mov a, 00000010b
mov adcr, a
mov a, 00h
mov tmrbl, a
mov a, 00h
mov tmrbh, a
; RREF~CREF; set RC type ADC mode; set Timer A overflow
mov a, 01010000b
mov tmrc, a
; timer A clock source=fSYS and timer on
p10:
clr wdt
snz intc.4
jmp p10
clr intc.4
Rev. 1.00
; give timer B initial value
; polling timer/event counter interrupt request flag
; clear timer/event counter interrupt request flag
; program continue
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HT47C06L
Example for RC type AD converter mode (Timer B overflow):
clr tmrc
clr adcr.1
clr intc.4
mov a, 00h
mov tmrbl, a
mov a, 00h
mov tmrbh, a
; set timer mode
; clear timer/event counter interrupt request flag
; give timer A initial value
mov a, 00000011b
mov adcr,a
; RREF~CREF; set RC type ADC mode; set Timer B overflow
mov a, low (65536-1000)
mov tmrbl, a
mov a, high (65536-1000)
mov tmrbh, a
; give timer B initial value
; count 1000 time and then overflow
mov a, 00110000b
mov tmrc, a
; timer A clock source=fSYS and timer on
p10:
clr wdt
snz intc.4
jmp p10
clr intc.4
; polling timer/event counter interrupt request flag
; clear timer/event counter interrupt request flag
; program continue
Input/Output Ports
After a chip reset, these input/output lines remain at high
levels (pull-high). Each bit of these input/output latches
can be set or cleared by ²SET [m].i² (m=12H) instructions. Some instructions first input data and then follow
the output operations. For example, ²SET [m].i², ²CPLA
[m]², read the entire port states into the CPU, execute
the defined operations (bit-operation), and then write
the results back to the latches or to the accumulator.
There is an 8-bit bidirectional input/output port in the
microcontroller, labeled PA which is mapped to the data
memory [12H]. All of these I/O lines can be used as input and output operations. For the input operation, these
lines are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A, [m]²
(m=12H). For output operation, all the data is latched
and remain unchanged until the output latch is rewritten.
Each bit of the port A has the capability of waking-up the
device.
Each I/O line has its own control register (PAC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with pull-high
resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register has to be set as
²1². The pull-high resistor will be exhibited automatically. The input sources also depend on the control register. If the control register bit is ²1², the input will read
the pad state (²MOV² and read-modify-write instructions).If the control register bit is ²0², the contents of the
latches will move to internal data bus (²MOV² and
read-modify-write instructions). The input paths (pad
state or latches) of read-modify-write instructions are
dependent on the control register bits. For output function, CMOS is the only configuration. This control register is mapped to locations 13H.
Rev. 1.00
The PA0 and PA1 are pin-shared with BZ and BZ, respectively. If the BZ mode is selected, the output signal
in output mode of PA0 (or PA1) will be BZ (or BZ) signal.
The input mode always retain its original functions. The
4kHz buzzer output signals (in output mode) are controlled by the PA0 and PA1 data registers. The truth table of PA0/BZ and PA1/BZ are listed below.
PA1
PA0
Data Register Data Register
PA1, PA0
Pad Function
0 (CLR PA.1)
0 (CLR PA.0)
PA0=BZ, PA1=BZ
1 (SET PA.1)
0 (CLR PA.0)
PA0=BZ, PA1=0
X
1 (SET PA.0)
PA0=0, PA1=0
Mask Option
16
June 15, 2007
HT47C06L
V
C o n tr o l B it
D a ta B u s
P H
Q
D
C K
W r ite C o n tr o l R e g is te r
D D
Q B
S
C h ip R e s e t
P A 0 ~ P A 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
C K
W r ite D a ta R e g is te r
Q B
S
M
U
R e a d D a ta R e g is te r
S y s te m
X
W a k e -u p
Note: BZ and EL mode functions are not shown in this diagram
The PA2 is pin-shared with EL carrier signals. If the EL
carrier output is selected, the output signal in output
mode of PA2 will be the EL carrier signal. The input mode
always remains its original functions. The EL carrier output signal (in output mode) is controlled by the PA2 data
register. The truth table of PA2/EL is listed below.
P A .2 = 1
PA2
Data Register
PA2
Pad Function
0 (CLR PA.2)
PA2=0
1 (SET PA.2)
PA2=EL carrier output
P A .2 = 0
E L C a r r ie r S ig n a l
5
/fO
1 /fO
S C
2
S C
(= 2 5 0 m s )
E L C a r r ie r S ig n a l
(= 7 .8 m s )
EL Timing (fOSC=128kHz)
ory. The LCD display memory can be read and written to
only by indirect addressing mode using MP1. When
data is written into the display data area, it is automatically read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
on or off, a ²1² or a ²0² is written to the corresponding bit
of the display memory, respectively. The figure illustrates the mapping between the display memory and
LCD pattern for the device.
LCD Display Memory
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 4DH of
the RAM at Bank 1. Bank pointer (BP; located at 04H of
the RAM) is the switch between the RAM and the LCD
display memory. When the BP is set as ²01H², any data
written into 40H~4DH will effect the LCD display. When
the BP is cleared to ²00H², any data written into 40H~
4DH means to access the general purpose data memC O M
4 0 H
4 1 H
4 2 H
4 3 H
0 B H
0 C H
0 D H
B it
0
0
1
1
2
2
S E G M E N T
0
1
2
3
1 1
1 2
1 3
Display Memory (Bank 1)
Rev. 1.00
17
June 15, 2007
HT47C06L
LCD Driver Output
value may be set as 1.3V±0.05V by changing suitable external RLVD for the same lot. The low voltage detector circuit can be turned On or Off by writing a ²1² or a ²0² to
BON (bit 3 of ADCR register). The BLF is invalid when the
BON is cleared as ²0².
The output number of the LCD driver device can be
14´2 or 13´3 by option (i.e., 1/2 duty or 1/3 duty).
The bias type LCD driver can only be ²C² type. A capacitor mounted between C1 and C2 pins is needed. A
capacitor mounted between VCC pin and ground is required.
Set BON=0 after checking the voltage to prevent from
DC current consumption of LVD.
Low Voltage Detect - LVD
B L F
A D C R
The HT47C06L provides a low voltage detector for battery system application. If the LVD is on and the battery
voltage is lower than the specified value, the low voltage
flag (BLF; bit 4 of ADCR register) is set. The specified
b it 3
B O N
L V D
L V D
D u r in g R e s e t o r in H A L T M o d e
A D C R b it 4
C O M 0 , C O M 1
V C C *
V S S
A ll s e g m e n t o u tp u ts
V C C *
V S S
R
L V D
1 F ra m e
N o r m a l O p e r a tio n M o d e
V C
V D
V S
V C
V D
V S
V C
V D
V S
C O M 0
C O M 1
A ll s e g m e n ts O F F
D
S
C
C
D
S
C
D
S
V C C
V D D
V S S
C O M 0 s e g m e n ts O N
V C
V D
V S
V C
V D
V S
C O M 1 s e g m e n ts O N
A ll s e g m e n ts O N
D
S
S
C
D
C
LCD Driver Output (1/2 Duty, 1/2 Bias)
Note:
²VCC² is 2VDD at normal operation mode.
²VCC*² is VDD with LCD off or reset.
Rev. 1.00
18
June 15, 2007
HT47C06L
D u r in g R e s e t o r in H A L T M o d e
C O M 0 , C O M 1 , C O M 2
V C C *
V S S
A ll s e g m e n t o u tp u ts
V C C *
V S S
N o r m a l O p e r a tio n M o d e
1 F ra m e
V C C
V D D
V S S
C O M 0
V C
V D
V S
V C
V D
V S
V C
V D
V S
V C
V D
V S
C O M 1
C O M 2
A ll s e g m e n ts O F F
C O M 0 s e g m e n ts O N
D
S
C
D
S
C
D
S
S
D
C
C
V C C
V D D
V S S
C O M 1 s e g m e n ts O N
V C
V D
V S
V C
V D
V S
C O M 2 s e g m e n ts O N
C O M 0 , 1 s e g m e n ts O N
D
S
S
C
D
C
C O M 0 , 2 s e g m e n ts O N
V C C
V D D
V S S
C O M 1 , 2 s e g m e n ts O N
V C C
V D D
V S S
A ll s e g m e n ts O N
V C C
V D D
V S S
LCD Driver Output (1/3 Duty, 1/2 Bias)
Note:
²VCC² is 2VDD at normal operation mode.
²VCC*² is VDD with LCD off or reset.
Rev. 1.00
19
June 15, 2007
HT47C06L
Mask Option
The following shows many kinds of mask options in the HT47C06L. All these options should be defined in order to ensure proper system functioning.
No.
Function
1
WDT enable or disable selection.
(0=enable; 1=disable)
2
Buzzer output frequency selection.
There are four types of frequency signals for the buzzer output frequency: fSYS/22 to fSYS/25
3
To define the PA0 and PA1 output function.
0=Normal output
1=Buzzer output. PA0 is BZ output, PA1 is BZ output.
4
To define the PA2 output function.
PA2 is normal output or EL carrier output.
5
Oscillator/LCD are on or off when CPU HALT
0=Oscillator/LCD is off at HALT
1=Oscillator/LCD is on at HALT
6
PA0~PA7 pull-high option in input mode (0: enable; 1: disable)
7
LCD common selection.
There are two types of selection: 2 common (1/2 duty) or 3 common (1/3 duty).
If the 3 common is selected, the segment output pin ²SEG13² will be set as a common output.
8
LCD driver clock selection.
There are four types of frequency signals for the LCD driver circuits: fSYS/23 to fSYS/26.
Application Circuits
V C C
0 .1 m F
C O M 0 ~ 1
C O M 2 /S E G 1 3
S E G 0 ~ 1 2
P A 0 /B Z
V D D
1 .5 V
P A 1 /B Z
P A 2 /E L
P A 3
P A 4
C 1
P A 5
C 2
P A 6
0 .1 m F
O S C 1
P A 7
R
L V D
O S C
O S C 2
V S S
R E S
R C IN
2 2 0 0 p F
L C D
P a n e l
R R E F
1 0 0 k W
V D D
R S E N
0 .1 m F
0 .1 m F
S e n s o r
1 0 m F
V S S
H T 4 7 C 0 6 L
Rev. 1.00
20
June 15, 2007
HT47C06L
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
21
June 15, 2007
HT47C06L
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
22
June 15, 2007
HT47C06L
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
23
June 15, 2007
HT47C06L
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
24
June 15, 2007
HT47C06L
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
25
June 15, 2007
HT47C06L
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
26
June 15, 2007
HT47C06L
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
27
June 15, 2007
HT47C06L
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
28
June 15, 2007
HT47C06L
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
June 15, 2007
HT47C06L
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
30
June 15, 2007
HT47C06L
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
June 15, 2007
HT47C06L
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
June 15, 2007
HT47C06L
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
June 15, 2007
HT47C06L
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
June 15, 2007
HT47C06L
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
35
June 15, 2007
HT47C06L
Package Information
44-pin QFP (10´10) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Rev. 1.00
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13
¾
13.40
B
9.90
¾
10.10
C
13
¾
13.40
D
9.90
¾
10.10
E
¾
0.80
¾
F
¾
0.30
¾
G
1.90
¾
2.20
H
¾
¾
2.70
I
¾
0.10
¾
J
0.73
¾
0.93
K
0.10
¾
0.20
a
0°
¾
7°
36
June 15, 2007
HT47C06L
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
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Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
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709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
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46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
37
June 15, 2007