HOLTEK HT49RA0-6

HT49RA0-6
Remote Type 8-Bit MCU with LCD
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· Independent Carrier output pin (REM/REMDRV)
fSYS = 4MHz at VDD = 2.0V~3.6V (LVR enabled)
· Integrated IR driver (560mA at 3.0V)
· Oscillator types:
- External High Frequency crystal -- HXT
- Internal High Frequency RC -- HIRC
- External 32768Hz crystal -- LXT
- Internal 32kHz RC -- LIRC
· LCD driver with 21´2, 21´3 or 20´4 segments
· Fully integrated internal 4095kHz oscillator requires
· Software enable control for LCD and RTC function
· LCD display duty and bias
· Duty: 1/2, 1/3 or 1/4
· Bias: 1/2 or 1/3
no external components
· Watchdog Timer
· Program Memory: 2K´16
· Low Voltage Reset/Detect function
· Data Memory: 96´8
· Power-down and wake-up features reduce power
consumption
· 4 subroutine nesting levels
· Up to 23 bidirectional I/O lines
· 16-bit table read instruction
· Two external interrupt lines shared with I/O pins
· Bit manipulation instruction
· One 8-bit programmable timer/event counter
· 63 powerful instructions
· Real Time Clock -- RTC
· Up to 1ms instruction cycle with 4MHz system clock
· 8-bit prescaler for RTC
· All instructions in 1 or 2 machine cycles
· One programmable carrier output -- using 9-bit
· 48-pin LQFP package
timer
General Description
The HT49RA0-6 is 8-bit high performance, RISC
architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The advantages of low power consumption, I/O
flexibility, timer functions, oscillator options, watchdog
timer, power-down and wake-up functions, as well as
Rev. 1.10
low cost, enhance the versatility of this device to suit a
wide range of application possibilities such as industrial
control, consumer products, and particularly suitable for
use in products such as infrared LCD remote controllers
and various subsystem controllers.
1
February 18, 2013
HT49RA0-6
Block Diagram
O T P
P ro g ra m
M e m o ry
D a ta
M e m o ry
In te rru p t
C o n tr o lle r
W a tc h d o g
T im e r
S ta c k
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
I/O
P o rts
9 - b it
T im e r
E x te rn a l X T A L
O s c illa to r s
In te rn a l R C
O s c illa to r s
R E M
O u tp u t
L o w V o lta g e
R e s e t
L C D
C o n tr o lle r
Pin Assignment
P C 6
P C 5
P C 4
P C 3
P C 2
P C 1
P B 5
P B 6
/S
/S
/S
/S
/S
/S
/O
/O
E G 6
E G 5
E G 4
E G 3
E G 2
E G 1
S C 2
S C 1
P A 0
P A 1
P A 2
P A 3
P B 0
P B 1
P B 2
P B
P B
P A 4
P A 5
P A 6
P A 7
/IN T 0
/IN T 1
/T M R
V D D
V S S
3 /X T 1
4 /X T 2
P B 7
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
2
3 6
3 5
3
3 4
4
3 3
5
3 2
6
H T 4 9 R A 0 -6
4 8 L Q F P -A
7
8
3 1
3 0
2 9
9
2 8
1 0
2 7
1 1
2 6
1 2
2 5
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
P C 7
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
/S
8
9
1
1
1
1
1
1
1
1
1
E G 7
0
1
2
3
4
5
6
7
8
S E G 1 9
S E G 2 0
C O M 3 /S E G 2 1
C O M 2
C O M 1
C O M 0
C 2
C 1
V C
V A
V S S 1
R E M /R E M D R V
Rev. 1.10
2
February 18, 2013
HT49RA0-6
Pin Description
Pin Name
PA0~PA7
Function
OPT
I/T
O/T
Description
PAn
CO
ST
NMOS
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB0
CO
ST
NMOS
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
INT0
CO
ST
¾
PB1
CO
ST
NMOS
INT1
CO
ST
¾
PB2
CO
ST
NMOS
TMR
TMRC
ST
¾
PB3
CO
ST
NMOS
XT1
CO
LXT
¾
PB4
CO
ST
NMOS
XT2
CO
¾
LXT
PB5
CO
ST
NMOS
OSC2
CO
¾
HXT
PB6
CO
ST
NMOS
OSC1
CO
HXT
¾
PB7
CO
ST
NMOS
PB0/INT0
External interrupt 0 input
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB1/INT1
External interrupt 1 input
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB2/TMR
External Timer clock input
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB3/XT1
Oscillator pin
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB4/XT2
Oscillator pin
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB5/OSC2
Oscillator pin
General purpose I/O with pull-up resistor. Configuration
option enabled wake-up.
PB6/OSC1
PB7
Oscillator pin
General purpose I/O without pull-up resistor. Configuration option enabled wake-up.
PC1/SEG1~
PC7/SEG7
PCn
¾
ST
NMOS General purpose I/O with pull-up resistor.
SEGn
SEGCR
¾
CMOS LCD segment output
SEG8~SEG20
SEGn
LCDC
¾
CMOS LCD segment output
COM3
CO
¾
CMOS LCD common output
SEG21
CO
¾
CMOS LCD segment output
COM0~COM2
COMn
LCDC
¾
CMOS LCD common output
VA, VC, C1, C2
Vn, Cn
LCDC
¾
CMOS LCD voltage pump
REM
TSR1
¾
CMOS Carrier output
REMDRV
TSR1
¾
NMOS High sink carrier output
COM3/SEG21
REM/REMDRV
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
VSS1
VSS
¾
PWR
¾
Ground, of REM/REMDRV
Note:
I/T: Input type; O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output; NMOS: NMOS output
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
Rev. 1.10
3
February 18, 2013
HT49RA0-6
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+4.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-20°C to 70°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
Conditions
VDD
Operating Voltage
¾
LVR enable
2.0
¾
3.6
V
IDD
Operating Current
(RC OSC)
3V
No load, fSYS=4MHz
¾
0.7
1.5
mA
ISTB1
Standby Current
(*fS=T1=fSYS)
3V
No load, system HALT,
LCD off at HALT
¾
0.1
1.0
mA
ISTB2
Standby Current
(*fS=32.768kHz,QOSC=1)
3V
No load, system HALT,
LCD On at HALT, C type
¾
2.5
5.0
mA
ISTB3
Standby Current
(*fS=WDT RC OSC)
3V
No load, system HALT
LCD On at HALT, C type
¾
2.0
5.0
mA
VIL1
Input Low Voltage for I/O Ports,
TMR, INT0 and INT1
3V
¾
0
¾
0.2VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR, INT0 and INT1
3V
¾
0.8VDD
¾
VDD
V
IOL1
PA0~PA7, PB0~PB6, PC1~PC7,
REM sink current
3V
VOL=0.1VDD
6
12
¾
mA
IOH1
REM Source Current
3V
VOH=0.9VDD
-5
-7
¾
mA
IOL2
LCD Common and Segment
Current
3V
VOL=0.1VDD
210
420
¾
mA
IOH2
LCD Common and Segment
Current
3V
VOH=0.9VDD
-80
-160
¾
mA
IOL3
PB7 Sink Current
3V
VOL=0.1VDD
0.8
1.2
¾
mA
IOL4
REMDRV Sink Current
3V
VOL=0.6V, Ta=25°C
500
560
¾
mA
RPH
Pull-high Resistance of I/O Ports
3V
100
150
200
kW
VLVR
Low Voltage Reset Voltage
¾
Ta=25°C
1.8
1.9
2.0
V
VLVD
Low Voltage Detector Voltage
¾
Ta=25°C
2.0
2.1
2.2
V
Note:
¾
²*² for the value of VA refer to the LCD driver section.
²*fS² please refer to WDT clock option
Rev. 1.10
4
February 18, 2013
HT49RA0-6
A.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock
1.8V~
Ta= -20°C~70°C
3.6V
400
¾
4000
kHz
fHIRC
System Clock (HIRC)
2.2V~
Ta= -10°C~50°C
3.6V
-1%
4095
+1%
kHz
fLXT
LXT oscillator frequency
¾
¾
32768
¾
Hz
fLIRC
Cystem Clock (LIRC)
3V
-10%
32
+10%
kHz
fTIMER
Timer I/P frequency (TMR)
3V
0
¾
4000
kHz
Power-up or Wake-up
from HALT (HXT)
¾
128
¾
*tSYS
Power-up from HALT
(HIRC)
¾
128
¾
*tSYS
Wake-up from HALT
(HIRC)
¾
2
¾
*tSYS
tSST
System Start-up Timer Period
¾
¾
Ta=25°C
¾
tINT
Interrupt pulse width
¾
¾
1
¾
¾
ms
tLVR
Low voltage width to reset
¾
¾
0.25
1.00
2.00
ms
fREADYB
REMDRV output function stable
time; polling READYB register
bit=0
¾
Wake-up from HALT or
change REMDRV
register bit from 1 to 0
¾
250
¾
ms
Min.
Typ.
Max.
Unit
Note:
*tSYS=1/fSYS
Power-on Reset Characteristics
Symbol
Test Conditions
Parameter
VDD
Conditions
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Rev. 1.10
5
February 18, 2013
HT49RA0-6
Characteristics Curves
HIRC Oscillator Voltage/Temperature vs. Frequency
H IR C C u r v e
4 2 0 0
4 1 5 0
4 0 9 5 k H z + 1 %
F re q u e n c y (k H z )
-2 5 ° C
2 5 ° C
4 1 0 0
7 5 ° C
4 0 5 0
4 0 9 5 k H z - 1 %
4 0 0 0
2 .0
2 .5
3 .0
3 .6
V D D (V )
IR Sink Current vs. VDD
IR
D r iv e r C u r v e T a = 2 5 ° C
°
8 0 0
7 0 0
5 0 0
4 0 0
3 0 0
R E M
S in k C u r r e n t (m A )
6 0 0
2 0 0
1 0 0
0
1 .8
2 .0
2 .2
2 .4
2 .6
2 .8
V D D
Rev. 1.10
6
3 .0
3 .2
3 .4
3 .6
3 .8
(V )
February 18, 2013
HT49RA0-6
Functional Description
Execution Flow
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
specify a maximum of 2048 addresses.
The main system clock is derived from either an external
crystal oscillator which requires the connection of the
external crystal or resonator or an internal RC oscillator
which requires no external component for its operation.
It is internally divided into four non-overlapping clocks.
One instruction cycle consists of four system clock cycles.
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by
one. The PC then points to the memory word containing
the next instruction code.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction.
Program Counter - PC
The program counter (PC) is 11 bits wide and controls
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
In s tr u c tio n C y c le
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter overflow
0
0
0
0
0
0
0
1
1
0
0
Time Base Interrupt
0
0
0
0
0
0
1
0
0
0
0
RTC Interrupt
0
0
0
0
0
0
1
0
1
0
0
Skip
Program Counter + 2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*10~*0: Program counter bits
#10~#0: Instruction code bits
Rev. 1.10
S10~S0: Stack register bits
@7~@0: PCL bits
7
February 18, 2013
HT49RA0-6
· Location 014H
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional
dummy cycle is required.
Location 014H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 014H.
· Table location
Program Memory - ROM
Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, 1
page=256 words) and TABRDL [m] (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH, and the remaining 2 bit is read as ²0². The
TBLH is read only, and the table pointer (TBLP) is a
read/write register (07H), indicating the table location.
Before accessing the table, the location should be
placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas
may function as a normal ROM depending upon the
user¢s requirements.
The program memory (ROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 2048 ´ 16 bits which are addressed by the program
counter and table pointer.
Certain locations in the ROM are reserved for special
usage:
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
· Location 008H
E x te r n a l In te r r u p t 0 S u b r o u tin e
0 0 8 H
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program begins execution at location 008H.
0 0 C H
E x te r n a l In te r r u p t 1 S u b r o u tin e
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 1 0 H
T im e B a s e In te r r u p t
0 1 4 H
R T C
P ro g ra m
R O M
In te rru p t
· Location 00CH
Location 00CH is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
1 0 0 H
1 F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
7 0 0 H
7 F F H
· Location 010H
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 6 b its
N o te : n ra n g e s fro m
Location 010H is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 010H.
0 to 6
Program Memory
Table Location
Instruction(s)
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.10
P10~P8: Current program Counter bits
8
February 18, 2013
HT49RA0-6
B a n k 0
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 4 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At a
commencement of a subroutine call or an interrupt acknowledgment, the contents of the program counter is
pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or
RETI), the contents of the program counter is restored
to its previous value from the stack. After chip reset, the
SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent 4 return addresses are stored).
P ro g ra m
T o p o f S ta c k
B o tto m
S ta c k L e v e l 3
o f S ta c k
3 F H
4 0 H
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
C o u n te r
5 5 H
5 6 H
P ro g ra m
M e m o ry
B a n k 1
IA R 0
M P 0
IA R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
IN T C 0
C T R L
T M R
T M R C
W D T C
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
P A
P B
P C
S E G C R
T S R 0
T S R 1
C A R L 0
C A R L 1
C A R H 0
C A R H 1
IN T C 1
L C D C
G e
P u
D
M e
(9 6
n
rp
a
m
B
e ra
o s
ta
o r
y te
y
e
l
L C D
R A M
s )
7 F H
S ta c k L e v e l 4
:u n im p le m e n te d , r e a d a s " 0 "
Data Memory - RAM
RAM Mapping
The data memory is divided into two functional groups:
special function registers and general purpose data
memory (96´8). Most of them are read/write, but some
are read only. The unused space before 20H is reserved
for future expanded usage and reading these locations
will return the result 00H. The general purpose data
memory, addressed from 20H to 7FH, is used for data
and control information under instruction command. The
areas in the RAM can directly handle arithmetic, logic,
increment, decrement, and rotate operations. Except
some dedicated bits, each bit in the RAM can be set and
reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through the Memory pointer register 0
(MP0; 01H) or the Memory pointer register 1 (MP1;
03H).
function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in
the same way as normal registers providing a convenient way with which to address and track data. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to, is the address specified by
the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data
from Bank 0, while MP1 and IAR1 are used to access
data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks
must be addressed indirectly using MP1 and IAR1.
Indirect Addressing Register - IAR0, IAR1
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation. The
Rev. 1.10
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HT49RA0-6
Bank Pointer - BP
Arithmetic and Logic Unit - ALU
Depending upon which device is used, the Program and
Data Memory are divided into several banks. Selecting
the required Program and Data Memory area is
achieved using the Bank Pointer. Bit 0 of the Bank
Pointer is used to select Data Memory Banks 0~1. The
Data Memory is initialised to Bank 0 after a reset, except
for a WDT time-out reset in the Power-down Mode, in
which case, the Data Memory bank remains unaffected.
It should be noted that the Special Function Data Memory is not affected by the bank selection, which means
that the Special Function Registers can be accessed
from within any bank. Directly addressing the Data
Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing
data from banks other than Bank 0 must be implemented using Indirect addressing mode. As both the
Program Memory and Data Memory share the same
Bank Pointer Register, care must be taken during programming.
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is of 8 bits wide and contains,
a carry flag (C), an auxiliary carry flag (AC), a zero flag
(Z), an overflow flag (OV), a power down flag (PDF), and
a watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those intended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the
latest operations.
Accumulator - ACC
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Bit No.
Label
0
BP0
1~7
¾
Function
BP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Unused bit, read as ²0²
BP Register
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
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February 18, 2013
HT49RA0-6
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
Interrupts
The devices provides two external interrupts, one internal timer/event counter interrupts, an internal time base
interrupt, and an internal real time clock interrupt. The
interrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
External interrupts are triggered by a high to low or low
to high or both transition of INT0 or INT1, and the related
interrupt request flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of
INTC0) is set as well. After the interrupt is enabled, the
stack is not full, and the external interrupt is active, a
subroutine call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all
cleared to disable other interrupts.
Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack should be prevented
from becoming full.
The internal Timer/Event Counter interrupt is initialized by
setting the Timer/Event Counter interrupt request flag
(TF;bit 6 of INTC0), which is normally caused by a timer
overflow. After the interrupt is enabled, and the stack is
not full, and the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag (TF) is reset, and the EMI bit is cleared to disable further interrupts.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF;bit 4 of INTC1), that is
caused by a regular time base signal. After the interrupt
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enabled; 0=disabled)
1
EEI0
Controls the external interrupt 0 (1=enabled; 0=disabled)
2
EEI1
Controls the external interrupt 1 (1=enabled; 0=disabled)
3
ETI
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
4
EIF0
External interrupt 0 request flag (1=active; 0=inactive)
5
EIF1
External interrupt 1 request flag (1=active; 0=inactive)
6
TF
Internal Timer/Event Counter request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
ETBI
Controls the time base interrupt (1=enabled; 0:disabled)
1
ERTI
Controls the real time clock interrupt (1=enabled; 0:disabled)
2, 3
¾
Unused bit, read as ²0²
4
TBF
Time base request flag (1=active; 0=inactive)
5
RTF
Real time clock request flag (1=active; 0=inactive)
6, 7
¾
Unused bit, read as ²0²
INTC1 (1EH) Register
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February 18, 2013
HT49RA0-6
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 10H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further interrupts.
Oscillator Configuration
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 5 of
INTC1), that is caused by a regular real time clock signal.
After the interrupt is enabled, and the stack is not full, and
the RTF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (RTF) is reset and
the EMI bit is cleared to disable further interrupts.
In addition to the main system clock oscillators, there is
an external 32768Hz crystal (LXT) oscillator to provide
the clock sources for Real Time and Time Base Interrupts and LCD display.
In this device there are two methods of generating the
system clock, one external crystal oscillator and one internal RC oscillator.
· External Crystal/Resonator Oscillator - HXT
The External Crystal/Ceramic System Oscillator is
one of the system oscillator choices, which is selected
via a configuration option. For the crystal oscillator
configuration, the connection of a crystal across
OSC1 and OSC2 will create the necessary phase shift
and feedback for oscillation. Two external capacitors
may be required to be connected as shown. However,
the feedback resistor named Rf shown in the following
diagram for the crystal oscillator to oscillate properly
can be selected as either an internally or externally
connected type via a configuration option. When the
external connection type of the feedback resistor is
selected, the recommended value of the external connected feedback resistor ranges from 300kW to
500kW. Using a ceramic resonator will usually require
two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of
C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer¢s specification.
During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set both to 1 (if the stack is not
full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI sets the EMI bit and enables an interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External interrupt 0
1
04H
External interrupt 1
2
08H
Timer/Event Counter overflow
3
0CH
Time base interrupt
4
10H
Real time clock interrupt
5
14H
Crystal Oscillator C1 and C2 Values
C1
C2
4MHz
8pF
10pF
Note:
C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
The EMI, EEI0, EEI1, ETI, ETBI and ERTI are all used to
control the enable/disable status of interrupts. These
bits prevent the requested interrupt from being serviced.
Once the interrupt request flags (RTF, TBF, TF, EIF1,
EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by
a software instruction.
C 1
O S C 1
R f
R p
It is recommended that a program not use the ²CALL
subroutine² within the interrupt subroutine. It¢s because
interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications.
At this time, if only one stack is left, and enabling the interrupt is not well controlled, operation of the ²call² in the
interrupt subroutine may damage the original control sequence.
Rev. 1.10
Crystal Frequency
C 2
O S C 2
In te r n a l
O s c illa to r
C ir c u it
T o in te r n a l
c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT
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HT49RA0-6
· Internal RC Oscillator - HIRC
LXT Oscillator C1 and C2 Values
The internal RC oscillator is a fully integrated system
oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 4095kHz.
Device trimming during the manufacturing process
and the inclusion of internal frequency compensation
circuits are used to ensure that the influence of the
power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a
result, at a power supply ranging from 1.8V to 3.6V
and in a temperature range from -20°C to 50°C degrees, the fixed oscillation frequency of 4095kHz will
have a tolerance within 2%. Note that if this internal
system clock option is selected, as it requires no external pins for its operation, I/O pins PB5 and PB6 are
free for use as normal I/O pins.
Crystal Frequency
32.768kHz
Note:
R p
X T 2
LXT Mode
0
Quick Start
1
Low-power
It should be noted that, no matter what condition the
QOSC bit is set to, the LXT oscillator will always function
normally and the only difference is that it will take more
time to start up if in the Low-power mode.
Internal Low Speed Oscillator - LIRC
The LIRC is a fully self-contained on-chip RC oscillator
with a typical frequency of 32kHz at 3V requiring no external components. Device trimming during the manufacturing process and the inclusion of internal frequency
compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are
minimised. When the device enters the Power-Down
Mode, the system clock will stop running but the LIRC
oscillator continues to run and to keep the watchdog active if the WDT function is enabled. However, to preserve power in certain applications the LIRC can be
disabled via a configuration option together with software register control bits.
In te rn a l
O s c illa to r
C ir c u it
3 2 .7 6 8
k H z
C 2
QOSC Bit
After power-on the QOSC bit will be automatically
cleared to zero ensuring that the LXT oscillator is in the
Quick Start operating mode. In the Quick Start Mode the
LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can
be placed into the Low-power mode by setting the
QOSC bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current
consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery
applications, where power consumption must be kept to
a minimum, it is therefore recommended that the application program sets the QOSC bit high about 2 seconds
after power-on.
If the LXT oscillator is used for any clock source, the
32.768 kHz crystal should be connected to the
XT1/XT2 pins.
X T 1
10pF
The LXT oscillator can function in one of two modes, the
Quick Start Mode and the Low Power Mode. The mode
selection is executed using the QOSC bit in the RTCC
register.
If the LXT oscillator is not used for any clock source,
the XT1/XT2 pins should be left as floating states.
C 1
10pF
1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
LXT Oscillator Low Power Function
The External 32.768kHz Crystal Oscillator is one of
the oscillator choices for WDT function, Real Time and
Time Base interrupts and LCD display, which is selected via configuration options. This clock source has
a fixed frequency of 32.768 kHz and requires a 32.768
kHz crystal to be connected between pins XT1 and
XT2. The external resistor and capacitor components
connected to the 32.768kHz crystal are necessary to
provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to
different crystal manufacturing tolerances. During
power-up there is a time delay associated with the
LXT oscillator waiting for it to start-up.
However, for some crystals, to ensure oscillation and
accurate frequency generation, it is necessary to add
two small value external capacitors, C1 and C2. The
exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer¢s
specification. The external parallel feedback resistor,
RP, is required.
Some configuration options determine if the XT1/XT2
pins are used for the LXT oscillator or as I/O pins.
¨
C2
32.768kHz Crystal Recommended Capacitor Values
· External 32.768kHz Crystal Oscillator - LXT
¨
C1
T o in te r n a l
c ir c u its
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n p in s h a v e a
p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External Oscillator - LXT
Rev. 1.10
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February 18, 2013
HT49RA0-6
riod can vary with VDD, temperature and process variations. The Watchdog Timer source clock is then
subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the
WS2~WS0 bits in the WDTC register.
Watchdog Timer - WDT
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise.
· Watchdog Timer control register
· Watchdog Timer clock source
A single register, WDTC, controls the required timeout
period as well as the enable/disable operation. This
register together with the corresponding configuration
option control the overall operation of the Watchdog
Timer.
The Watchdog Timer clock source is provided by the
internal clock which is supplied by the LIRC oscillator.
The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock pe-
¨
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3
WE4~WE0: WDT function software control
10101: Disabled
01010: Enabled
other: Reset MCU
When these bits are changed by the environmental noise to reset the microcontroller, the reset
operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will
be set to 1.
Bit 2~0
WS2~WS0: WDT Time-out period selection
000: 28/fLIRC
001: 210/fLIRC
010: 212/fLIRC
011: 214/fLIRC
100: 215/fLIRC
101: 216/fLIRC
110: 217/fLIRC
111: 218/fLIRC
¨
CTRL Register
Bit
7
6
5
4
3
2
1
0
¾
¾
WRF
¾
¾
R/W
¾
0
Name
¾
¾
¾
¾
¾
R/W
¾
¾
¾
¾
¾
POR
¾
¾
¾
¾
¾
¾
Bit 7~1
Unimplemented, read as 0
Bit 0
WRF: WDT Control register software reset flag
0: not occur
1: occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the application
program. Note that this bit can only be cleared to 0 by the application program.
Rev. 1.10
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February 18, 2013
HT49RA0-6
· Watchdog Timer Operation
WDT
Configuration Option
The Watchdog Timer operates by providing a device
reset when its timer overflows. This means that in the
application program and during normal operation the
user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from
executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters
an endless loop, these clear instructions will not be
executed in the correct manner, in which case the
Watchdog Timer will overflow and reset the device.
Some of the Watchdog Timer options, such as always
on select and clear instruction type are selected using
configuration options. With regard to the Watchdog
Timer enable/disable function, there are also five bits,
WE4~WE0, in the WDTC register to offer additional
enable/disable and reset control of the Watchdog
Timer. If the WDT configuration option is determined
that the WDT function is always enabled, the
WE4~WE0 bits still have effects on the WDT function.
When the WE4~WE0 bits value is equal to 01010B or
10101B, the WDT function is enabled. However, if the
WE4~WE0 bits are changed to any other values except 01010B and 10101B, which is caused by the environmental noise, it will reset the microcontroller after
2~3 LIRC clock cycles. If the WDT configuration option is determined that the WDT function is controlled
by the WDT control register, the WE4~WE0 values
can determine which mode the WDT operates in. The
WDT function will be disabled when the WE4~WE0
bits are set to a value of 10101B. The WDT function
will be enabled if the WE4~WE0 bits value is equal to
01010B. If the WE4~WE0 bits are set to any other values by the environmental noise, except 01010B and
10101B, it will reset the device after 2~3 LIRC clock
cycles. After power on these bits will have the value of
01010B.
W E 4 ~ W E 0 B its
Always Enable
Controlled by WDT
Control Register
WE4 ~ WE0
Bits
WDT
Function
01010B or
10101B
Enable
Any other
value
Reset MCU
10101B
Disable
01010B
Enable
Any other
value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Power Down Mode,
when a Watchdog Timer time-out occurs, the TO bit in
the status register will be set and only the Program
Counter and Stack Pointer will be reset. Three methods
can be adopted to clear the contents of the Watchdog
Timer. The first is a WDT reset, which means a certain
value except 01010B and 10101B written into the
WE4~WE0 bit filed, the second is using the Watchdog
Timer software clear instructions and the third is via a
HALT instruction.
There is only one method of using software instruction
to clear the Watchdog Timer. That is to use the single
²CLR WDT² instruction to clear the WDT.
The maximum time out period is when the 218 division
ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum
watchdog period of around 8 second for the 218 division
ratio, and a minimum timeout of 7.8ms for the 28 division
ration.
R e s e t M C U
W D T C R e g is te r
C L R
" C L R W D T " In s tr u c tio n
L IR C
fL
IR C
fL
8 - s ta g e D iv id e r
W S 2 ~ W S 0
( f L IR C / 2 8 ~ f L
/2
IR C
IR C
/2
8
W D T P r e s c a le r
1 8
)
W D T T im e - o u t
2 8 / f L IR C ~ 2 1 8 / f L IR
C
8 -to -1 M U X
Watchdog Timer
Rev. 1.10
15
February 18, 2013
HT49RA0-6
Time Base
Power Down Operation - HALT
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from fS/212 to fS/215 selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 4 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 10H occurs.
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
fS
· The system oscillator turns off but the LIRC OSC
keeps running (if WDT is enabled or the LIRC oscillator or real time clock is selected).
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and start recounting (if WDT is
P r e s c a le r
D iv id e r
enabled).
· All I/O ports maintain their original status.
O p tio n
L C D
D r iv e r ( fS /2
B u z z e r (fS /2
2
2
~ fS /2
~ fS /2
· The PDF flag is set but the TO flag is cleared.
O p tio n
9
8
)
T im e B a s e In te r r u p t
(fS /2
)
The system quits the HALT mode by an interrupt, an external falling edge signal on port B, or a WDT overflow.
The WDT overflow performs a ²warm reset². After examining the TO and PDF flags, the reason for chip reset can
be determined. The PDF flag is cleared by system
power-up or by executing the ²CLR WDT² instruction,
and is set by executing the ²HALT² instruction. On the
other hand, the TO flag is set if WDT time-out occurs, and
causes a wake-up that only resets the program counter
and Stack Pointer, and leaves the others at their original
state.
1 2
~ fS /2
1 5
)
Time Base
Real Time Clock - RTC
The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming . Writing data to RT2,
RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 5 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs. The real time clock
time-out signal also can be applied to be a clock source of
Timer/Event Counter for getting a longer time-out period.
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
28*
0
0
1
29*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
15
1
1
2
The port A and port B wake-up and interrupt methods
can be considered as a continuation of normal execution. Each bit in port A and port B can be independently
selected to wake-up the device by option. Awakening
from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequences may occur. If the
related interrupt is disabled or the interrupt is enabled
but the stack is full, the program resumes execution at
the next instruction. But if the interrupt is enabled, and
the stack is not full, the regular interrupt response takes
place.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awaken using that
interrupt.
If wake-up events occur, it takes a certain period known
as the tSST period to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the Wake-up results in
the next instruction execution, the execution will be performed immediately after the dummy period is finished.
Note: ²*² not recommended to be used
fS
D iv id e r
R T 2
R T 1
R T 0
P r e s c a le r
8 to 1
M u x .
8
1 5
fS /2 ~ fS /2
R T C In te rru p t
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Real Time Clock
Rev. 1.10
When at HALT state and fS=fSYS/4, the LCD and RTC
will be turned off no matter the bit value of (LCDEN,
RTCEN).
16
February 18, 2013
HT49RA0-6
Reset
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the HALT state. Awaking from the
HALT state, the SST delay is added.
There are three ways in which reset may occur.
· Power-on reset
· LVR is reset during normal operation
· WDT time-out is reset during normal operation
An extra SST delay is added during the power-up period
and any wakeup from the HALT may enable only the
SST delay.
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and stack pointer and
leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition²
once the reset conditions are met. Examining the PDF
and TO flags, the program can distinguish between different ²chip resets².
The functional unit chip reset status is shown below.
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC,
Time base
Cleared. After master reset,
WDT starts counting
TO
PDF
0
0
Power-on reset
Input/output ports
Input mode
u
u
LVR reset during normal operation
Stack Pointer
Points to the top of the stack
1
u
WDT time-out during normal operation
Carrier Output
Floating state
1
1
WDT Wake-up HALT
SEG/COM outputs
High state
Note:
Timer/Event Counter Off
²u² means unchanged
V D D
C h ip
RESET Conditions
Program Counter
tR
S T D +
tS
H A L T
S T
W a rm
W D T
R e s e t
Reset Timing Chart
C o ld
R e s e t
L V R
O S C 1
R e s e t
W D T
T im e - o u t
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
P o w e r - o n D e te c tio n
Reset Configuration
Rev. 1.10
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February 18, 2013
HT49RA0-6
The chip reset register status is summarised in the following table:
Reset
(Power-on)
WDT Time-out Reset
(Normal Operation)
LVR Reset
(Normal Operation)
WDT Time-out
(HALT)*
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
---- ---0
---- ---0
---- ---0
---- ---u
Register
BP
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RTCC
--00 0111
--00 0111
--00 0111
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
CTRL
---- ---0
---- ---0
---- ---0
---- ---u
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
0000 1---
0000 1---
0000 1---
uuuu u---
WDTC
0101 0011
0101 0011
0101 0011
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 111x
1111 111x
1111 111x
uuuu uuuu
SEGCR
0000 000x
0000 000x
0000 000x
uuuu uuuu
TSR0
0000 0000
0000 0000
0000 0000
uuuu uuuu
TSR1
100- --00
100- --00
100- --00
uuu- --uu
CARL0
0000 0000
0000 0000
0000 0000
uuuu uuuu
CARL1
0000 0000
0000 0000
0000 0000
uuuu uuuu
CARH0
0000 0000
0000 0000
0000 0000
uuuu uuuu
CARH1
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC1
--00 --00
--00 --00
--00 --00
--uu --uu
LCDC
---- --11
---- --11
---- --11
---- --uu
Note:
²*² refers to warm reset
²u² means unchanged
²x² means unknown
²-² means unimplemented
Rev. 1.10
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HT49RA0-6
Timer/Event Counter
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
One timer/event counters are implemented in the devices.
It contains an 8-bit programmable count-up counter.
In the event count or timer mode, the timer/event counter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag (TF;bit 6 of INTC0).
The timer/event counter clock source may come from
the system clock or system clock/4 or RTC time-out signal or external source. System clock source or system
clock/4 is selected by option.
Using external clock input allows the user to count external events, measure time internals or pulse widths, or
generate an accurate time base. While using the internal clock allows the user to generate an accurate time
base.
In the pulse width measurement mode with the values of the TON and TE bit equal to one, after the TMR
has received a transient from low to high (or high to
low if the TE bit is ²0²), it will start counting until the
TMR returns to the original level and resets the TON.
The measured result remains in the timer/event
counter even if the activated transient occurs again.
In other words, only one cycle measurement can be
made until the TON is set. The cycle measurement will
re-function as long as it receives further transient pulse.
In this operation mode, the timer/event counter begins
counting according not to the logic level but to the transient edges. In the case of counter overflows, the counter
is reloaded from the timer/event counter preload register
and issues an interrupt request, as in the other two
modes, i.e., event and timer modes.
There are two registers related to the timer/event counter, i.e., TMR (0DH) and TMRC (0EH). There are also
two physical registers are mapped to TMR location; writing TMR places the starting value in the timer/event
counter preload register, while reading it yields the contents of the timer/event counter. TMRC is timer/event
counter control register used to define some options.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
Function
3
TE
To define the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
5
TS
6
7
TM0
TM1
To enable/disable timer counting
(0=disabled; 1=enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
To define the operating mode (TM1, TM0)
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMRC (0EH) Register
S y s te m
S y s te m
C lo c k
C lo c k /4
O p tio n
S e le c t
M
U
X
D a ta B u s
R T C O u t
T M 1
T M 0
T S
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
T o In te rru p t
Timer/Event Counter
Rev. 1.10
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February 18, 2013
HT49RA0-6
To enable the counting operation, the Timer ON bit
(TON: bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI disables the related interrupt service.
timer/event counter for proper operation. Because the
initial value of TMR is unknown.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
Carrier Generator
Due to the timer/event scheme, the programmer should
pay special attention on the instruction to enable then
disable the timer for the first time, whenever there is a
need to use the timer/event function, to avoid
unpredicatable result. After this procedure, the
timer/event function can be operated normally.
The device provides a carrier generator of which the signal appears on the REM/REMDRV pin. The carrier output is generated by a 9-bit down-count counter enabled
by a control bit together with a carrier signal generator.
· Timer Configuration
This timer is an internal unit for creating a remote control transmission pattern. As shown, it consists of a
9-bit down-count counter (T8 to T0), a flag (T9) permitting the 1-bit timer output and a zero detector.
There are two registers related to this timer known as
TSR0 and TSR1 registers.
When the timer/event counter (reading TMR) is read,
the clock is blocked to avoid errors. As this may results
in a counting error, blocking of the clock should be taken
into account by the programmer.
It is strongly recommended to load a desired value into
the TMR register first, then turn on the related
Bit No.
Label
0~7
T7~T0
Function
Timer bit 7~0
TSR0 Register
Bit No.
Label
Function
0
T8
Timer bit 8
1
T9
T9: Timer enable control
0: Disable
1: Enable
2~4
¾
Unused bit, read as ²0²
READYB: REMDRV output driver ready flag
0: REMDRV driver is ready for carrier output
1: REMDRV driver is not ready for carrier output
This bit is used to indicate that whether the REMDRV output driver gets ready to deliver the
carrier signal or not. When the REMDRV function is first enabled, including a wake-up from
HALT instruction or an output function switch from REM to REMDRV mode, a certain period
delay is necessary for the output driver to become stable before the REMDRV carrier signal
is sent on the REMDRV pin. Users should make sure that the REMDRV output driver is
ready by polling the READYB bit before the Timer is enabled. Note that in REM output function the READYB bit is not available and is always read as 0.
5
READYB
6
REM/REMDRV output function selection
REMDRV 0: REMDRV
1: REM
7
TOEF
Timer Operation End Flag
0: Timer operation is in progress
1: Timer operation is ended
TSR1 Register
Rev. 1.10
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February 18, 2013
HT49RA0-6
T S R 1
t9
t8
T S R 0
t7
t6
t5
t4
t3
t2
t1
t0
D o w n C o u n te r, (T 8 ~ T 0 )+ 1
fS
Y S
/6 4
T 9
T O E F
R E M D R V
R E M /R E M D R V
C o u n t
C lo c k
Z e ro D e te c to r
O u tp u t C o n tro l
C ir c u it
Timer Configuration
· Timer Operation
The timer starts counting down when a value other than ²0² is set for the down counter with a timer manipulation instruction. The timer manipulation instructions for making the timer start operation are shown below:
MOV A,XXH
; Load T7~T0 into TSR0; XX = 00H ~ FFH
MOV TSR0,A
MOV A,01H
; Load T8 into TSR1 and operate in REMDRV output mode
MOV
LOOP: SZ
JMP
SET
TSR1,A
READYB
LOOP
; recommended to add the code to the program when a wake-up from HALT,
; or an output function switch from REM to REMDRV mode
TSR1.1
; after READYB=0, set T9 to 1 to enable the carrier timer
· Additional notes for the 9-bit timer
¨
Writing to the TSR0 register will only put the written
data to the TSR0 register (T7~T0) while writing to
the TSR1 register (T8) will transfer the specified
data together with the TSR0 register contents to the
9-bit Down Counter. The TOEF bit will be cleared
after the data transferred from TSR1 and TSR0 registers to the Down Counter is completed and then
wait until the TSR1 register bit 1 is set by user.
¨
Setting the TSR1 register bit 1 to 1, the timer will
start to count. The timer will stop when the counter
content is equal to 0 and then the TOEF bit is set to
1.
¨
¨
The down counter is decremented (-1) in the cycle of
64/fSYS. If the value of the down counter becomes ²0²,
the zero detector generates the timer operation end signal to stop the timer operation. At this time, the TOEF bit
will be set to ²1². The output of the timer operation end
signal is continued while the down counter is ²0² and the
timer is stopped. The following relational expression applies between the timer¢s output time and the down
counter¢s setting value.
Timer output time = (Set value+1) ´ 64/fSYS
An example is shown below for fSYS=4MHz.
If the TSR1 register bit 1 is cleared during the timer
counting, the timer will be stopped. Once the TSR1
register bit 1 is set by a specific sequence, i.e.
1®0®1, the down counter will reload the data from
T8~T0, and then the down counter begins counting
down with the new load data.
MOV
MOV
MOV
A,0FFH
TSR0, A
A,01H
MOV
SET
TSR1, A
TSR1.1
If the TSR1 register bit 1 and the TOEF bit both are
equal to 1, the timer can re-start, after a new data is
written to the TSR0 and TSR1 register, i.e. T8~T0,
in sequence.
Note: If the Down counter content is equal to 000H,
set the T9 bit to start the timer counting, the timer will
only count 1 step. The timer output time = 64/fSYS. ®
[(0+1) ´ 64/fSYS=64/fSYS]
Rev. 1.10
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February 18, 2013
HT49RA0-6
Setting the T9 bit channels the timer output to the
REM/REMDRV pin. The REM/REMDRV pin will be a
combination of the timer output and carrier signals.
In the case above, the timer output time is as follows.
(Set value+1) ´ 64/fSYS
= (511+1) ´ 16ms
Note:
= 8.192ms
The timer output is shown as below if the
high-level period setting modulo register named
CARH bit 9 is set to 1.
T im e r O u tp u t
T im e r O u tp u t
8 .1 9 2 m s
T im e r O u tp u t T im e :
( S e t v a lu e + 1 ) x 6 4 /fS
Y S
T im e r O u tp u t w h e n C a r r ie r is n o t O u tp u t
Carrier Output
· Carrier output generator
The carrier generator consists of a 9-bit counter and two modulo registers known as the CARH and CARL registers
respectively for setting the high-level and low-level periods.
¨
CARL0 Register
Bit
7
6
5
4
3
2
1
0
Name
CL7
CL6
CL5
CL4
CL3
CL2
CL1
CL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
0
0
Bit 7~0
¨
CL7~CL0: Low level period modulo bit 7~0
CARL1 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
CL9
CL8
R/W
¾
¾
¾
¾
¾
¾
R
R/W
POR
¾
¾
¾
¾
¾
¾
0
0
Bit 7~2
unimplemented, read as ²0²
Bit 1
CL9: This bit is read only and fixed to ²0²
Bit 0
CL8: Low level period modulo bit 8
¨
CARH0 Register
Bit
7
6
5
4
3
2
1
0
Name
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
0
0
Bit 7~0
¨
CH7~CH0: Low level period modulo bit 7~0
CARH1 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
CH9
CH8
R/W
0
R/W
¾
¾
¾
¾
¾
¾
R
POR
¾
¾
¾
¾
¾
¾
1
Bit 7~2
unimplemented, read as ²0²
Bit 1
CH9: High level period modulo bit 9
If this bit is set to 1, the carrier signal will not be output.
Bit 0
CH8: High level period modulo bit 8
Rev. 1.10
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February 18, 2013
HT49RA0-6
The carrier duty ratio and carrier frequency can be determined by setting the high-level and low-level widths using the
respective modulo registers.
CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) are read and written using instructions.
Example:
MOV
A, XXH
; XXH = 00H~FFH
MOV
MOV
MOV
CARL0, A
A, XXH
CARL1, A
; XXH 01H, CL.8 (CARL1.0)
MOV
MOV
MOV
A, XXH
CARH0, A
A, XXH
MOV
CLR
CARH1, A
CARH1.1
; XXH = 00H~FFH
; XXH 02H, CH.8 (CARH1.0)
; The carrier is started by clearing CARH1.1 to 0
C A R H
C A R H 1
C a r r ie r
S ig n a l
C H .9
C A R Y
C A R L
C A R H 0
C H .8
C H .7
C H .6
C H .5
C H .4
C H .3
C A R L 1
C H .2
C H .1
C H .0
M o d u lo r e g is te r fo r s e ttin g th e h ig h - le v e l p e r io d
(C A R H .8 ~ C A R H .0 )
C L .9 (0 )
N o te 1 .
C A R L 0
C L .8
C L .7
C L .6
C L .5
C L .4
C L .3
C L .2
C L .1
C L .0
M o d u lo r e g is te r fo r s e ttin g th e lo w - le v e l p e r io d
(C A R L .8 ~ C A R L .0 )
S e le c to r
F /F
M a tc h
C le a r
C o m p a ra to r
9 - b it C o u n te r
fS
Y S
T 9 (N o te 2 )
fS
Y S
Configuration of Remote Controller Carrier Generator
Note:
1. The bit 9 of the modulo register for setting the low-level period (CARL) is fixed to 0.
2. T9: Flag that enables timer output (timer block, see Timer Configuration)
Rev. 1.10
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February 18, 2013
HT49RA0-6
The values of CARH and CARL can be calculated from the following expressions.
CARL (CARL1.0, CARL0.7 ~ CARL0.0) = ( fSYS ´ (1-D) ´ T) - 1 ¼¼¼ (1)
CARH (CARH1.0, CARH0.7 ~ CARH0.0) = (fSYS ´ D ´ T) - 1 ¼¼¼¼ (2)
(1) + (2) ® CARL + CARH = ( fSYS ´ T) - 2 ® Actual Carrier Frequency = fSYS / (CARL + CARH + 2)
D: Carrier duty ratio (0 < D < 1)
fSYS: Input clock (MHz)
T: Carrier cycle (ms)
Ensure to input values in the range from 001H to 1FFH to the CARL and CARH registers.
If fSYS = 4095kHz, Target fC = 38kHz, T = 1 / fC = 26.3157ms = tL + tH, duty = 1/3
CARL = (4.095M ´ (1 ´ 1/3) ´ 26.3157ms) ´ 1 = 70.842
select 71 = 47H, actual tL = (71+1) / 4.095M = 17.58ms
CARH = (4.095M ´ 1/3 ´ 26.3157ms) ´ 1 = 34.921
select 35=23H, actual tH = (35+1) / 4.095M = 8.79ms
For actual Carrier Frequency = fSYS / (CARL + CARH +2)
So, actual fC = fSYS / (CARL + CARH +2) = 4095kHz / (71 + 35 + 2) = 37.917kHz
· Carrier output control
The remote controller carrier can be output from the REM/REMDRV pin by clearing to zero bit 9 (CARY) of the
modulo register for setting the high-level period (CARH).
Be sure to set the timer operation after setting the CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0,
CARL0.7~CARL0.0) values when performing a carrier output.
Note that a malfunction may occur if the values of the CARH and CARL registers are changed while the carrier is being output on the REM/REMDRV pin.
Executing the timer manipulation instruction starts the carrier output from the low level.
There is a dual function remote controller carrier output pin named REM/REMDRV. The selection of REM or
REMDRV is determined by the TSR1 register bit 6. After a reset, the REM/REMDRV pin will be initiated to a
REMDRV carrier output function and its output status will be in a floating condition. The generic structures of the
REM or REMDRV function are illustrated in the accompanying diagram in the Input/Output Ports section. As the exact construction of the carrier output pin will differ from these drawings, they are supplied as a guide only to assist
with the functional understanding of the remote carrier output pins.
The output from the REM/REMDRV pin is in accordance with the value of the CARH bit 9 (CARY) and the timer output enable flag T9 together with the value of the 9-bit down timer counter (T0 to T8).
CARH1.1
Timer Output Enable Flag
(t9: TSR1.1)
9-bit
Down Counter
0
0
0
0
0
Other than 0
0
1
0
REM Function
(CMOS Output)
REMDRV Function
(NMOS Output)
Low-level output
Floating output
0
64/fSYS
(with carrier output)
64/fSYS
(with carrier output)
1
Other than 0
Carrier output (Note)
Carrier output
1
0
¾
Low-level output
Floating output
1
1
¾
High-level output
Low-level output
REM Pin Output Control
Note: The input value for CARH and CARL should be in the range from 001H to 1FFH.
Caution: The CARH and CARL value must be set while the REM/REMDRV pin is at its inactive level.
Rev. 1.10
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February 18, 2013
HT49RA0-6
Target
Setting
Actual
fC(kHz)
Duty
CARH (CARH 1, 0,
CARH0.7~CARH0.0)
CARL (CARL 1,0,
CARL0.7~CARL0.0)
tH(ms)
tL(ms)
T(ms)
fC(kHzs)
36
1/3
25H
4BH
9.28
18.56
27.84
35.92
38
1/3
23H
47H
8.79
17.58
26.37
37.92
56
1/3
18H
2FH
6.11
11.72
17.83
56.10
56
1/2
23H
24H
8.79
9.04
17.83
56.10
Carrier Frequency Setting (fSYS=4095kHz)
Target
Setting
Actual
fC(kHz)
Duty
CARH (CARH 1, 0,
CARH0.7~CARH0.0)
CARL (CARL 1,0,
CARL0.7~CARL0.0)
tH(ms)
tL(ms)
T(ms)
fC(kHzs)
36
1/3
24H
49H
9.25
18.50
27.75
36.04
38
1/3
22H
45H
8.75
17.50
26.25
38.10
56
1/3
17H
2EH
6.00
11.75
17.75
56.34
56
1/2
23H
22H
9.00
8.75
17.75
56.34
Carrier Frequency Setting (fSYS=4MHz)
tL
tH
C a r r ie r S ig n a l
t
Input/Output Ports
After chip reset, PA, PB0~6 and PC remain at a high
level input line and PB7 remains at a high impedance input line. Each bit of PA, PB and PC output latches can
be set or cleared by the ²SET [m].i² and ²CLR [m].i²
(m=12H , 14H or 16H) instructions respectively.
There are three 8-bit bidirectional input/output ports in the
device, labeled as PA, PB and PC which are mapped to
[12H], [14H], [16H] of the RAM respectively. Each bit of
PA, PB and PC can be selected as NMOS output or
Schmitt trigger with pull-high resistor by software instruction. Note that PB7 is without pull-high resistor.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m]²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator.
When PA, PB and PC for the input operation, these
ports are non-latched, that is, the inputs should be ready
at the T2 rising edge of the instruction ²MOV A, [m]²
(m=12H, 14H or 16H). For PA, PB and PC output operation all data are latched and remain unchanged until the
output latch is rewritten.
Each line of PA and PB has a wake-up capability to the
device by configuration option.
When the PA, PB and PC are used for input operation, it
should be noted that before reading data from pads, a
²1² should be written to the related bits to disable the
NMOS device. That is, the instruction ²SET [m].i²
(i=0~7, m=12H, 14H or 16H) is executed first to disable
the related NMOS device, and then use the instruction
²MOV A, [m]² to get stable data.
Rev. 1.10
Pins PC1~PC7 are pin-shared with SEG1~SEG7 and
are selected by the LCD Segment Control Register
named SEGCR.
25
February 18, 2013
HT49RA0-6
· I/O Resistor Lists
¨
Bit
Register
Name
7
6
5
4
3
2
1
0
SEGCR
SEG7C
SEG6C
SEG5C
SEG4C
SEG3C
SEG2C
SEG1C
Reserved
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
Reserved
SEGCR Register
Bit
7
6
5
4
3
2
1
0
Name
SEG7C
SEG6C
SEG5C
SEG4C
SEG3C
SEG2C
SEG1C
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
x
Bit 7~0
SEG7C~SEG1C: Segment 7~ Segment 1 selection bits
0: I/O
1: Segment output
V
D a ta b u s
W r ite
D
W e a k
P u ll- u p
Q
C K
D D
P A 0 ~ P A 7
P B 0 ~ P B 6
P C 1 ~ P C 7
Q
S
C h ip R e s e t
R e a d I/O
S y s te m
W a k e -u p
W a k e - u p S e le c t
Note that the pin-shared functions are not shown here.
PA, PB0~PB6 and PC Input/Output Ports
D a ta b u s
D
W r ite
P B 7
Q
C K
S
Q
C h ip R e s e t
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
W a k e - u p S e le c t
PB7 Input/Output Pin
V
D D
S /W
O p tio n
R E M
R E M
O u tp u t
Note that the S/W Option is the TSR1 register bit 6
REM/REMDRV Pin Structure
Rev. 1.10
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February 18, 2013
HT49RA0-6
LCD Driver
LCD Display Memory
LCD Driver Output
The device provides an area of embedded data memory
for LCD display. This area is located from address 41H
to 55H of the RAM at Bank 1. The Bank pointer (BP; located at 04H of the RAM) is the switch between the
RAM and the LCD display memory. When the BP is set
as ²1², any data written into 41H~55H will affect the LCD
display. When the BP is cleared to ²0², any data written
into 41H~55H means to access the general purpose
data memory.
The output number of the LCD driver device can be
21´2, 21´3 or 20´4 by configuration option. The LCD
driver bias type is ²C² type only. A capacitor mounted
between C1 and C2 pins is needed. If 1/2 bias is selected, a capacitor mounted between VC pin and ground
is required. If 1/3 bias is selected, two capacitors are
needed for VA and VC pins. All the capacitance of capacitors used for LCD bias generator is suggested to
use the 0.1mF. The relationships between LCD bias
types, bias levels and VA and VC connection are listed
in the table.
The LCD display memory can be read and written to
only by indirect addressing mode using MP1. When a
data is written into the display data area, it is automatically read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
on or off, a ²1² or a ²0² is written to the corresponding bit
of the display memory, respectively. The figure illustrates the mapping between the display memory and
LCD pattern for the device.
C O M
4 1 H
4 2 H
4 3 H
5 3 H
5 4 H
5 5 H
B it
1
1
2
2
3
3
Bias
Type
C1/C2
VA
VC
1/2
C
0.1mF
x
0.1mF
1/3
C
0.1mF
0.1mF
0.1mF
There is a clock source needed for the LCD driver. The
LCD clock source comes from the general purpose
prescaler and is decided by configuration options. The
LCD clock frequency should be selected as near to
4kHz either from 32768Hz LXT or LIRC or fSYS/4 clock
source.
0
0
Bias
Level
The options of LCD clock frequency are listed in the following table.
fS Clock Source
S E G M E N T
1
2
3
1 9
2 0
2 1
Display Memory
Rev. 1.10
27
LCD Clock Selection
LIRC oscillator
fLIRC/23
LXT oscillator
fLXT/23
fSYS/4
fSYS/24~fSYS/210
February 18, 2013
HT49RA0-6
D u r in g a R e s e t P u ls e
V B
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
V C
V S S
V B
V C
V S S
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
V B
V C
V S
C O M 0
C O M 1
C O M 2
L C D s e g m e n ts O N
C O M 0 ,1 ,2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 ,2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 ,2 s id e s a r e lig h te d
H A L T M o d e
S
S
S
S
S
S
S
S
S
S
V B
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
S
V C
V S S
V B
V C
V S S
d r iv e r o u tp u ts
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
V B = V A = V D D , V C = V D D x 1 /2
is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Bias, C Type)
Rev. 1.10
28
February 18, 2013
HT49RA0-6
V A
V B
C O M 0
V C
V S S
V A
V B
C O M 1
V C
V S S
V A
V B
C O M 2
V C
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V C
V S S
N o te : V A = V D D x 1 .5 , V B = V D D , V C = V D D x 1 /2
LCD Driver Output (1/4 Duty, 1/3 Bias, C Type)
Rev. 1.10
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February 18, 2013
HT49RA0-6
LCD/RTC OSC Control Register
Two bit in (1FH) are for controlling LCD and RTC OSC.
Bit No.
Label
Function
0
RTCEN
Controls RTC OSC enable (1=enabled; 0=;disabled)
1
LCDEN
Controls LCD enable (1=enabled; 0=disabled)
2~7
¾
Unused bit, read as ²0²
LCDC (1FH) Register
LCDEN and RTCEN may decide LCD and RTC On/Off condition on normal operation.
fS Clock
Source
LCD/RTC Control Bits
LCDEN, RTCEN=0, 0
LCDEN, RTCEN=0, 1
LCDEN, RTCEN=1, 0
LCDEN, RTCEN=1, 1
fSYS/4
LCD off, RTC off
LCD off, RTC off
LCD off, RTC off
LCD off, RTC off
WDT OSC
LCD off, RTC off
LCD off, RTC off
LCD on, RTC off
LCD on, RTC off
RTC OSC
LCD off, RTC on
LCD off, RTC on
LCD on, RTC on
LCD on, RTC on
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. LVR is
always enabled except in HALT mode. LVD can be enabled/disabled by options. Once the LVD options is enabled, the
user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5;
otherwise, the LVD function is disabled.
The RTCC register definitions are listed below.
Bit No.
Label
Function
0~2
RT0~RT2
3
LVDC*
LVD enable/disable (1/0)
4
QOSC
32768Hz OSC quick start-up oscillating
0/1: quickly/slowly start
5
LVDO
LVD detection output (1/0)
1: low voltage detected, read only
6, 7
¾
8 to 1 multiplexer control inputs to select the real clock prescaler output
Unused bit, read as ²0²
RTCC (09H) Register
Once the LVD function is enabled the reference generator should be enabled; otherwise the reference generator is
controlled by LVR Enable/Disable. The relationship among LVR and LVD options and LVDC are as shown.
LVDC can read/write, LVDO is read only.
LVD
LVR
LVDC
VREF Generator
LVR Comparator
LVD Comparator
Enable
Enable
On
Enable
Enable
Enable
Enable
Enable
Off
Enable
Enable
Disable
Enable
Disable
On
Enable
Disable
Enable
Enable
Disable
Off
Disable
Disable
Disable
Disable
Enable
X
Enable
Enable
Disable
Rev. 1.10
30
February 18, 2013
HT49RA0-6
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as might happen when changing a battery, the LVR will automatically reset the device internally. During a HALT state, LVR is disabled.
The relationship between VDD and VLVR is shown below.
V D D
3 .6 V
The LVR includes the following specifications:
V
L V R
1 .9 V
· The low voltage (0.9V~VLVR) state must exists for
more than 1ms, while the other circuits remain in their
original state. If the low voltage state does not exceed
1ms, the LVR will ignore it and do not perform a reset
function.
0 .9 V
· The LVR uses the ²OR² function with the power-on re-
set signal to perform a chip reset.
V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
D D
3 .6 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t
N o r m a l O p e r a tio n
*1
R e s e t
*2
Low Voltage Reset
Note:
²*1² To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
²*2² Low voltage state has to be maintained for over 1ms, then after a 1ms delay the device enters the reset
mode.
Rev. 1.10
31
February 18, 2013
HT49RA0-6
Options
The following table shows all kinds of options in the micro-controller. All of the options must be defined to ensure proper
system functioning.
Item
Options
I/O Options
1
PA0~PA7 wake-up: Enabled or Disabled
2
PB0~PB7 wake-up: Enabled or Disabled
Oscillator Options
3
System oscillator selection - fSYS:
XTAL oscillator without internal feedback resistor
XTAL oscillator with internal feedback resistor
Internal 4095kHz RC oscillator
4
fS internal clock source: fSYS /4 or LXT OSC or LIRC OSC
Interrupt Options
5
INT0 function : Disable, rising edge, falling edge or both edges
6
INT1 function : Disable, rising edge, falling edge or both edges
Timer/Event Counter Options
7
Timer/Event Counter (fTMR) clock source: fSYS/4 or fSYS
Time Base Options
8
Time Base frequency (fTB): fS/212 ~ fS/215
LVD Option
9
LVD Low Voltage Detect : enable or disabled
LCD Options
10
fLCD: LCD frequency (typical 4kHz): fS/22 ~ fS/28
11
LCD duty: 1/2, 1/3, 1/4 duty
12
LCD bias: 1/2, 1/3 bias
I/O Pin Option
13
I/O pin or XT1/XT2 pin
Rev. 1.10
32
February 18, 2013
HT49RA0-6
Application Circuits
The following application circuit shows the situation when a transistor is added to IR driver circuit. Here the MCU REM
function must be enabled.
VDD
VDD1
VBAT
C2
Battery
R1
10 ohm
R3
2 ohm C1
0.1uF
VDD
VSS
IR
LED
R2
Q1 250
8050 ohm
REM
PA0~PA7
PB0~PB7
VSS1
OSC
Circuit
OSC1
OSC2
See Oscillator
Section
COM0~COM2
COM3/SEG21
SEG1~SEG20
LCD
Panel
C1
0.1uF
XT1
C2
VA
0.1uF
XT2
VC
See Oscillator
Section
0.1uF
HT49RA0-6
Note:
1. The values of R1 and C2 should be selected in consultation with the actual application, R1=10W, C1=0.1mF,
C2=200~330mF are suggested values.
2. To obtain a better frequency stability and longer transmission distances, C2=330mF is a recommended
value. The frequency stability may be different and the transmission distance may be shorter if a value other
than 330mF is used.
3. VSS, VSS1, C2 and Q1 must be connected to the power GND terminal.
4. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS on the PCB .
5. The C1 (0.1mF) decoupling capacitor should be located as close to the VDD and VSS pins as possible.
6. R1 and C1 should be located as close to the VDD pin as possible
7. VDD and VDD1 must be connected to the power VBAT terminal.
8. The values of R1 and C2 should be selected in consultation with the actual application
9. It should to be noted that when programming the device, the HT49RA0-6 writer type is the e-Writer PRO,
which when used together with the e-Socket, can ensure that the HIRC oscillator frequency will have a
tolerance within 1% in the actual application circuit.
Rev. 1.10
33
February 18, 2013
HT49RA0-6
The following application circuit shows the situation when the internal IR driver circuit is used. Here the MCU REMDRV
function must be enabled.
VDD
VDD1
VBAT
C2
Battery
R1
10 ohm
R3
2 ohm C1
0.1uF
VDD
VSS
IR
LED
REMDRV
PA0~PA7
PB0~PB7
VSS1
OSC
Circuit
OSC1
OSC2
See Oscillator
Section
COM0~COM2
COM3/SEG21
SEG1~SEG20
LCD
Panel
C1
0.1uF
XT1
C2
VA
0.1uF
XT2
VC
See Oscillator
Section
0.1uF
HT49RA0-6
Note:
1. The values of R1 and C2 should be selected in consultation with the actual application, R1=10W, C1=0.1mF,
C2=47~100mF are suggested values.
2. To obtain a better frequency stability and longer transmission distances, C2=100mF is a recommended
value. The frequency stability may be different and the transmission distance may be shorter if a value other
than 100uF is used.
3. VSS, VSS1, C2 and Q1 must be connected to the power GND terminal.
4. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS on the PCB.
5. The C1 (0.1mF) decoupling capacitor should be located as close to the VDD and VSS pins as possible.
6. R1 and C1 should be located as close to the VDD pin as possible
7. VDD and VDD1 must be connected to the power VBAT terminal.
8. The values of R1 and C2 should be selected in consultation with the actual application
9. It should to be noted that when programming the device, the HT49RA0-6 writer type is the e-Writer PRO,
which when used together with the e-Socket, can ensure that the HIRC oscillator frequency will have a
tolerance within 1% in the actual application circuit.
Rev. 1.10
34
February 18, 2013
HT49RA0-6
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.10
35
February 18, 2013
HT49RA0-6
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.10
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
36
February 18, 2013
HT49RA0-6
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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HT49RA0-6
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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HT49RA0-6
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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HT49RA0-6
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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February 18, 2013
HT49RA0-6
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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HT49RA0-6
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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HT49RA0-6
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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HT49RA0-6
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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HT49RA0-6
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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HT49RA0-6
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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HT49RA0-6
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for
the latest version of the package information.
48-pin LQFP (7mm´7mm) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.350
¾
0.358
B
0.272
¾
0.280
C
0.350
¾
0.358
D
0.272
¾
0.280
E
¾
0.020
¾
F
¾
0.008
¾
G
0.053
¾
0.057
H
¾
¾
0.063
I
¾
0.004
¾
J
0.018
¾
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.10
1 2
Dimensions in mm
Min.
Nom.
Max.
8.90
¾
9.10
B
6.90
¾
7.10
C
8.90
¾
9.10
D
6.90
¾
7.10
E
¾
0.50
¾
F
¾
0.20
¾
G
1.35
¾
1.45
H
¾
¾
1.60
I
¾
0.10
¾
J
0.45
¾
0.75
K
0.10
¾
0.20
a
0°
¾
7°
48
February 18, 2013
HT49RA0-6
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc.
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2013 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
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