DS3883A BTL 9-Bit Data Transceiver General Description The DS3883A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3883A, is a BTL 9-bit Transceiver designed to conform to IEEE 1194.1 (Backplane Transceiver Logic — BTL) as specified in the IEEE 896.2 Futurebus+ specification. Utilization of the DS3883A simplifies the implementation of byte wide address/data with parity lines and also may be used for the Futurebus+ status, tag and command lines. The DS3883A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus thus reducing the bus loading in the inactive state. The combined output capacitance of the driver and receiver input is less than 5 pF. The driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. BTL eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching.The unique driver circuitry meets the maximum slew rate of 0.5 V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines.The transceiver’s control and driver inputs are designed with high impedance PNP input structures and are fully TTL compatible. The receiver is a high speed comparator that utilizes a bandgap reference for precision threshold control allowing maximum noise immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. The output is TRI-STATE ® and fully TTL compatible. The DS3883A supports live insertion as defined in 896.2 through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported the LI pin must be tied to the VCC pin. The DS3883A also provides glitch free power up/down protection during power sequencing. The DS3883A has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two logic VCC pins on the DS3883 that provide the supply voltage for the logic and control circuitry. Multiple power pins reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the V CC bus internal to the device, a voltage delta should never exist between these pins and the voltage difference between VCC and QV CC should never exceed ± 0.5V because of ESD circuitry. Additionally, the ESD circuitry between the VCC pins and all other pins except for BTL I/O’s and LI pins requires that any voltage on these pins should not exceed the voltage on VCC + 0.5V. There are three different types of ground pins on the DS3883A. They are the logic ground (GND), BTL grounds (B0GND–B8GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and B0GND–B8GND should be connected to the nearest backplane ground pin with the shortest possible path. Since many different grounding schemes could be implemented and ESD circuitry exists on the DS3883, it is important to note that any voltage difference between ground pins, QGND, GND or B0GND–B8GND should not exceed ± 0.5V including power-up/down sequencing. When CD (Chip Disable) is high, An and Bn are in a high impedance state. To transmit data (An to Bn) the T/R signal is high. To receive data (Bn to An) the T/R signal is low. Features n 9-bit Inverting BTL transceiver meets IEEE 1194.1 standard on Backplane Transceiver Logic (BTL) n Supports live insertion n Glitch free power-up/down protection n Typically less than 5 pF bus-port capacitance n Low bus-port voltage swing (typically 1V) at 80 mA n Open collector bus-port output allows Wired-OR n Controlled rise and fall time to reduce noise coupling n TTL compatible driver and control inputs n Built in bandgap reference with separate QV CC and QGND pins for precise receiver thresholds n Exceeds 2 kV ESD (Human Body Model) n Individual bus-port ground pins minimize ground bounce n Tight skew (1 ns typical) TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS010719 www.national.com DS3883A BTL 9-Bit Data Transceiver July 1998 Connection Diagram DS010719-17 Order Number DS3883AVF See NS Package Number VF44B www.national.com 2 Absolute Maximum Ratings (Note 1) Storage Temperature Range Lead Temperature (Soldering, 4 seconds) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Control Input Voltage Driver Input and Receiver Output Receiver Input Current Bus Termination Voltage Power Dissipation at 25˚C PQFP (VF44B) Derate PQFP Package (VF44B) −65˚C to +150˚C 260˚C Recommended Operating Conditions 6.5V 6.5V 5.5V ± 15 mA 2.4V Supply Voltage, VCC Bus Termination Voltage (VT) Operating Free Air Temperature 1.3W 11.1 mW/˚C Min 4.5 2.06 0 Max 5.5 2.14 70 Units V V ˚C Typ Max Units DC Electrical Characteristics (Notes 2, 3) TA = 0˚C to +70˚C, VCC = 5V ± 10% Symbol Parameter Conditions Min DRIVER AND CONTROL INPUT (CD, T/R , An) VIH Minimum Input High Voltage VIL Maximum Input Low Voltage II Input Leakage Current IIH Input High Current IIL Input Low Current VCL Input Diode Clamp Voltage 2.0 V VIN = V CC = 5.5V VIN = 2.4V, AN = CD = 0.5V, T/R = 2.4V VIN = 0.5V, AN = CD = 0.5V, T/R = 2.4V ICLAMP = −12 mA 0.8 V 250 µA 40 µA −100 µA −1.2 V 1.1 V DRIVER OUTPUT/RECEIVER INPUT (Bn) VOLB Output Low Bus Voltage (Note 5) IOFF Output Off Low Current Output Off High Current Output Off Low Current — An = T/R = 2.4V, CD = 0.5V IOL = 80 mA An = 0.5V, T/R = 2.4V, Bn = 0.75V, CD = 0.5V An = 0.5V, T/R = 2.4V, Bn = 2.1V, CD = 0.5V An = 0.5V, T/R = CD = 2.4V, Bn = 0.75V 0.75 1.0 −200 µA 200 µA −50 µA 50 µA Chip Disabled Output Off Low Current — An = 0.5V, T/R = CD = 2.4V, Bn = 2.1V Chip Disabled VTH Receiver Input Threshold VCLP Positive Clamp Voltage VCLN Negative Clamp Voltage T/R = CD = 0.5V VCC = Max or 0V, IBn = 1 mA, CD = T/R = 0V An = 0V 1.47 1.55 1.62 V 2.4 3.4 4.5 V VCC = Max or 0V, IBn = 10 mA, CD = T/R = 0V An = 0V 2.9 3.9 5.0 V −1.2 V 0.35 0.5 V 0.35 0.4 V 10 µA ICLAMP = −12 mA, CD = T/R = 0.5V RECEIVER OUTPUT (An) VOH Voltage Output High VOL Voltage Output Low IOZ TRI-STATE Leakage Current IOS Output Short Circuit Current Bn = 1.1V, T/R = CD = 0.5V, IOH = −2 mA T/R = CD = 0.5V, Bn = 2.1V, IOL = 24 mA T/R = CD = 0.5V, Bn = 2.1V, IOL = 8 mA An = 2.4V, CD = 2.4V, T/R = 0.5V An = 0.5V, CD = 2.4V, T/R = 0.5V Bn = 1.1V, T/R = CD = 0.5V (Note 4) 2.4 −40 3.2 −70 V −10 µA −100 mA 62 mA SUPPLY CURRENT ICC Supply Current: Includes VCC, QVCC and LI ILI Live Insertion Current T/R = All An Inputs = 2.4V, CD = 0.5V CD = T/R = 0.5V, All Bn Inputs = 2.1V T/R = CD = An = 0.5V, Bn = Open, VCC = QV CC = 5.5V T/R = All An = 2.4V, CD = 0.5V, Bn = Open VCC = QV CC = 5.5V 3 53 mA 2.2 mA 4.5 mA www.national.com DC Electrical Characteristics (Notes 2, 3) (Continued) Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC + 0.5V and shall not exceed the absolute maximum rating at any time, including power-up and power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QV CC and VCC. There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. LI and Bn pins do not have power sequencing requirements with respect to V CC and QVCC. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions: VCC = 5V and TA = 25˚C, unless otherwise stated. Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. AC Electrical Characteristics (Note 6) TA = 0˚C to +70˚C, VCC = 5V ± 10% Symbol Parameter Conditions Min Typ Max Units ns DRIVER tPHL An to Bn Propagation Delay CD = 0V, T/ R = 3V 1 3.5 6 1 3.5 6 ns Enable Time (Figure 1 and Figure 2) T/R = An = 3V 3 6 9 ns Disable Time (Figure 1 and Figure 3 ) 2.5 5 8 ns Enable Time (Figure 8 and Figure 9) CD = 0V 9 13.5 18 ns 2 6 10 ns 1 2.5 4.5 ns 1 2 4.5 ns 0.5 V/ns 3.5 ns tPLH tPHL CD to Bn tPLH tPHL T/R to Bn tPLH Disable Time tr Transition Time — Rise/Fall tf 20% to 80% SR Slew Rate is Calculated tSKEW (Figure 1 and Figure 2) CD = 0V, T/R = 3V (Note 10) from 1.3V to 1.8V (Figure 1 and Figure 2) (Note 10) CD = 0V T/R = 3V An to Bn Skew (Same Package) (Note 7) 1 RECEIVER tPHL Bn to An CD = T/ R = 0V 2 4 7 ns 1.5 4.5 7.5 ns CD to An (Figure 4 and Figure 5 ) Bn = 2.1V, T/R = 0V 4 8 12 ns (Figure 6 and Figure 7 ) Bn = 1.1V, T/R = 0V 2.5 6 9 ns 3 6.5 10 ns (Figure 6 and Figure 7 ) CD = 0V Bn = 2.1V 2 6 10 ns 3 7 12 ns 4 10 16 ns 2 6.5 10 ns 3 7 11 ns (Note 7) 1 3.5 ns tPLH tPLZ Disable Time tPZL Enable Time tPHZ Disable Time tPZH tPLZ Enable Time T/R to An Disable Time tPZL Enable Time tPHZ Disable Time (Figure 8 and Figure 9 ) Bn = 1.1V, CD = 0V tPZH Enable Time (Figure 6 and Figure 7 ) tSKEW Bn to An Skew (Same Package) PARAMETERS NOT TESTED Coutput BTL Output Capacitance (Note 8) 5 pF tNR Noise Rejection (Note 9) 1 ns Note 6: Input waveforms shall have a rise/fall time of 3 ns. Propagation delays are measured with a single output switching. Note 7: tSKEW is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note 8: The parameter is tested using TDR techniques described in 1194.0 BTL backplane Design Guide. Note 9: This parameter is tested during device characterization. The measurement revealed that the part will reject 1 ns pulse widths. Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Ω tied to +2.1V DC. www.national.com 4 Pin Description Pin Name Number Input/ of Pins Output A0–A8 9 I/O B0–B8 9 I/O BTL receiver input and driver output B0GND–B8GND 9 NA Parallel driver grounds reduce ground bounce due to high current switching of driver outputs. (Note 11) CD 1 I GND 2 NA Ground for switching circuits. (Note 11) LI 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 12) NC 8 NA No Connect QGND 1 NA Ground for receiver input bandgap reference and non-switching circuits. (Note 11) QVCC 1 NA T/R 1 I VCC 2 NA Description TTL TRI-STATE receiver output and driver input Chip Disable VCC supply for bandgap reference and non-switching circuits. (Note 12) Transmit/Receive — transmit (An to Bn), receive (Bn to An) VCC supply for switching circuits. (Note 12) Note 11: The multiplicity of parallel ground paths reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low inductance. (i.e., ground plane with power pins and many signal pins connected to the backplane ground.) If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset between their grounds will degrade the noise margin. Note 12: The same considerations for ground are used for VCC in reducing lead inductance (see (Note 11) ). QVCC and VCC should be tied together externally. If live insertion is not supported, the LI pin can be tied together with QVCC and VCC. Package Thermal Characteristics CD T/R An Bn (BTL) H X Z H L L L H L L H L Linear Feet per Minute Air Flow (LFPM) L H H L 0 82 L H L H 225 68 500 60 900 53 X = High or low logic state Z = High impedance state L = Low state H = High state θJA (˚C/W) 44-Pin PQFP Note 13: The above values are typical values and are different from the Absolute Maximum Rating values, which include guardbands. 5 www.national.com Logic Diagram DS010719-1 www.national.com 6 Test Circuit and Timing Waveforms DS010719-3 FIGURE 1. Driver Propagation Delay Set-Up DS010719-4 FIGURE 2. Driver: An to Bn, SR DS010719-5 FIGURE 3. Driver: CD to Bn DS010719-6 Switch Position S1 tPLH tPHL Open Close FIGURE 4. Receiver Propagation Delay Set-Up DS010719-7 FIGURE 5. Receiver: Bn to An 7 www.national.com Test Circuit and Timing Waveforms (Continued) Switch Position tPZL tPLZ DS010719-8 FIGURE 6. Receiver Enable/Disable Set-Up DS010719-9 FIGURE 7. Receiver: CD to An, T/R to An (tPHZ and tPZH only) DS010719-18 FIGURE 8. T/R to An, T/R to Bn DS010719-19 FIGURE 9. T/R to Bn (tPHL and tPLH only), T/R to An (tPZL and tPLZ only) www.national.com 8 tPZH tPHZ S1 Close Open S2 Open Close DS3883A BTL 9-Bit Data Transceiver Physical Dimensions inches (millimeters) unless otherwise noted Note: All dimensions in millimeters 44-Lead Plastic Quad Flatpak Order Number DS3883AVF NS Package Number VF44B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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