DS3885 BTL Arbitration Transceiver General Description Features The DS3885 is one in a series of transceivers designed specifically for the implementation of high performance Futurebus a and proprietary bus interfaces. The DS3885 Arbitration Transceiver is designed to conform to IEEE 1194.1 (Backplane Transceiver LogicÐBTL) as specified in the IEEE 896.2 Futurebus a specification. The Arbitration Transceiver incorporates the competition logic internally which simplifies the implementation of a Futurebus a application by minimizing the on board logic required. The DS3885 driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus thus reducing the bus loading in the inactive state. The BTL drivers also have high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semicon(Continued) Y Y Y Y Y Y Y Y Y Y Y Y Y Y 9-bit inverting BTL transceiver Meets IEEE 1194.1 standard on Backplane Transceiver Logic (BTL) Includes on chip competition logic and parity checking Supports live insertion Glitch free power-up/down protection Typically less than 5 pF bus-port capacitance Low bus-port voltage swing (typically 1V) at 80 mA Open collector bus-port output allows Wired-OR connection Exceeds 2 kV ESD testing (Human Body Model) Individual bus-port ground pins minimize ground bounce Controlled rise and fall time to reduce noise coupling to adjacent lines TTL compatible driver and control inputs Built in bandgap reference with separate QVCC and QGND pins for precise receiver thresholds Product offered in PLCC and PQFP package styles Connection Diagrams TL/F/10721 – 2 TL/F/10721 – 13 Order Number DS3885V or DS3885VF See NS Package Number V44A or VF44B TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10721 RRD-B30M75/Printed in U. S. A. DS3885 BTL Arbitration Transceiver January 1994 General Description (Continued) The DS3885 has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two VCC pins on the DS3885 that provide the supply voltage for the logic and control circuitry. Multiple power pins reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the VCC bus internal to the device, a voltage difference should never exist between these pins and the voltage difference between VCC and QVCC should never exceed g 0.5V because of ESD circuitry. Additionally, the ESD circuitry between the VCC pins and all other pins except for BTL I/O’s and LI pins requires that any voltage on these pins should not exceed the voltage on VCC a 0.5V There are three different types of ground pins on the DS3885. They are the logic ground (GND), BTL grounds (AB0GND – AB7GND/ABPGND) and the Bandgap reference ground (QGND). All of these reference pins are isolated within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and AB0GND – AB7GND/ABPGND should be connected to the nearest backplane ground pin with the shortest possible path. Since many different grounding schemes could be implemented and ESD circuitry exists on the DS3885, it is important to note that any voltage difference between ground pins, QGND, GND or AB0GND – AB7GND and ABPGND should not exceed g 0.5V including power-up/down sequencing. Three additional transceivers are included in the Futurebus a family. They are the DS3883A BTL 9-bit Transceiver. The DS3884A BTL Handshake Transceiver features selectable Wired-OR glitch filtering. The DS3886A BTL 9-bit Latching Data Transceiver contains edge triggered latches in the driver which may be bypassed during a fall-through mode. In addition, the device contains a transparent latch in the receiver section. The DS3875 Arbitration Controller included in the Futurebus a family supports all the required and optional modes for Futurebus a arbitration protocol. It is designed to be used in conjunction with the DS3884A and DS3885 transceivers. The LOGICAL INTERFACE FUTUREBUS a ENGINE (LIFE) is a high performance Futurebus a Protocol Controller designed for IEEE 896.1. The LIFE will handle all handshaking signals between the Futurebus a and the local bus interface. The Protocol Controller supports the Futurebus a compelled mode data transfer as both master and slave. The Protocol Controller can be configured to operate in compliance to IEEE 896.2 Profile B mode. The LIFE incorporates a DMA controller and 64-bit FIFO’s for fast queuing. All of the transceivers are offered in 44-pin PLCC and PQFP high density package styles. ductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. BTL eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching. The transceiver’s control and driver inputs are designed with high impedance PNP input structures and are fully TTL compatible. The receiver is a high speed comparator that utilizes a bandgap reference for precision threshold control allowing maximum noise immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. The output is TRI-STATEÉ and fully TTL compatible. The signals abk7:0l designate the arbitration bus number which this transceiver places on the bus. The signal names ABk7:0l designate the open collector Wired-OR signals on the backplane bus. The DS3885 implements an odd parity check on the arbitration bus bits ABk7:0l, with ABP being the parity bit. The signal PER will indicate the parity check result. For a quick indication of current bus conditions, the bus status block generates ALL1 (all asserted) status when all bits (ABk7:0l) are asserted by any module. This signal is used by the DS3875 Arbitration Controller to detect the Arbitration message number (during phase 1) or the powerfail message number (during phase 2). To latch the arbitration number into the transceiver, it is placed onto the CNk7:0l port, and the CNÐLE signal is asserted. When the CMPT signal is asserted, the arbitration number is placed on the bus lines AB k7:0l. The WINÐGT signal serves two purposes during the arbitration cycle. If the CMPT signal is not asserted during the arbitration cycle, the transceiver compares its internally latched number to the number on the ABk7:0l bus lines. If the internal number on the transceiver is greater than or equal to the number on the ABk7:0l lines, the WINÐGT signal is asserted. However, if the CMPT signal is asserted, the transceiver participates in the competition. If the transceiver wins the arbitration, the WINÐGT signal is asserted to confirm the winning. The ABÐRE signal is used to enable the on-chip receiver outputs. The DS3885 supports live insertion as defined in IEEE 896.2 through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported the LI pin must be tied to the VCC pin. The DS3885 also provides glitch free power-up/down protection during power sequencing. 2 Absolute Maximum Ratings (Notes 1 and 2) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Control Input Voltage Driver Input and Receiver Output Receiver Input Current Bus Termination Voltage Power Dissipation at 25§ C PLCC PQFP Derate PLCC Package Derate PQFP Package b 65§ C to a 150§ C Lead Temperature (Soldering, 4 sec.) 260§ C Recommended Operating Conditions 6.5V 6.5V 5.5V g 15 mA Min 4.5 2.06 0 Supply Voltage, VCC 2.4V 2.5W 1.3W 20 mW/§ C 11.1 mW/§ C Bus Termination Voltage (VT) Operating Free Air Temperature Max 5.5 2.14 70 Units V V §C DC Electrical Characteristics (Notes 2 and 3) TA e 0§ C to a 70§ C, VCC e 5V g 10% Symbol Parameter Conditions Min Typ Max Units 0.8 V DRIVER AND CONTROL INPUT (CNn CNP, CNÐLE, CMPT, and ABÐRE) VIH Minimum Input High Voltage VIL Maximum Input Low Voltage 2.0 V II Input Leakage Current VIN e VCC e 5.5V 100 mA IIH Input High Current VIN e 2.4V 40 mA IIL Input Low Current VIN e 0.5V b 100 mA VCL Input Diode Clamp Voltage ICLAMP e b12 mA b 1.2 V DRIVER OUTPUT/RECEIVER INPUT (ABn and ABP) VOLB Output Low Bus Voltage (Note 5) CNn e ABÐRE e 2.4V, CNÐLE e CMPT e 0.5V IOL e 80 mA IOLBZ Output Low Bus Current IOHBZ Output High Bus Current CMPT e ABÐRE e 2.4V, ABn e 0.75V CMPT e ABÐRE e 2.4V, ABn e 2.1V VTH Receiver Input Threshold VCLP Positive Clamp Voltage VCLN Negative Clamp Voltage 0.75 1.0 1.1 V b 100 mA 100 mA 1.47 1.55 1.62 V VCC e Max or 0V, IABn e 1 mA 2.4 3.4 4.5 V VCC e Max or 0V, IABn e 10 mA 2.9 3.9 ICLAMP e b12 mA 5.0 V b 1.2 V RECEIVER OUTPUT (CNn, CNP, ALL1, PER, and WINÐGT) VOH Voltage Output High ABn e 1.1V, ABÐRE e 0.5V, CMPT e CNÐLE e 2.4V, IOH e b2 mA VOL Voltage Output Low ABn e 2.1V, ABÐRE e 0.5V, CMPT e CNÐLE e 2.4V, IOL e 24 mA 0.35 0.5 V ABn e 2.1V, ABÐRE e 0.5V, CMPT e CNÐLE e 2.4V, IOL e 8 mA 0.30 0.4 V IOZ IOS TRI-STATE Leakge Current Output Short Circuit Current 2.4 3.2 CNn e CNP e 2.4V, e 2.4V, ABÐRE e 2.4V CNn e CNP e 0.5V, ABÐRE e 2.4V ABn e 1.1V, ABÐRE e 0.5V CMPT e CNÐLE e 2.4V (Note 4) b 40 V 40 mA b 100 mA b 70 b 100 mA SUPPLY CURRENT ICC ILI Supply Current: Includes VCC, QVCC and LI CMPT e CNÐLE e 0.5V, All CNn e ABÐRE e 2.4V 75 100 mA CMPT e CNÐLE e ABÐRE e 2.4V 26 40 mA Live Insertion Current CMPT e ABÐRE e CNn e 2.4V, CNÐLE e 0.5V CMPT e CNÐLE e 0.5V, All CNn e ABÐRE e 2.4 1.5 3 mA 3 5 mA 3 DC Electrical Characteristics (Notes 2 and 3) TA e 0§ C to a 70§ C, VCC e 5V g 10% (Continued) Note 1: Absolute Maximum Ratings are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC a 0.5V and shall not exceed the absolute maximum rating at any time, including power-up and powerdown. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC. There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. LI and Bn pins do not have power sequencing requirements with respect to VCC and QVCC. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions: VCC e 5V and TA e 25§ C, unless otherwise stated. Note 4: Only one output should be shorted at a time, and duration of the short not to exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. AC Electrical Characteristics TA e 0§ C to a 70§ C, VCC e 5V g 10% (Note 6) Symbol Parameter Conditions Min Typ Max Units DRIVER (Figures 1 and 2 ) tPHL CNÐLE to AB7 Propagation Delay CMPT e 0V, ABÐRE e 3V tPLH tr tf Transition TimeÐRise/Fall 20% to 80% 7 13 18 ns 6 10 17 ns ABÐRE e 3V, CMPT e CNÐLE e 0 ABÐRE e 3V, CMPT e CNÐLE e 0 3 ns 1 ns DRIVER TIMING REQUIREMENTS (Figures 1 and 2 ) tS CNn to CNÐLE Set-Up Time ABÐRE e 3V, CMPT e 0V 9 tH CNÐLE to CNn Hold Time ABÐRE e 3V, CMPT e 0V 0 ns ns tPW CNÐLE Pulse Width ABÐRE e 3V, CMPT e 0V 15 ns ABÐRE e 0V, CMPT e CNÐLE e 3V (Figures 4 and 5 ) 5 13 22 3 15 23 ns CMPT e CNÐLE e 3V, ABn e 2.1V (Figures 6 and 7 ) 3 6 11 ns 5 9 13 ns CMPT e CNÐLE e 3V, ABn e 1.1V (Figures 6 and 7 ) 4 7 12 ns 3 6 11 ns AB0 to ALL1 Propagation Delay All Asserted Condition AB k7:1l e 1.1V (Figures 4 and 8 ) 7 16 28 ns 7 16 26 ns AB0 to WINÐGT Win Condition CMPT e CNÐLE e 0V, ABÐRE e 3V, CN k7:0l e 0V ABk7:0l e 2.1V (Figures 4 and 9 ) 6 14 23 ns 6 14 23 ns CMPT e ABÐRE e 3V, CNÐLE e 0V, CN k7:1l e 0V, CN0 e 3V ABk7:0l e 2.1V (Figures 4 and 9 ) 6 16 27 ns 6 16 26 ns CMPT e CNÐLE e ABÐRE e 3V, AB k7:1l e 1.1V, AB0 e 2.1V (Figures 4 and 8 ) 6 13 23 ns 4 13 23 ns 5 12 22 ns 5 13 23 ns 4 8 14 ns 5 9 16 ns RECEIVER tPHL ABn to CNn Propagation Delay tPLH tPLZ ABÐRE to CNn Disable Time tPZL Enable Time tPHZ Disable Time tPZH Enable Time ns OTHERS tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay AB0 to WINÐGT Propagation Delay Greater Than Condition ABP to PER Propagation Delay Parity Error Condition ABn to AB knb1l Propagation Delay tPLH tPHL CMPT to AB7 Propagation Delay tPLH tPHL tPLH AB7 to ABP Propagation Delay CMPT e CNÐLE e 0V, ABÐRE e 3V, CNn e 0V, CN knb1l e 3V, CN k7:n a 1l e 0V, AB k7:n a 1l e 2.1V (Figures 1 and 10 ) CNÐLE e 0V, ABÐRE e CN7 e 3V (Figures 1 and 3 ) CMPT e CNÐLE e 0V, ABÐRE e CNP e 3V, CN k7:0l e 0V (Figures 1 and 10 ) 4 36 60 ns 36 60 ns AC Electrical Characteristics TA e 0§ C to a 70§ C, VCC e 5V g 10% (Note 6) (Continued) Symbol Parameter Conditions Min Typ Max Units PARAMETERS NOT TESTED Coutput Capacitance at Bn (Note 7) 5 pF tNR Noise Rejection (Note 8) 1 ns Note 6: All input rise/fall times should be 3 ns. Note 7: This parameter is tested using TDR techniques described in 1194.0 BTL Backplane Design Guide. Note 8: This parameter is tested during device characterization. The measurement revealed that the part will typically reject 1 ns pulse width. Pin Description Number of Pins Input/ Output ALL1 1 O ABk7:0l 8 I/O BTLÐFuturebus a Wired-OR competition bits ABP 1 I/O BTLÐFuturebus a Wired-OR competition parity bit ABk7:0l and 9 NA Parallel driver grounds reduce ground bounce due to high current switching of driver outputs (Note 9) CNk7:0l 8 I/O TTL TRI-STATEÐModule competition bits CNP 1 I TTL TRI-STATEÐModule competition parity bit CMPT 1 I TTLÐCompetition bit (A logic ‘‘0’’ indicates that the module will compete in the arbitration.) GND 3 NA CNÐLE 1 I TTLÐCNn latch enable (A logic ‘‘0’’ indicates that the CNknl logic states are latched with corresponding parity bit). LI 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 10) NC 3 NA PER 1 O TTLÐABn odd parity (A logic ‘‘0’’ indicates parity error) ABÐRE 1 I TTLÐReceiver Enable (A logic ‘‘0’’ enables receivers) QGND 1 NA Ground for receiver input bandgap reference and non-switching circuits. (Note 9) QVCC 1 NA VCC supply for bandgap reference and non-switching circuits. (Note 2) VCC 2 NA VCC supply for switching circuits. (Note 10) WINÐGT 1 O Pin Name ABP GND Description TTLÐAll asserted (A logic ‘‘1’’ indicates that all the competition bits are asserted.) Ground for switching circuits. (Note 9) No connect TTLÐWin signal (active low). During competition, WINÐGT indicates that the module has won the competition. For a module not participating in the competition, WINÐGT indicates that the module has a number which is greater than winner’s number. Note 9: The multiplicity of parallel ground paths, reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low inductance (i.e., ground plane with power pins and many signal pins connected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset between their grounds will degrade the noise margin. Note 10: The same considerations for ground are used for VCC in reducing lead inductance. (See Note 9) QVCC and VCC should be tied together externally. If live insertion is not supported, the LI pin can be tied together with QVCC and VCC. 5 Package Thermal Characteristics ija (§ C/W) Linear Feet Per Minute Air Flow (LFPM) 44-Pin PQFP 44-Pin PLCC 0 82 45 225 68 35 500 60 30 900 53 26 Note: The above values are typical values and are different from the Absolute Maximum Rating values, which include guardbands. Typical Application TL/F/10721 – 14 DS3885 Block Diagram TL/F/10721 – 15 6 Function Diagram Parallel Implementation of Parallel Contention Logic TL/F/10721 – 1 7 Test Circuits and Timing Waveforms TL/F/10721–3 FIGURE 1. Driver Propagation Delay Set-up TL/F/10721 – 4 FIGURE 2. Driver: CNÐLE to AB7, tS, tH, tPW TL/F/10721 – 5 FIGURE 3. Driver: CMPT to AB7 Switch Position S1 tPLH tPHL open close TL/F/10721–6 FIGURE 4. Receiver Propagation Delay Set-Up TL/F/10721 – 7 FIGURE 5. Receiver: ABn to CNn 8 Test Circuits and Timing Waveforms (Continued) Switch Position tPZL tPLZ tPZH tPHZ S1 close open S2 open close TL/F/10721 – 8 FIGURE 6. Receiver Enable/Disable Set-Up TL/F/10721 – 10 TL/F/10721 – 9 FIGURE 7. Receiver: ABÐRE to CNn FIGURE 8. AB0 to ALL1, AB0 to PER TL/F/10721 – 11 TL/F/10721 – 12 FIGURE 9. AB0 to WINÐGT, ABP TO PER FIGURE 10. ABn to ABkn-1l, AB7 to ABP 9 10 Physical Dimensions inches (millimeters) 44-Lead Plastic Chip Carrier Order Number DS3885V NS Package Number V44A 11 DS3885 BTL Arbitration Transceiver Physical Dimensions inches (millimeters) (Continued) 44-Lead Plastic Quad Flatpack Order Number DS3885VF NS Package Number VF44B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.