DS3886A BTL 9-Bit Latching Data Transceiver General Description The DS3886A is a higher speed, lower power, pin compatible version of the DS3886. The DS3886A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3886A is a BTL 9-Bit Latching Data Transceiver designed to conform to IEEE 1194.1 (Backplane Transceiver Logic — BTL) as specified in the IEEE 896.2 Futurebus+ specification. The DS3886A incorporates an edge-triggered latch in the driver path which can be bypassed during fall-through mode of operation and a transparent latch in the receiver path. Utilization of the DS3886A simplifies the implementation of byte wide address/data with parity lines and also may be used for the Futurebus+ status, tag and command lines. The DS3886A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with it’s collector to isolate the transistor output capacitance from the bus, thus reducing the bus loading in the inactive state. The combined output capacitance of the driver output and receiver input is less than 5 pF. The driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching. The unique driver circuitry meets the maximum slew rate of 0.5 V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines. The transceiver’s high impedance control and driver inputs are fully TTL compatible. The receiver is a high speed comparator that utilizes a Bandgap reference for precision threshold control, allowing maximum noise immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. The output is TRI-STATE ® and fully TTL compatible. The DS3886A supports live insertion as defined in IEEE 896.2 through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported, the LI pin must be tied to the VCC pin. The DS3886A also provides glitch free power up/down protection during power sequencing. The DS3886A has two types of power connections in addition to the LI pin. They are the Logic VCC (VCC) and the Quiet VCC (QVCC). There are two Logic VCC pins on the DS3886A that provide the supply voltage for the logic and control circuitry. Multiple connections are provided to reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the VCC bus internal to the device, a voltage delta should never exist between these pins and the voltage difference between V CC and QVCC should never exceed ± 0.5V because of ESD circuitry. When CD (Chip Disable) is high, An is in high impedance state and Bn is high. To transmit data (An to Bn) the T/R signal is high. When RBYP is high, the positive edge triggered flip-flop is in the transparent mode. When RBYP is low, the positive edge of the ACLK signal clocks the data. In addition, the ESD circuitry between the VCC pins and all other pins except for BTL I/O’s and LI pins requires that any voltage on these pins should not exceed the voltage on VCC +0.5V. There are three different types of ground pins on the DS3886A; the logic ground (GND), BTL grounds (B0GND–B8GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and B0GND–B8GND should be connected to the nearest backplane ground pin with the shortest possible path. Since many different grounding schemes could be implemented and ESD circuitry exists on the DS3886A, it is important to note that any voltage difference between ground pins, QGND, GND or B0GND–B8GND should not exceed ± 0.5V including power up/down sequencing. The DS3886A is offered in 44-pin PLCC, and 44-pin PQFP high density package styles. Features n n n n n n n n n Fast propagation delay (3ns typ) 9-BIT BTL Latched Transceiver Driver incorporates edge triggered latches Receiver incorporates transparent latches Meets IEEE 1194.1 Standard on Backplane Transceiver Logic (BTL) Supports Live Insertion Glitch free Power-up/down protection Typically less than 5 pF Bus-port capacitance Low Bus-port voltage swing (typically 1V) at 80 mA TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS011458 www.national.com DS3886A BTL 9-Bit Latching Data Transceiver June 1998 Features n TTL compatible Driver and Control inputs n Built in Bandgap reference with separate QV CC and QGND pins for precise receiver thresholds n Individual Bus-port ground pins n Product offered in PLCC and PQFP package styles n Tight skew (0.5 ns typical) (Continued) n Exceeds 2 KV ESD testing (Human Body Model) n Open collector Bus-port outputs allows Wired-OR connection n Controlled rise and fall time to reduce noise coupling to adjacent lines Connection Diagrams DS011458-1 DS011458-2 Order Number DS3886AV, or DS3886AVF See NS Package Number V44A, or VF44B www.national.com 2 Absolute Maximum Ratings (Notes 1, 2) Derate PQFP Package (VF44B) Storage Temperature Range Lead Temperature (Soldering, 4 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Control Input Voltage Driver Input and Receiver Output Receiver Input Current Bus Termination Voltage Power Dissipation at 25˚C PLCC (V44A) PQFP (VF44B) Derate PLCC Package (V44A) 6.5V 6.5V 11.1 mW/˚C −65˚C to +150˚C 260˚C Recommended Operating Conditions 5.5V ± 15 mA 2.4V Min 4.5 2.06 0 Supply Voltage (VCC) Bus Termination Voltage (VT) Operating Free Air Temperature 2.5W 1.3W 20 mW/˚C Max 5.5 2.14 70 Units V V ˚C DC Electrical Characteristics (Notes 3, 4) TA = 0˚ to +70˚C, VCC = 5V ± 10% Symbol Parameter Conditions Min Typ Max Units DRIVER AND CONTROL INPUT (CD, T/R, An, ACLK, LE and RBYP) VIH Minimum Input High Voltage VIL Maximum Input Low Voltage II Input Leakage Current 2.0 IIH Input High Current IIL Input Low Current IIL Input Low Current VIN = V CC = 5.5V VIN = 2.4V, An = CD = 0.5V, T/R = 2.4V VIN = 0.5V, An = CD = 0.5V, T/R = 2.4V An Port, An = 0.5V, CD = 0.5V Input Diode Clamp Voltage T/R = 2.4V, RBYp = 2.4V ICLAMP = −12 mA VCL V 0.8 V 250 µA 40 µA −10 µA −100 µA −1.2 V 1.1 V DRIVER OUTPUT/RECEIVER INPUT (Bn) VOLB Output Low Bus Voltage An = T/R = 2.4V, CD = 0.5V, IOL = 80 mA 0.75 1.0 (Note 4) IOFF Output Off Low Current Output Off High Current Output Off Low Current-Chip Disabled Output Off High Current-Chip Disabled VTH Receiver Input Threshold VCLP Positive Clamp Voltage VCLN Negative Clamp Voltage An = 0.5V, T/R = An = 0.5V, T/R = An = 0.5V, T/R = An = 0.5V, T/R = 2.4V, Bn = 0.75V, CD = 0.5V 2.4V, Bn = 2.1V, CD = 0.5V CD = 2.4V, Bn = 0.75V CD = 2.4V, Bn = 2.1V −200 µA 200 µA −50 µA 50 µA T/R = CD = 0.5V VCC = Max or 0V, Bn = 1 mA VCC = Max or 0V, Bn = 10 mA ICLAMP = −12 mA 1.47 1.55 1.62 V 2.4 3.4 4.5 V 2.9 3.9 5.0 V −1.2 V Bn = 1.1V, IOH = −2mA, T/R = CD = 0.5V T/R = CD = 0.5V, Bn = 2.1V, IOL = 24 mA 2.4 RECEIVER OUTPUT (An) VOH Voltage Output High VOL Voltage Output Low IOZ IOS TRI-STATE Leakage Current Output Short Circuit Current T/R = CD = 0.5V, Bn = VIN = 2.4V, CD = 2.4V, Bn = 0.75V VIN = 0.5V, CD = 2.4V, Bn = 0.75V Bn = 1.1V, T/R = CD = 3 2.1V, IOL = 8 mA T/R = 0.5V, 3.2 0.5 0.30 0.4 V 10 µA −10 µA −100 mA T/R = 0.5V, 0.5V (Note 3) −40 V 0.35 −70 V www.national.com DC Electrical Characteristics (Notes 3, 4) (Continued) TA = 0˚ to +70˚C, VCC = 5V ± 10% Symbol Parameter Conditions Min Typ Max Units 55 62 mA 45 53 mA 1.5 2.2 mA 3 4.5 mA SUPPLY CURRENT I CCT ICCT — Power Supply Current for a TTL High Input (VIN = VCC − 2.1V) Supply Current: Sum of V CC, QVCC and LI ILI Live Insertion Current T/R = All An = 3.4V, CD = 0.5V ACLK = LE = RBYP = 3.4V T/R = 0.5V, All Bn = 2.1V, LE = CD = 0.5V ACLK = RBYP = 3.4V T/R = An = CD = ACLK = 0.5V T/R = All An = RBYB = 2.4V, CD = ACLK = 0.5V Note 1: “Absolute maximum ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All input and/or output pins shall not exceed VCC plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVCC and VCC. There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used when pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50 mA. Exception, LI and Bn pins do not have power sequencing requirements with respect to VCC and QVCC. Furthermore, the difference between VCC and QVCC should never be greater than 0.5V at any time including power-up. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. All typical values are specified under these conditions: VCC = 5V and TA = 25˚C, unless otherwise stated. Note 4: Only one output should be shorted at a time, and duration of the short should not exceed one second. Note 5: Referenced to appropriate signal ground. Do not exceed maximum power dissipation of package. AC Electrical Characteristics (Note 5) TA = 0˚C to +70˚C, VCC = 5V ± 10% Symbol Parameter Conditions Min Typ Max Units ns DRIVER tPHL An to Bn tPLH Fall-through mode tPHL ACLK to Bn tPLH Latch mode tPHL CD to Bn tPLH tPHL T/R to Bn CD = 0V, T/ R = RBYP = 3V 1 3 5 1.5 3 5 ns Propagation Delay (Figure 1 and Figure 2) CD = RBYP = 0V, T/R = 3V 1.7 4 6.5 ns (Figure 1 and Figure 4) T/R = 3V, An = 3V 2 4 6.5 ns Enable Time 3 5 9 ns Disable Time (Figure 1 and Figure 3) 2.5 5 6.7 ns Enable Time CD = 0V (Figure 10 and Figure 11), RBYP = 3V CD = 0V (Figure 10 and Figure 11), RBYP = 3V CD = RBYP = 0V, T/R = 3V (Figure 1 and Figure 3) (Note 10) 9 13 18 ns 2 5 8 ns 1 2 3.5 ns Disable Time tPLH tr Propagation Delay Transition Time-Rise/Fall tf 20% to 80% SR Slew Rate is calculated from CD = RBYP = 0V, T/R = 3V 1.3V to 1.8V (Figure 1 and Figure 2) (Note 10) tskew 1 2 4 0.85 0.5 V/ns ACLK to Bn Same Package (Note 7) 0.8 3 ns An to Bn Same Package (Note 7) 0.8 3 ns DRIVER TIMING REQUIREMENTS (Figure 4) CD = RBYP = 0V, T/R = 3V CD = RBYP = 0V, T/R = 3V CD = RBYP = 0V, T/R = 3V 3 ns 1 ns 3 ns Propagation Delay CD = T/ R = 0V, LE = 3V 3 4.5 6 3 4.5 6.5 ns Propagation Delay (Figure 5 and Figure 6) CD = T/ R = 0V 3.5 5.5 10 ns (Figure 5 and Figure 7) 4.5 5.5 8.5 ns tS An to ACLK Set-up Time tH ACLK to An Hold Time tpw ACLK Pulse Width RECEIVER tPHL Bn to An tPLH Bypass Mode tPHL LE to An tPLH Latch Mode www.national.com 4 ns AC Electrical Characteristics (Note 5) (Continued) TA = 0˚C to +70˚C, VCC = 5V ± 10% Symbol Parameter Conditions Min Typ Max Units 3 5 10 ns 2.5 6 8 ns RECEIVER tPLZ CD to An Enable Time tPHZ Disable Time tPZH Enable Time tPLZ T/R to An Bn = 1.1V, T/R = 0V (Figure 8 and Figure 9) LE = 3.0V, Bn = 2.1V Disable Time 4 6 8.5 ns 2.5 5 8.5 ns 3 7.5 12 ns CD = 0V (Figure 10 and Figure 11) LE = 3.0V 5 9.5 15 ns 3 6 9 ns Enable Time Bn = 1.1V, CD = 0V (Figure 8 and Figure 9) 3 6 9 ns LE to An Same Package (Note 7) 0.5 3 ns Bn to An Same Package (Note 7) 0.5 2.5 ns tPZL Enable Time tPHZ Disable Time tPZH tskew LE = 3.0V Bn = 2.1V, T/R = 0V (Figure 8 and Figure 9) LE = 3.0V Disable Time tPZL RECEIVER TIMING REQUIREMENTS (Figure 7) tS Bn to LE Set-up Time tH LE to Bn Hold Time tpw LE Pulse Width CD = T/R = 0V CD = T/R = 0V CD = T/R = 0V 3 ns 1 ns 5 ns PARAMETERS NOT TESTED Coutput Capacitance at Bn (Note 8) 5 pF tNR Noise Rejection (Note 9) 1 ns Note 6: Input waveforms shall have a rise and fall time of 3 ns. Note 7: tskew is an absolute value defined as differences seen in propagation delay between drivers in the same package with identical load conditions. Note 8: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide. Note 9: This parameter is tested during device characterization. The measurements revealed that the part will typically reject 1 ns pulse width. Note 10: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5 V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5Ω tied to +2.1 V DC. Pin Description Pin Name Number of Input/ Pins Output A0–A8 9 I/O ACLK 1 I B0–B8 9 I/O BTL receiver input and driver output B0GND–B8GND 9 NA Driver output ground reduces ground bounce due to high current switching of driver outputs. (Note 11) CD 1 I GND 2 NA LE 1 I LI 1 NA Power supply for live insertion. Boards that require live insertion should connect LI to the live insertion pin on the connector. (Note 12) NC 5 NA No Connect QGND 1 NA Ground reference for receiver input bandgap reference and non-switching circuits. (Note 11) VCC supply for bandgap reference and non-switching circuits. (Note 12) QVCC 1 NA RBYP 1 I T/R 1 I VCC 2 NA Description TTL TRI-STATE receiver output and driver input Clock input for latch Chip Disable Ground reference for switching circuits.(Note 10) Latch Enable Register bypass enable Transmit/Receive — Transmit (An to Bn) Receive (Bn to An) VCC supply for switching circuits. (Note 12) Note 11: The multiplicity of grounds reduces the effective inductance of bonding wires and leads, which then reduces the noise caused by transients on the ground path. The various ground pins can be tied together provided that the external ground has low iductance (i.e., ground plane with power pins and many signal pins con- 5 www.national.com Pin Description (Continued) nected to the backplane ground). If the external ground floats considerably during transients, precautionary steps should be taken to prevent QGND from moving with reference to the backplane ground. The receiver threshold should have the same ground reference as the signal coming from the backplane. A voltage offset between their grounds will degrade the noise margin. Note 12: The same considerations for ground are used for V CC in reducing lead inductance (see (Note 10) ). QVCC and VCC should be tied together externally. If live insertion is not supported, the LI pin can be tied together with QV CC and VCC. CD T/R LE RBYP ACK An H X X X X Z Bn H L H X H X L H L H X H X H L L H X L X X Bn0 L H X L L-H H L L H X L L-H L H L L H X X H L L L H X X L H L L L X X An0 X X = High or low logic state Z = High impedance state L = Low state H = High state L-H = Low to high transition An0 = no change from previous state Bn0 = no change from previous state BTL = high and low state are nominally 2.1V and 1.0V, respectively. TTL = high and low state are nominally 2.4V and 0.5V, respectively. Package Thermal Characteristics θ JA (˚C/W) Linear Feet per Minute Air 44-Pin 44-Pin Flow (LFPM) PQFP PLCC 0 82 45 225 68 35 500 60 30 900 53 26 Note 13: The above values are typical values and are different from the Absolute Maximum Rating values, which include guardbands. www.national.com 6 Logic Diagram DS011458-3 Test Circuits and Timing Waveforms DS011458-6 DS011458-5 FIGURE 2. Driver: An to Bn, CD to An FIGURE 1. Driver Propagation Delay Set-up 7 www.national.com Test Circuits and Timing Waveforms (Continued) DS011458-7 FIGURE 3. Driver: CD to Bn DS011458-11 FIGURE 7. Receiver Enable/Disable Set-up DS011458-12 Switch Position tPZL DS011458-8 FIGURE 4. Driver: ACLK to Bn, tS, tH, tPW tPZH tPLZ tPHZ S1 close open S2 open close FIGURE 8. Receiver: Enable/Disable Set-up DS011458-9 Switch Position S1 tPLH tPHL open close DS011458-13 FIGURE 9. Receiver: CD to An, T/R to An (tPHZ and tPZH only) FIGURE 5. Receiver Propagation Delay Set-up DS011458-10 DS011458-14 FIGURE 6. Receiver: Bn to An FIGURE 10. T/R to An, T/R to Bn www.national.com 8 Test Circuits and Timing Waveforms (Continued) DS011458-15 FIGURE 11. T/R to Bn (tPHLand tPLH only), T/R to An (tPZLand tPLZ only) 9 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Note: All dimensions in inches (millimeters) 44-Lead Molded Plastic Leaded Chip Carrier Order Number DS3886AV NS Package Number V44A www.national.com 10 DS3886A BTL 9-Bit Latching Data Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Note: All dimensions in millimeters 44-Lead Plastic Quad Flatpak Order Number DS3886AVF NS Package Number VF44B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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