MM54HC195/MM74HC195 4-Bit Parallel Shift Register General Description trol input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truth table. The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. The MM54HC195/MM74HC195 is a high speed 4-bit SHIFT REGISTER utilizes advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads at LS type speeds. This shift register features parallel inputs, parallel outputs, JK serial inputs, SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in two modes: PARALLEL LOAD; SHIFT from QA towards QD. Parallel loading is accomplished by applying the four bits of data, and taking the SHIFT/LOAD control input low. The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the SHIFT/LOAD con- Features Y Y Y Y Y Y Typical operating frequency: 45 MHz Typical propagation delay: 16 ns (clock to Q) Wide operating supply voltage range: 2 – 6V Low input current: 1 mA maximum Low quiescent current: 80 mA maximum (74HC Series) Fanout of 10 LS-TTL loads Connection Diagram Dual-In-Line Package TL/F/5324 – 1 Top View Order Number MM54HC195 or MM74HC195 Function Table Inputs Clear Shift/ Clock Load L H H H H H H X L H H H H H X u L u u u u Outputs Serial Parallel QC QD QD X L L L d a b c X QA0 QB0 QC0 X QA0 QA0 QBn X L QAn QBn X H QAn QBn X QAn QAn QBn L d QD0 QCn QCn QCn QCn H d QD0 QCn QCn QCn QCn J K A B C D X X X L L H H X X X H L H L X a X X X X X C1995 National Semiconductor Corporation X b X X X X X TL/F/5324 X c X X X X X QA QB H e high level (steady state) L e low level (steady state) X e irrelevant (any input, including transitions) e transition from low to high level a, b, c, d e the level of steady-state input at inputs A, B, C, or D, respectively. QA0, QB0, QC0, QD0 e the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn e the level of QA, QB, QC, respectively, before the most-recent transition of the clock. u RRD-B30M115/Printed in U. S. A. MM54HC195/MM74HC195 4-Bit Parallel Shift Register November 1995 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Typ Guaranteed Limit Units fMAX Symbol Maximum Operating Frequency Parameter Conditions 45 30 MHz tPHL, tPLH Maximum Propagation Delay, Clock to Q 14 24 ns tPHL Maximum Propagation Delay, Reset to Q 16 25 ns tREM Minimum Removal Time, Shift/Load to Clock 0 ns tREM Minimum Removal Time, Reset Inactive to Clock 5 ns tS Minimum Setup Time, (A, B, C, D, J, K to Clock) 20 ns tS Minimum Setup Time, Shift/Load to Clock 20 ns tW Minimum Pulse Width Clock or Reset 16 ns tH Minimum Hold Time, any Input except Shift/Load 0 ns AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C VCC Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits fMAX Maximum Operating Frequency 2.0V 4.5V 6.0V 10 45 50 6 30 35 5 24 28 4 20 24 MHz MHz MHz tPHL Maximum Propagation Delay, Reset to Q or Q 2.0V 4.5V 6.0V 70 15 12 150 30 26 189 38 32 224 45 38 ns ns ns tPHL, tPLH Maximum Propagation Delay, Clock to Q or Q 2.0V 4.5V 6.0V 70 15 12 145 29 25 183 37 31 216 43 37 ns ns ns tTHL, tTLH Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 30 8 7 75 15 13 95 19 16 110 22 19 ns ns ns tREM Minimum Removal Time, Shift Load to Clock 2.0V 4.5V 6.0V b2 b2 b2 0 0 0 0 0 0 0 0 0 ns ns ns tREM Minimum Removal Time, Reset Inactive to Clock 2.0V 4.5V 6.0V 5 5 5 5 5 5 5 5 5 ns ns ns tS Minimum Setup Time, (A, B, C, D, J, K to Clock) 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 25 ns ns ns tS Minimum Setup Time, Shift/Load to Clock 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time any Input except Shift/Load 2.0V 4.5V 6.0V b 10 b2 b2 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum Pulse Width, Clock or Reset 2.0V 4.5V 6.0V 30 10 9 80 16 14 100 20 18 120 24 20 ns ns ns tr, tf Maximum Input Rise and Fall Time 2.0V 4.5V 6.0V 1000 500 400 1000 500 400 1000 500 400 ns ns ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance 100 5 pF 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Logic and Timing Diagrams TL/F/5324 – 2 TL/F/5324 – 3 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC195J or MM74HC195J NS Package Number J16A 5 MM54HC195/MM74HC195 4-Bit Parallel Shift Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM74HC195N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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