MM54HC166/MM74HC166 8-Bit Parallel In/Serial Out Shift Registers General Description The MM54HC166/MM74HC166 high speed 8-BIT PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. These Parallel-In or Serial-In, Serial-Out shift registers feature gated CLOCK inputs and an overriding CLEAR input. The load mode is established by the SHIFT/LOAD input. When high, this input enables the SERIAL INPUT and couples the eight flip-flops for serial shifting with each clock pulse. When low, the PARALLEL INPUTS are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high level edge of the CLOCK pulse through a 2-input NOR gate, permitting one input to be used as a clock enable or CLOCK INHIBIT function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be Connection Diagram stopped on command with the other clock input. The CLOCK INHIBIT input should be changed to the high level only while the clock input is high. A direct CLEAR input overrides all other inputs, including the CLOCK, and sets all flipflops to zero. The 54HC/74HC logic family is functionally as well as pin out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and Ground. Features Y Y Y Y Y Typical propagation delay: Wide operating supply voltage range: 2V – 6V Low input current: k1 mA Low quiescent supply current: 80 mA maximum (74HC Series) Fanout of 10 LS-TTL loads Function Table Inputs Internal Output Shift/ Clock Parallel Outputs Clear Clock Serial QH Load Inhibit A...H QA QB Dual-In-Line Package L H H H H H X X L H H X X L L L L H X L u u u u X X X H L X X X a...h X X X L L QA0 QB0 a b H QAn L QAn QA0 QB0 L QH0 h QGn QGn QH0 H e High Level (steady state), L e Low Level (steady state) X e Don’t Care (any input, including transitions) u e Transition from low to high level a . . . h e The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 e The level of QA, QB, QH, respectively, before the indicated steady-state input conditions were established QAn, QGn e The level of QA, QG, respectively, before the most recent transition of the clock u TL/F/5770 – 1 Order Number MM54HC166 or MM74HC166 C1995 National Semiconductor Corporation TL/F/5770 RRD-B30M105/Printed in U. S. A. MM54HC166/MM74HC166 8-Bit Parallel In/Serial Out Shift Registers August 1989 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temp. Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr, tf) VCC e 2.0V VCC e 4.5V VCC e 6.0V b 0.5V to a 7.0V Supply Voltage (VCC) b 1.5V to VCC a 1.5V DC Input Voltage (VIN) b 0.5V to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per Pin (IOUT) g 50 mA DC VCC or GND Current, per Pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260§ C Min 2 Max 6 Units V 0 VCC V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C 74HC TA eb40§ C to a 85§ C Typ 54HC TA eb55§ C to a 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V IIN Maximum Input Current VIN e VCC or GND VCC e 2V – 6V 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA VCC e 2V – 6V 6.0V 8.0 80 160 mA Note 1: Absolute Maximum ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power dissipation temperature deratingÐplastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10%, the worst-case output voltages (VOH and VOL) occur for HC at 4.5V. Thus, the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC e 5.5V and 4.5V, respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns unless otherwise noted Symbol Parameter VCC 74HC TA eb40§ C to a 85§ C TA e 25§ C Typ fMAX Maximum Operating Frequency 2.0V 4.5V 6.0V tPHL/ tPLH Maximum Propagation Delay Clock to QH 2.0V 4.5V 6.0V tPHL/ tPLH Maximum Propagation Delay Clear to Qh 2.0V 4.5V 6.0V tsu Minimum Setup Time Shift/Load to Clock tsu 54HC TA eb55§ C to a 125§ C Units Guaranteed Limits 6 31 36 5 25 29 4.2 21 25 MHz MHz MHz 14 140 28 24 175 35 30 210 42 36 ns ns ns 11 130 26 22 165 35 30 195 39 33 ns ns ns 2.0V 4.5V 6.0V 80 16 14 100 20 18 120 24 20 ns ns ns Minimum Setup Time Data before Clock 2.0V 4.5V 6.0V 80 16 14 100 20 18 120 24 20 ns ns ns tREM Minimum Removal Time Clear to Clock 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns th Maximum Hold Time Data after Clock 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns tr, tf Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 75 15 13 95 19 16 110 22 19 ns ns ns tw Minimum Pulse Width Clock or Clear 2.0V 4.5V 6.0V 80 16 14 100 20 16 120 24 20 ns ns ns Cpd Power Dissipation Capacitance (Note 5) (per package) 100 Cin Maximum Input Capacitance 7 5 10 pF 10 10 pF AC Electrical Characteristics VCC e 5V, CL e 15 pF, TA e 25§ C, tr e tf e 6 ns unless otherwise noted Guaranteed Limits Units fMAX Symbol Maximum Operating Frequency Parameter Typical 31 MHz tPHL/ tPLH Maximum Propagation Delay Clock to Qh 16 ns tPHL/ tPLH Maximum Propagation Delay Clear to Qh 12 ns tsu Minimum Setup Time Shift/Load High to Clock 16 tsu Minimum Setup Time Data before Clock 16 ns tREM Minimum Removal Time Clear to Clock 0 ns th Maximum Hold Time Data after Clock 0 ns tw Minimum Pulse Width Clock or Clear 16 ns ns Note 5: Cpd determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 TL/F/5770 – 2 Logic Diagram 4 Logic Diagram Typical Clear, Shift, Load, Inhibit and Shift Sequences TL/F/5770 – 3 5 MM54HC166/MM74HC166 8-Bit Parallel In/Serial Out Shift Registers Physical Dimensions inches (millimeters) Order Number MM54HC166 or MM74HC166 NS Package Number M16A Order Number MM54HC166 or MM74HC166 NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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