ICHAUS IC-HC

iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
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FEATURES
APPLICATIONS
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦ Receiver for 24 V control
systems
♦ A/D and D/A converters
♦ Signal conditioning
♦ Zero-crossing detectors
♦ I/Os, level shift
♦ Timing critical measurement
equipment
♦ Time-to-digital converter
interfaces (TDC)
Independent input supply voltage range up to 36 V
Input voltage range down to VN
Differential input voltage of 36 V max.
Separate digital supply
Programmable hysteresis resp. hold function
Propagation delay typ. 5 ns
Power save mode with propagation delay of typ. 20 ns
Low current consumption stand-by mode
TTL and CMOS compatible logic inputs and outputs
8 mA CMOS outputs
Digital supply 3 to 5.5 V
All pins protected against ESD
PACKAGES
TSSOP16
BLOCK DIAGRAM
IN0
1
IP0
2
VP
3
T0
4
+
HYS
16
O0
15
NFAST
14
VDD
13
P0
HOLD
Copyright © 2013 iC-Haus
T1
5
12
P1
VN
6
11
GND
IP1
7
10
NEN
IN1
8
9
O1
Slow
+
-
Fast
http://www.ichaus.com
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iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
Rev A1, Page 2/10
DESCRIPTION
iC-HC features separate supply voltages for both the
analogue inputs and the logic outputs. The logic
power supply though must stay inside the boundaries
of the inputs power supply.
The iC also features a zero current consumption
standby mode as well as a current saving mode,
the latter reducing the current consumption by 80%,
though tripling the propagation delay.
Four values of input hysteresis (17 to 100 mV) or alternatively a hold function can be configured. The
hold function blocks the toggling of the output for the
configured hold time. For hold times > 100 µs external R/C networks can be used. Both hysteresis and
hold function can be deactivated.
PACKAGING INFORMATION TSSOP16 to JEDEC
PIN CONFIGURATION TSSOP16
IN0
1
IP0
2
VP
3
T0
4
+
HYS
PIN FUNCTIONS
No. Name Function
16
O0
15
NFAST
14
VDD
13
P0
HOLD
T1
5
12
P1
VN
6
11
GND
IP1
7
10
NEN
IN1
8
9
O1
Slow
+
-
Fast
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN0
IP0
VP
T0
T1
VN
IP1
IN1
O1
NEN
GND
P1
P0
VDD
NFAST
O0
Neg. Input Comparator 0
Pos. Input Comparator 0
Pos. Power Supply
Configuration Input / ext. RC
Configuration input / ext. RC
Neg. Power Supply
Pos. Input Comparator 1
Neg. Input Comparator 1
Output Comparator 1
Standby (NEN = hi)
Logic Ground
Configuration Input
Configuration Input
Logic Power Supply 5/3.3 V
Power Save (NFAST = hi)
Output Comparator 0
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ULTRA FAST DUAL HV-KOMPARATOR
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ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
G001 VP
Pos. Supply Voltage
G002 I(VP)
Current in VP
G003 V()
V(IPx), V(INx)
G004 I()
I(IPx), I(INx)
G005 VDD
Voltage at VDD
G006 VDD
Logic Supply VDD
G007 I(VDD)
Conditions
Unit
Min.
Max.
-0.5
46
V
-5
5
mA
VN − 0.5 VP + 0.5
V
-2
+2
mA
referenced to VN
-0.5
46
V
referenced to GND
-0.5
6
V
Current in VDD
referenced to GND
-5
20
mA
G008 I(VDD)
Current in VDD
referenced to VN
-5
5
mA
G009 GND
Voltage at GND
referenced to VN
-0.5
46
V
G010 I(GND)
Current in GND
referenced to VN
-5
5
mA
G011 V()
Voltage at output O0 and O1
referenced to GND
-0.5
6
V
G012 I()
Current in output O0 and O1
referenced to GND
-20
+20
mA
G013 I()
Current in iutput O0 and O1
referenced to VN
mA
G014 V()
V(NFAST,NEN,T0,T1,P0,P1)
referenced to GND
G015 I()
I(NFAST,NEN,T0,T1,P0,P1)
G016 Vd()
Susceptibility to ESD at all pins
G017 Ts
G018 Tj
-5
+5
-0.5
6
V
-5
+5
mA
3
kV
Storage Temperature Range
-40
150
°C
Chip Temperature
-40
150
°C
HBM, 100 pF discharged through 1.5 kΩ
THERMAL DATA
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
T01
Ta
Operating Ambient Temperature Range
T02
Rthja
Thermal Resistance Chip/Ambient
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
-40
Typ.
Max.
125
°C
140
K/W
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ELECTRICAL CHARACTERISTICS
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001
VDIFF
Differential Supply Voltage
VP − VN, VDD ≤ VP − 4 V
7
36
V
002
VP
Pos. Supply Voltage
VN = GND, VDD ≤ VP − 4 V
7
36
V
003
004
VN
Neg. Supply Voltage
VP = 9 V, VDD = 5 V
-27
0
V
I(VP)a
VP Current Consumption, active NEN = lo;
NFAST = lo
NFAST = hi
7.4
0.8
12
1.5
mA
mA
0
10
µA
005
I(VP)p
VP Current Consumption, passive
NEN = open (hi), NFAST = open (hi)
006
I(VN)a
VN Current Consumption, active NEN = lo;
NFAST = lo
NFAST = hi
-8.5
-1
-5.5
-0.55
mA
mA
0
µA
007
I(VN)p
VN Current Consumption, passive
NEN = open (hi)
-10
008
VDD
Logic Supply
VDD = VP − 4 V
3
009
I(VDD)p
VDD Current Consumption, pas- NEN open (hi), NFAST open (hi)
sive
010
I(VDD)a
VDD Current Consumption, active
Vs()hi
Vs()hi
5.5
V
0
10
µA
V(NEN) = lo
0.78
2.3
mA
Saturation Voltage hi
Vs()hi = VDD − V(), I() = -3.2 mA
0.1
0.2
V
Saturation Voltage hi
Vs()hi = VDD − V(), I() = -8 mA;
VDD = 3 V
VDD = 4.5 V
0.25
0.2
0.5
0.4
V
V
Outputs O0, O1
101
102
103
104
Vs()lo
Saturation Voltage lo
I() = 3.2 mA
0.12
0.25
V
Vs()lo
Saturation Voltage lo
I() = 8 mA;
VDD = 3 V
VDD = 4.5 V
0.35
0.3
0.7
0.6
V
V
2.4
1.7
V
V
Logic Inputs NFAST, NEN
201 Vt()hi
Threshold Voltage hi
VDD = 5.5 V
VDD = 3 V
202
Vt()lo
Threshold Voltage lo
203
Vhys()
Input Hysteresis
10
90
250
mV
204
Rpu()
Pull-Up Resistor at NFAST, NEN
referenced to VDD
35
50
70
kΩ
205
Rpd()
Pull-Down Resistor at T0, T1, P0,
P1 referenced to GND
35
50
70
kΩ
VDD = 5.5 V
VDD = 3 V
1.4
0.8
V
V
Comparator Inputs INx, IPx
301
Vcm()fast
Input Voltage Range
NFAST = lo
VN −
0.1
VP − 5
V
302
Vcm()
Input Voltage Range
NFAST = hi
VN −
0.1
VP − 4
V
303
∆Vi()
Permissible Differential Input
Voltage
V(IPx) − V(INx)
-VDIFF
VDIFF
V
304
I()
Input Current at INx, IPx
I() = I(INx) + I(IPx);
NFAST = lo
NFAST = hi
50
1
150
4
µA
µA
0
30
mV
305
Vos
Offset VOltage
P0 = lo (no hysteresis)
306
Vhys0
Input Hysteresis symmetrical
P1 = P0 = T1 = T0 = lo
-30
34
mV
307
Vhys1
Input Hysteresis symmetrical
P1 = lo, P0 = hi, T1 = lo, T0 = hi
66
mV
308
Vhys2
Input Hysteresis symmetrical
P1 = lo, P0 = T1 = hi, T0 = lo
110
mV
309
Vhys3
Input Hysteresis symmetrical
P1 = lo, P0 = hi, T1 = T0 = hi
200
310
tHoldint0
internal hold time
P1 = P0 = lo, T1 = lo, T0 = hi
0.6
1
1.6
µs
311
tHoldint1
internal hold time
P1 = P0 = lo, T1 = hi, T0 = lo
6
10
16
µs
mV
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ELECTRICAL CHARACTERISTICS
Item
No.
Symbol
Parameter
Conditions
312
tHoldint2
internal hold time
P1 = P0 = lo, T1 = T0 = hi
313
tHold
external hold time
P1 = P0 = hi, T0 (T1): ext. RC network with R
referenced to VDD and C referenced to GND or
VDD
Dynamic Parameters
401 tp
Propagation Delay Ix → Ox
402
∆tp
Propagation Delay Difference
Unit
Min.
Typ.
60
100
160
µs
0.7 *
RC
RC
1.2 *
RC
ms
9
11
20
20
20
50
ns
ns
ns
25
70
%
%
|∆Vi()| > 200 mV + Vhys in 0.5 ns, NFAST = lo;
VDD = 5 V
VDD = 3 V
NFAST = hi
tp(Ox lo → hi) − tp(Ox hi → lo),
symmetrical input signal;
NFAST = lo
NFAST = hi
-25
-70
Max.
403
trf()
Rise and Fall Time at O0, O1
Cl = 10 pF, Rl = 10 kΩ, VDD = 5 V,
10 % ↔ 90 %
1
2
ns
404
tpmin
Minimum Pulse Duration
NFAST = lo, VDD = 5 V
NFAST = lo, VDD = 3 V
NFAST = hi, VDD = 3 V
9
11
20
20
25
50
ns
ns
ns
Hold-Timer T0, T1
501
Rext
ext. resistor
P0 = P1 = hi, hold time = R * C,
Rext referenced to VDD
2
kΩ
502
Cext
ext. capacitor
P0 = P1 = hi, holdtime = R * C,
Cext referenced to GND or VDD
0
pF
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ULTRA FAST DUAL HV-KOMPARATOR
Rev A1, Page 6/10
DESCRIPTION OF FUNCTION
For noise suppression four symmetrical hysteresis settings can be configured as per Table 4.
VI(x)diff
time
VO(x)
P1 P0 T1
T0
Hys./Hold
0
0
0
0
no Hys./Hold
0
0
0
1
1 µs Hold
0
0
1
0
10 µs Hold
0
0
1
1
100 µs Hold
0
1
0
0
±17 mV Hys.
0
1
0
1
±33 mV Hys.
0
1
1
0
±55 mV Hys.
0
1
1
1
±100 mV Hys.
1
0
X
X
no Hys./Hold
1
1 R/C∗ R/C∗ Hold with ext. R/C
time
Figure 1: Switching characteristic without Hysteresis/Hold
VO(x)hys
time
VI(x)diff
+ Vhys
-
Table 4: Configuration
time
VO(x)hold
thold
thold
thold
Alternatively a hold function can be used for noise suppression: Following each falling or rising edge at the
outputs the toggling is blocked for the configured hold
time. With the hold time elapsed the output will follow
the input signal instantly. Table 4 shows three pre-set
hold times. The hold function has the advantage over
the hysteresis, that it does not shift the input switching threshold. With the aid of the hold function even
extreme interferences like e.g. "bouncing" can be completely blanked. Figure 3 shows a respective example
of a zero-crossing detector.
thold
thold
time
Figure 2: Switching characteristic with hysteresis
resp. hold function
VI(x)diff
time
VO(x)
hysteresis too small,
no hold function
time
VO(x)hold
Three hold times are pre-configured and can be chosen according to Table 4 without external circuitry. For
different hold times external R/C networks can be used
at T0 and T1 (P0 and P1 = hi)). Both hold timers work
independently, so individual hold times can be chosen.
∗
external R/C network
with hold function
thold
thold
thold
thold
time
Figure 3: Blanking of noise using the hold function
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ULTRA FAST DUAL HV-KOMPARATOR
Rev A1, Page 7/10
Hold function with external R/C network
Using external R/C networks at TO and T1 results in
signals as shown in Figure 5. The threshold is set to
2/3 VDD, hence the hold time is calculated using τ to
thold = Rext * Cext. The discharging is accomplished
via ca. 25 Ω and hence neglible, since the ext. resistor
(vs. VDD) may not be smaller than 2 kΩ. The hold time
for comparator 0 is set by R0 and C0, whereas R1 and
C1 set the hold time for comparator 1.
VI(x)diff
time
V(Tx)
VDD
2/ VDD
3
time
GND
VP
R0
T0
3
4
C0
R1
14
HYS
13
VDD
P0
(int.)
P1
VO(x)hold
HOLD
T1
5
12
HoldTimer
thold
thold
time
thold = Rext * Cext
C1
time
Figure 4: R/C network connection
EVALUATION BOARD
For the iC-HC an Evaluation Board is available for test
purposes. The following figures show the schematic
diagram and the component side of the test PCB.
Figure 5: Signals at T0 (T1) with ext. R/C network
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ULTRA FAST DUAL HV-KOMPARATOR
Rev A1, Page 8/10
VP
VP
VDD
VDD
C4
1μF
C5
opt
C2
opt
C7
opt
GND1
14
3
VPVDD
U1-S
iC-HC
VN GND
6
11
C6
1μF
GND
C3
opt
VN
VN
VDD
VDD
VDD
R1
JP4
T1
1
JP6
0
VDD
1
P1
0
C1
VDD
VDD
R0
JP3
T0
JP5
1
0
1
P0
0
C0
NFAST
JP2
FAST
NEN
JP1
ON
VP
R2
IN1
VN
TPI1
R3
VP
VN
IP1
TPIN1
VN
VP
R5
VN
IN0
TPIP1
R4
R6
VN
10
15
12
13
5
4
8
7
1
2
VN
VN
U1-A
iC-HC
NEN
NFAST
P1
P0
T1
T0
IN1
IP1
IN0
IP0
O1
TPO1
TP_O1
O1
O0
9
16
TPI0
R7
VP
TPIN0
VN
IP0
TPIP0
R8
TP_O0
VN
R9
VN
O0
TPO0
VN
VN
Figure 6: Schematic of the evaluation board
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Figure 7: Evaluation board (component side)
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
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ORDERING INFORMATION
Type
Package
Order Designation
iC-HC
iC-HC
TSSOP16
Evaluation Board
iC-HC TSSOP16
iC-HC EVAL HC1D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners