IS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS 64K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV6416DALL/DBLL) • High-speed access time: 8, 10, 12, 20 ns • Low Active Power: 135 mW (typical) • Low Standby Power: 12 µW (typical) CMOS standby LOW POWER: (IS61/64WV6416DALS/DBLS) • High-speed access time: 25, 35 ns • Low Active Power: 55 mW (typical) • Low Standby Power: 12 µW (typical) CMOS standby • Single power supply — Vdd 1.65V to 2.2V (IS61WV6416DAxx) — Vdd 2.4V to 3.6V (IS61/64WV6416DBxx) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available JANUARY 2011 DESCRIPTION The ISSI IS61WV6416DAxx/DBxx and IS64WV6416DBxx are high-speed, 1,048,576-bit static RAMs organized as 65,536 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV6416DAxx/DBxx and IS64WV6416DBxx are packaged in the JEDEC standard 44-pin TSOP Type II, 44-pin 400-mil SOJ and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 64K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE UB LB CONTROL CIRCUIT Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 1 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X High-Z High-Z Output Disabled H L H X X High-Z High-Z X L X H H High-Z High-Z Read H L L L H Dout High-Z H L L H L High-Z Dout H L L L LDoutDout Write L L X L H Din High-Z L L X H L High-Z Din L L X L LDinDin Vdd Current Isb1, Isb2 Icc Icc Icc PIN CONFIGURATIONS 44-Pin TSOP-II A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC A0-A15 I/O0-I/O15 CE OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 GND F I/O14 I/O13 A14 A15 I/O5 1 44-Pin SOJ (K) I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC A15 1 44 A0 A14 2 43 A1 A13 3 42 A2 A12 4 41 OE A11 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 GND GND 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A10 18 27 A3 A9 19 26 A4 A8 20 25 A5 A7 21 24 A6 NC 22 23 NC 2 3 4 5 6 7 8 PIN DESCRIPTIONS A0-A15 I/O0-I/O15 CE OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 3 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –4.0 mA Vdd = Min., Iol = 8.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 2.4 — 2 –0.3 –1 –1 Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Max. — 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions Vdd = Min., Ioh = –1.0 mA Vdd = Min., Iol = 1.0 mA GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.8 — 2.0 –0.3 –1 –1 Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Vdd Ioh = -0.1 mA 1.65-2.2V Iol = 0.1 mA 1.65-2.2V 1.65-2.2V 1.65-2.2V GND ≤ Vin ≤ Vdd GND ≤ Vout ≤ Vdd, Outputs Disabled Min. 1.4 — 1.4 –0.2 –1 –1 Max. — 0.2 Vdd + 0.2 0.4 1 1 Unit V V V V µA µA Note: 1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS 1 AC TEST CONDITIONS Parameter Unit Unit (2.4V-3.6V) (3.3V + 5%) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD + 0.05 and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 1909 317 R2 ( Ω ) 1105 351 Vtm (V) 3.0V 3.3V Unit (1.65V-2.2V) 0.4V to Vdd - 0.3V 1V/ ns 0.9V 2 3 See Figures 1 and 2 13500 10800 1.8V 4 5 AC TEST LOADS R1 ZO = 50Ω 6 VTM 50Ω VDD/2 OUTPUT 30 pF Including jig and scope Figure 1. OUTPUT 5 pF Including jig and scope 7 R2 8 Figure 2. 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 5 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value –0.5 to Vdd + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS HIGH SPEED (IS61WV6416DALL/DBLL) 1 OPERATING RANGE (Vdd) (IS61WV6416DALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 20ns 20ns 20ns 2 3 OPERATING RANGE (Vdd) (IS61WV6416DBLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (8 ns)1 3.3V + 5% 3.3V + 5% Vdd (10 ns)1 2.4V-3.6V 2.4V-3.6V 4 Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. 5 OPERATING RANGE (Vdd) (IS64WV6416DBLL) Range Ambient Temperature Automotive –40°C to +125°C Vdd (10 ns) 2.4V-3.6V 6 7 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Icc Vdd Dynamic Operating Vdd = Max., Com. Supply Current Iout = 0 mA, f = fmax Ind. CE = Vil Auto.(3) Vin ≥ Vdd – 0.3V, or typ.(2) Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. Vin ≥ Vdd – 0.2V, or Auto. Vin ≤ 0.2V, f = 0 typ.(2) -8 -10 Min. Max. Min. Max. — 65 — 50 — 70 — 55 — — — 65 45 45 — — — 4 40 — 55 — — — 4 40 55 90 -12 Min. Max. — 45 — 50 — 55 45 -20 Min. Max. — 40 — 45 — 50 — 40 — 55 — 90 4 — 40 — 55 — 90 8 Unit mA 9 10 µA 11 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 12 7 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS LOW POWER (IS61WV6416DALS/DBLS) OPERATING RANGE (Vdd) (IS61WV6416DALS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C Vdd 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns 55ns OPERATING RANGE (Vdd) (IS61WV6416DBLS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Vdd (35 ns) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (Vdd) (IS64WV6416DBLS) Range Ambient Temperature Automotive –40°C to +125°C Vdd (35 ns) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -25 Symbol Parameter Test Conditions Min. Max. Icc Vdd Dynamic Operating Vdd = Max., Com. — 20 Supply Current Iout = 0 mA, f = fmax Ind. — 25 CE = Vil Auto. — 40 Vin ≥ Vdd – 0.3V, or typ.(2) 18 Vin ≤ 0.4V Isb2 CMOS Standby Vdd = Max., Com. — 40 Ind. — 50 Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Vin ≥ Vdd – 0.2V, or Auto. — 75 Vin ≤ 0.2V, f = 0 typ.(2) 4 -35 Min. Max. — 20 — 25 — 35 — 40 — 50 — 75 -45 Min. Max. — 18 — 20 — 30 — 40 — 50 — 75 Unit mA µA Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS 1 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter trc Read Cycle Time taa Address Access Time toha Output Hold Time tace CE Access Time tdoe OE Access Time (2) thzoe OE to High-Z Output tlzoe(2) OE to Low-Z Output thzce(2 CE to High-Z Output tlzce(2) CE to Low-Z Output tba LB, UB Access Time thzb(2) LB, UB to High-Z Output tlzb(2) LB, UB to Low-Z Output tpu Power Up Time tpd Power Down Time -8 Min. Max. 8 — — 8 2.0 — — 8 — 5.5 — 3 0 — 0 3 3 — — 5.5 0 5.5 0 — 0 — — 8 -10 Min. Max. 10 — — 10 2.0 — — 10 — 6.5 — 4 0 — 0 4 3 — — 6.5 0 6.5 0 — 0 — — 10 -12 Min. Max. 12 — — 12 3 — — 12 — 6.5 — 6 0 — 0 6 3 — — 6.5 0 6.5 0 — 0 — — 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 3 4 5 Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 9 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toha tace tdoe thzoe(2) tlzoe(2) thzce(2 tlzce(2) tba thzb tlzb Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -20 ns -25 ns Min.Max. Min. Max. 20 — 25 — — 20 — 25 2.5 — 6 — — 20 — 25 — 8 — 12 0 8 0 8 0 — 0 — 0 8 0 8 3 — 10 — — 8 0 8 0 — — 25 0 8 0 — - 35 ns -45 ns Min.Max. Min. Max. 35 — 45 — — 35 — 45 8 — 10 — — 35 — 45 — 15 — 20 0 10 0 15 0 — 0 — 0 10 0 15 10 — 10 — — 35 0 10 0 — — 0 0 45 15 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS 1 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB and/or LB = Vil) 2 t RC ADDRESS t OHA DOUT t AA 3 t OHA DATA VALID PREVIOUS DATA VALID 4 READ1.eps 5 READ CYCLE NO. 2 (1,3) 6 tRC ADDRESS tAA tOHA 7 OE tHZOE tDOE tLZOE CE tACE tLZCE 8 tHZCE LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC 9 DATA VALID tPU 50% tPD 50% ICC 10 ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB and/or LB = Vil. 3. Address is valid prior to or coincident with CE LOW transition. 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 11 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol twc tsce taw tha tsa tpwb tpwe1 tpwe2 tsd thd thzwe(2) tlzwe(2) Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -8 Min. Max. 8 — 6.5 — 6.5 — 0 0 6.5 6.5 8.0 5 0 — 2 — — — — — — — 3.5 — -10 Min. Max. 10 — 8 — 8 — 0 0 8 8 10 6 0 — 2 — — — — — — — 5 — -12 Min. Max. 12 — 9 — 9 — 0 0 9 9 11 9 0 — 3 — — — — — — — 6 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc tsce taw tha tsa tpwb tpwe1 tpwe2 tsd thd thzwe(3) tlzwe(3) -20 ns-25 ns-35 ns-45ns Parameter Min. Max. Min. Max. Min.Max. Min. Max. Write Cycle Time 20 — 25 — 35 — 45 — CE to Write End 12 — 18 — 25 — 35 — Address Setup Time 12 — 15 — 25 — 35 — to Write End Address Hold from Write End 0 — 0 — 0 — 0 — Address Setup Time 0 — 0 — 0 — 0 — LB, UB Valid to End of Write 12 — 18 — 30 — 35 — WE Pulse Width (OE = HIGH) 12 — 18 — 30 — 35 — WE Pulse Width (OE = LOW) 17 — 20 — 30 — 35 — Data Setup to Write End 9 — 12 — 15 — 20 — Data Hold from Write End 0 — 0 — 0 — 0 — WE LOW to High-Z Output — 9 — 12 — 20 — 20 WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 2 3 4 Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 13 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PWB UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PWB UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR2.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS 1 AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) 2 t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW 3 t PWE2 4 WE t SA t PWB UB, LB t HZWE DOUT t LZWE 5 HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR3.eps 6 7 WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS 8 t WC ADDRESS 1 ADDRESS 2 OE 9 t SA CE LOW t HA t SA WE UB, LB t HA t PWB t PWB WORD 1 WORD 2 t HZWE DOUT HIGH-Z DATA UNDEFINED t HD t SD DIN 10 t LZWE DATAIN VALID 11 t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 15 12 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS HIGH SPEED (IS61WV6416DALL/DBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. Options Com. Ind. Auto. Min. 2.0 — — 0 trc Typ.(1) — 4 — — — Max. 3.6 40 55 90 — — Unit V µA Min. 1.2 — — — 0 trc Typ.(1) — 4 — — — — Max. 3.6 40 55 90 — — Unit V µA ns ns o DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested. Options Com. Ind. Auto. ns ns o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS LOW POWER (IS61WV6416DALS/DBLS) 1 DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. Options Com. Ind. Auto. Min. 2.0 — — 0 trc Typ.(1) — 4 — — — Max. 3.6 40 50 75 — — Unit V µA 2 3 ns ns o 4 DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition Vdr Vdd for Data Retention See Data Retention Waveform Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested. Options Com. Ind. Auto. Min. 1.2 — — — 0 trc Typ.(1) — 4 — — — — Max. 3.6 40 50 75 — — 5 Unit V µA 6 ns ns 7 o 8 DATA RETENTION WAVEFORM (CE Controlled) 9 tSDR tRDR VDD 10 VDR 11 CE GND Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 Data Retention Mode CE ≥ VDD - 0.2V 12 17 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS ORDERING INFORMATION (HIGH SPEED) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V peed (ns) S 8 10 Order Part No. IS61WV6416DBLL-8BI IS61WV6416DBLL-8BLI IS61WV6416DBLL-8TI IS61WV6416DBLL-8TLI IS61WV6416DBLL-8KI IS61WV6416DBLL-8KLI IS61WV6416DBLL-10BI IS61WV6416DBLL-10BLI IS61WV6416DBLL-10TI IS61WV6416DBLL-10TLI IS61WV6416DBLL-10KI IS61WV6416DBLL-10KLI Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free 400-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free 400-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V peed (ns) S 20 Order Part No. IS61WV6416DALL-20BLI IS61WV6416DALL-20TLI Package 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V peed (ns) S 10 Order Part No. IS64WV6416DBLL-10BA3 IS64WV6416DBLL-10BLA3 IS64WV6416DBLL-10CTA3 IS64WV6416DBLL-10CTLA3 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe ORDERING INFORMATION (LOW POWER - IN EVALUATION) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V peed (ns) S 35 18 Order Part No. Package IS61WV6416DBLS-35TLI TSOP (Type II), Lead-free Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 Θ Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS 1 2 3 4 5 6 7 8 9 10 11 12 19 20 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 11/18/2010 SEATING PLANE 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS-027. 3. Dimension b2 does not include dambar protrusion/intrusion. 2. Dimension D and E1 do not include mold protrusion . 1. Controlling dimension : mm NOTE : 12/21/2007 IS61WV6416DALL/DALS, IS61WV6416DBLL/DBLS, IS64WV6416DBLL/DBLS 1 2 3 4 5 6 7 8 9 10 11 12 21