IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS 512K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access times: 8, 10, 20 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply VDD 1.65V to 2.2V (IS61WV51232Axx) speed = 20ns for VDD 1.65V to 2.2V VDD 2.4V to 3.6V (IS61/64WV51232Bxx) speed = 10ns for VDD 2.4V to 3.6V speed = 8ns for VDD 3.3V + 5% • Packages available: – 90-ball miniBGA (8mm x 13mm) • Industrial and Automotive Temperature Support • Lead-free available PRELIMINARY INFORMATION APRIL 2008 DESCRIPTION The ISSI IS61WV51232Axx/Bxx and IS64WV51232Bxx are high-speed, 16M-bit static RAMs organized as 512K words by 32 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The device is packaged in the JEDEC standard 90-ball BGA (8mm x 13mm). FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 32 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD VSS DQa-d CE OE WE CONTROL CIRCUIT BWa-d CE2 Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 1 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS PIN CONFIGURATION PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch) 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L M N P R DQ1 DQ0 VSS VDD DQ31 DQ30 DQ2 VDD VSS VDD VSS DQ3 DQ4 DQ27 DQ28 VDD VSS DQ6 DQ5 DQ26 DQ25 VDD VSS DQ29 VDD DQ7 NC NC DQ24 VSS VSS BWa A3 A4 BWd VDD A0 A1 A2 A10 A5 A6 A15 A14 A13 A8 A7 A11 CE2 A17 A16 A9 A12 CE BWb NC A18 OE WE BWc VDD DQ8 VSS VDD DQ23 VSS VSS DQ9 DQ10 DQ21 DQ22 VDD VSS DQ12 DQ11 DQ20 DQ19 VDD DQ13 VDD VSS VDD VSS DQ18 DQ14 DQ15 VSS VDD DQ16 DQ17 PIN DESCRIPTIONS 2 A0-A18 Address Inputs DQx Data I/O CE, CE2 Chip Enable Input OE Output Enable Input WE Write Enable Input BWx (x=a-d) Byte Write Control VDD Power Vss Ground NC No Connection Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS TRUTH TABLE CE CE2 OE WE BWa BWb BWc BWd H X L L X L H H X X L L X X H H X X L L X X L H X X L H X X L H L H L H H L H H High-Z Data Out High-Z High-Z L H L H H H L H High-Z High-Z Data Out High-Z L H L H H H H L High-Z High-Z High-Z Data Out L L H H X X L L L L L H L H L H Data In Data In Data In High-Z Data In High-Z Data In High-Z L H X L H L H H High-Z Data In High-Z High-Z L H X L H H L H High-Z High-Z Data In High-Z L H X L H H H L High-Z High-Z High-Z Data In L H H H X X X X High-Z High-Z High-Z High-Z DQ0-7 DQ8-15 DQ16-23 DQ24-31 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out Data Out Data Out Data Out High-Z High-Z High-Z Mode Power Power Down Power Down Read All Bits Read Byte a Bits Only Read Byte b Bits Only Read Byte c Bits Only Read Byte d Bits Only Write All Bits Write Byte a Bits Only Write Byte b Bits Only Write Byte c Bits Only Write Byte d Bits Only Selected, Outputs Disabled (ISB) (ISB) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 3 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage VIL Input LOW Voltage(1) 2 VDD + 0.3 V –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Min. Max. Unit Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol Parameter Test Conditions VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 1.8 — V VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V VIH VIL(1) Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V Input LOW Voltage 1.65-2.2V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Notes: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width -2.0ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width -2.0ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS HIGH SPEED OPERATING RANGE (VDD) (IS61WV51232ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 20ns 20ns 20ns OPERATING RANGE (VDD) (IS61WV51232BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (8 nS)1 3.3V + 5% 3.3V + 5% VDD (10 nS)1 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (VDD) (IS64WV51232BLL) Range Automotive Ambient Temperature –40°C to +125°C VDD (10 nS) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter ICC ICC1 VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Min. Max. Com. Ind. Auto. typ.(2) — — — 110 115 — -10 Min. Max. — — — -20 Min. Max. Unit 90 95 140 — — — 50 60 100 mA 60 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 Com. Ind. Auto. — — — 85 90 — — — — 85 90 110 — — — 45 55 90 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. Auto. — — — 30 35 — — — — 30 35 70 — — — 30 35 70 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 20 25 — — — — 20 25 60 — — — 20 25 60 mA 4 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 5 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS LOW POWER OPERATING RANGE (VDD) (IS61WV51232ALS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 35ns 35ns 35ns OPERATING RANGE (VDD) (IS61WV51232BLS)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (25 nS)1 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in the range of 3.3V + 5%, the device meets 20ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions ICC VDD = Max., IOUT = 0 mA, f = fMAX VDD Dynamic Operating Supply Current Min. Com. Ind. Auto. typ.(2) — — — -25 Max. -35 Min. Max. Unit 30 35 60 — — — 25 30 60 mA 25 ICC1 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 Com. Ind. Auto. — — — 20 30 50 — — — 20 30 50 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. Auto. — — — 15 20 40 — — — 15 20 40 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 0.8 1.2 2 — — — 0.8 1.2 2 mA 0.1 0.1 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to VDD-0.3V 1.5ns VDD/2 Unit (3.3V + 5%) 0.4V to VDD-0.3V 1.5ns VDD/2 + 0.05 Unit (1.65V-2.2V) 0.4V to VDD-0.2V 1.5ns VDD/2 See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 5 pF Including jig and scope 353 Ω Figure 2. 7 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tLZB tHZB Parameter -10 Min. Max. Min. Max. Unit Read Cycle Time 8 — 10 — ns Address Access Time — 8 — 10 ns Output Hold Time 2.5 — 2.5 — ns CE Access Time — 8 — 10 ns OE Access Time — 5.5 — 6.5 ns OE to High-Z Output — 3 — 4 ns OE to Low-Z Output 0 — 0 — ns CE to High-Z Output 0 3 0 4 ns CE to Low-Z Output 3 — 3 — ns Byte Enable to Data Valid — 5.5 — 6.5 ns Byte Enable to Low-Z 0 — 0 — ns Byte Enable to High-Z 0 3 0 3 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -20 ns Min. Max. Unit tRC Read Cycle Time 20 — ns tAA Address Access Time — 20 ns tOHA Output Hold Time 2.5 — ns tACE CE Access Time — 20 ns tDOE OE Access Time — 8 ns tHZOE(2) OE to High-Z Output 0 8 ns tLZOE OE to Low-Z Output 0 — ns (2 tHZCE CE to High-Z Output 0 8 ns (2) tLZCE tBA tLZB CE to Low-Z Output 3 — ns Byte Enable to Data Valid — 8 ns Byte Enable to Low-Z 0 — ns tHZB Byte Enable to High-Z 0 3 ns (2) Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 9 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t HZOE t DOE t BA BWa-d t HZB t LZB t LZOE t ACE CE t HZCE t LZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter -10 Min. Max. Min. Max. Unit tWC Write Cycle Time 8 — 10 — ns tSCE CE to Write End 6.5 — 8 — ns tAW Address Setup Time to Write End 6.5 — 8 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWB BWa-d Valid to End of Write 6.5 — 8 — ns tPWE1 WE Pulse Width 6.5 — 8 — ns tPWE2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns tSD Data Setup to Write End 5 — 6 — ns tHD Data Hold from Write End 0 — 0 — ns (2) tHZWE WE LOW to High-Z Output — 3.5 — 5 ns tLZWE(2) WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shadedareaproductindevelopment Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 11 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol Parameter -20 ns Min. Max. Unit tWC Write Cycle Time 20 — ns tSCE CE to Write End 12 — ns tAW Address Setup Time to Write End 12 — ns tHA Address Hold from Write End 0 — ns tSA Address Setup Time 0 — ns tPWB BWa-d Valid to End of Write 12 — ns tPWE1 WE Pulse Width (OE = HIGH) 12 — ns tPWE2 WE Pulse Width (OE = LOW) 17 — ns tSD Data Setup to Write End 9 — ns tHD Data Hold from Write End 0 — ns tHZWE(3) WE LOW to High-Z Output — 9 ns tLZWE(3) WE HIGH to Low-Z Output 3 — ns Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 13 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW BWa-d t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR2.eps WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW BWa-d t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR3.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS AC WAVEFORMS WRITE CYCLE NO. 4 (Byte Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE BWa-d t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the BWa-d pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 15 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61WV51232ALL/BLL) Symbol Parameter Test Condition Min. Max. Unit VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V — — 25 60 mA tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — ns Recovery Time See Data Retention Waveform tRC — ns Ind. Auto. DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD 1.65V 1.4V VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61WV51232ALS/BLS) Symbol Parameter Test Condition Min. Max. Unit VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V — — 1.2 2 mA tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — ns Recovery Time See Data Retention Waveform tRC — ns Ind. Auto. DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD 1.65V 1.4V VDR CE GND Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 CE ≥ VDD - 0.2V 17 IS61WV51232ALL/ALS IS61WV51232BLL/BLS IS64WV51232BLL/BLS ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 1 10 (8 ) Order Part No. Package IS61WV51232BLL-10BI IS61WV51232BLL-10BLI 90-ball BGA (8mm x 13mm) 90-ball BGA (8mm x 13mm), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V - 3.6V Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. Package IS61WV51232ALL-20BI 90-ball BGA (8mm x 13mm) Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 18 Order Part No. Package IS64WV51232BLL-10BA3 90-ball BGA (8mm x 13mm) Integrated Silicon Solution, Inc. — www.issi.com Rev. 00B 04/23/08 D1 0.80 Package Outline 0.45 NOTE : 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 08/14/2008