NJW1262 Analog Signal Input Class-D Amplifier for Piezo Speaker with DC-DC Converter Q GENERAL DESCRIPTION Q PACKAGE OUTLINE The NJW1262 is an analog signal input monaural class-D amplifier for Piezo speaker. And a built-in DC-DC converter generates fixed output voltage. Therefore, it realizes 7Vrms@1kHz output signal with louder sound and high efficiency. The NJW1262 incorporates BTL amplifier, which eliminate AC coupling capacitors, and it is capable of driving Piezo speaker with simple external LC low-pass filters. Class-D operation achieves lower power operation for Piezo speaker, thus the NJW1262 is suited for battery-powered applications. NJW1262NL2 Q FEATURES O Output Voltage VDD=3.0V to 4.2V VDDO=13.0V@SP MODE VDDO=4.5V@REC MODE O Analog Audio Signal Input O 2input selector (Speaker Mode and Receiver Mode) O 1-channel BTL Output, Piezo Speaker Driving O Built-in DC-DC Converter O Built-in Low Voltage Detector O Standby (Hi-Z), Soft Start, Soft Mute Control O Built-in Pop noise reduction O Built-in Short Protector) O Built-in Thermal Protection O Package Outline: EPCSP32 Q BLOCK DIAGRAM EQ1 VDD EQ2 VDDO VDD UVLO VDDO UVLO INSP INPREC OUTP Level Shifter Selector INNREC Pulse Width Modulator EQ3 OCP OUTN Level Shifter OSC BIAS TSD SW COM Pulse Width Modulator COM OCP STBYb CONTROL LOGIC SOFT MODE NJW1262Ver.4.0_E VSS OUTTEST VSSREG - ROSC1 ROSC2 FB IN- -1- NJW1262 Q PIN CONFIGURATION No. 23 28,29 11 7 6 12 13 14 5 19 SYMBOL VDD VDDO INSP INPREC INNREC EQ1 EQ2 EQ3 COM SOFT I/O − − I I I I/O I/O I/O I/O I/O 4 STBYb I 3 MODE I 22 10 26,31 ROSC1 ROSC2 VSS I/O I/O − Function Power supply:VDD =3.7 V Output Power supply:VDDO =13 V Noninverted signal input (SP Mode) terminal Noninverted signal input (REC Mode) terminal Inversion signal Input (REC Mode) LPF Setting terminal LPF Setting terminal LPF Setting terminal Bias terminal Capacitor connection terminal for soft start Standby control terminal (STBYb =L: Standby) SP/REC mode switch terminal (MODE =H: SP Mode, MODE =L: REC Mode) The mode maintains the logic when the STBYb terminal is started up. Class-D Amplifier Oscillator resistance connection terminal Switching Regulator Oscillator resistance connection terminal GND:VSS =0 V 30 27 OUTP OUTN O O Noninverted signal output terminal Inversion signal output terminal 2 OUTTEST O Test Pin (50kΩ ground) Should be floating or VSS fixation. 18 15 21 20 SW VSSREG INFB O − I/O I/O 8 TEST1 I Inductor connection terminal GND:VSSREG =0 V Phase compensating device connection terminal for switching regulator Phase compensating device connection terminal for switching regulator Test Pin (50kΩ ground) Should be floating or VSS fixation. NC pin Should be floating or VSS fixation. 1, 9,16,17, NC 24,25,32 Note: VBAT = VDD Note: Do not do floating the input terminal. VSS NC OUTN VDDO OUTp VDDO VSS NC Q TERMINAL CONFIGURATION 32 NC 25 1 24 ROSC1 STBYb IN- COM FB SOFT INNREC SW 8 17 -2- NC VSSREG EQ3 EQ2 EQ1 INSP 16 ROSC2 NC 9 NC INPREC TEST1 NC VDD OUTTEST MODE NJW1262Ver.4.0_E NJW1262 NJU3555 ■ INPUT TERMINAL Terminal Internal Circuit Vss NJW1262 Ver.4.0_E -3- NJW1262 Q ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage SYMBOL VDD VDDO Input Voltage VIN Operating Temperature Storage Temperature Topr Tstg PDMAX2 PDMAX4 θja2 θja4 Power Dissipation Thermal resistance CONDITIONS VDD VDDO INSP, INPREC, INNREC, STBYb, MODE, OUTTEST 2 layers (EIAJ), Tj = 125°C 4 layers (EIAJ), Tj = 125°C 2 layers (EIAJ), Tj = 125°C 4 layers (EIAJ), Tj = 125°C RATING -0.3 to +5.5 -0.3 to +36 (Ta=25°C) UNIT V -0.3 to VDD+0.3 V -40 to +85 -40 to +125 760 1800 132 54 °C °C mW mW °C /W °C /W Note 1) All voltage are relative to “VSS =0V” reference. Note 2) Power dissipation is a value in condition where it is mounted on 2-layer/ 4-layer board based on EIA/JEDEC. Note 3) The IC must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent damage to the LSI. Note 4) De-coupling capacitors must be connected between each power supply terminal and GND (VDD-VSS, VDDO-VSS). Note 5) The maximum power dissipation in the system is calculated, as shown below. TjMAX [°C] − Ta [°C] PDMAX = θ ja [°C / W ] Pdmax: Maximum Power Dissipation, Tjmax: Junction Temperature = 125°C Ta: Ambient Temperature, θja: Thermal Resistance of package = 132°C/W 125℃ − 50℃ PD = = 570[mW ] 132℃ / W -4- NJW1262Ver.4.0_E NJW1262 NJU3555 QELECTRICAL CHARACTERISTICS O DC Characteristics Ta = 25 °C,VDD = 3.7 V, VDDO = 13.0 V(SP Mode), VDDO = 4.5V (REC Mode), VSS = VSSREG = 0.0 V, Load= 1.5 µF, ROSC1= 82 kΩ, ROSC2= 82 kΩ, CLPF= 330 pF, Cc=0.033 µF, Output Filter: [LOUT= 22µH, RDAMP= 3.9 Ω] SW regulator: [LSW= 6.8µH, CSW= 20µF+ 0.1µF, Ccmpn1= 4.7 nF, Rcmpn= 68 kΩ] Input Signal :INSP= 100 mVrms, INPREC- INNREC =100 mVrms, Input Frequency= 1 kHz PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Supply Voltage VDD Boost voltage VSWSP VSWREC Output Driver On-state Resistance (High-side) Output Driver On-state Resistance (Low-side) Switching Regulator Output Driver On-state Resistance Input Impedance Operating Current (Standby) Operating Current (No signal input) RONHSP RONHREC RONLSP RONLREC RONSW 3.7 4.2 V 11.9 4.2 13 4.5 14.1 4.8 V V 1.3 2.0 2.4 Ω 1.3 2.2 2.8 Ω 1.3 2.0 2.4 Ω 1.3 2.2 2.8 Ω 0.05 0.4 0.7 Ω RINSP INSP 90 120 150 kΩ RINPREC INPREC 180 240 300 kΩ RINNREC INNREC 280 360 440 kΩ IST STBYb: "L",No Load SP Mode, Non-LC Filter, No Load REC Mode Non-LC Filter, No Load - - 1 µA - 11 14 mA - 4.0 5.0 mA IBATSP IBATREC NJW1262 Ver.4.0_E SP Mode REC Mode SP Mode, OUTP, OUTN VOUTP, N = VDDO - 0.1 V REC Mode, OUTP, OUTN VOUTP, N = VDD - 0.1 V SP Mode, OUTP, OUTN VOUTP, N = 0.1 V REC Mode, OUTP, OUTN VOUTP, N =0.1 V SW VSW = 0.1 V 3.0 -5- NJW1262 PARAMETER Input Voltage Input Leakage Current SW Off Leak Current OUTP Ground Resistance OUTN Ground Resistance Class-D Amplifier Oscillation Frequency Switching Regulator Oscillation Frequency Soft Start Resistance Soft Mute Resistance Start-up Time Stop Time Class-D Amplifier Voltage Gain SYMBOL VIH VIL ILK ILKSW ROUTP ROUTN CONDITIONS STBYb, MODE Pin STBYb, MODE Pin STBYb, MODE Pin SW Pin OUTP Pin OUTN Pin MIN. 1.5 0 70 70 TYP. 100 100 MAX. VDD 0.5 ±1 ±1 130 130 UNIT V V fOSCD 180 250 320 kHz fOSCSW 500 600 750 kHz 35 35 5.0 10 50 50 6.7 13.3 65 65 8.4 16.6 kΩ kΩ ms ms - 27.6 - dB - 5.1 - dB 10 50 - - µs µs -20 - 20 mV RSST RSMT TON TOFF AvSP AvREC MODE Setup Time MODE Holding Time TSTUP THLD Offset Voltage VOFFSET SOFT Pin SOFT Pin SP Mode, No Load CLPF=100 pF REC Mode, No Load CLPF=100 pF Refer to Figure 1. Refer to Figure 1. REC Mode 2ms After OUTP and OUTN pin start switching µA µA kΩ kΩ STBYb MODE TSTUP THLD Figure 1: STBYb/MODE input timing -6- NJW1262Ver.4.0_E NJW1262 NJU3555 O AC Characteristics Ta = 25 °C,VDD = 3.7 V, VDDO = 13.0 V(SP Mode), VDDO = 4.5V (REC Mode), VSS = VSSREG = 0.0 V, Load = 1.5 µF, ROSC1= 82 kΩ, ROSC2= 82 kΩ, CLPF= 330 pF, Cc=0.033 µF, Output Filter: [LOUT= 22µH, RDAMP= 3.9 Ω] SW regulator: [LSW= 6.8µH, CSW= 20µF+ 0.1µF, Ccmpn1= 4.7 nF, Rcmpn= 68 kΩ] Input Signal :INSP= 100 mVrms, INPREC- INNREC =100 mVrms, Input Frequency= 1 kHz PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT SP Mode, 0.2 % THD+NSP VOUTSP =2.5 Vrms THD+N REC Mode 0.08 % THD+NREC VOUTREC =1 Vrms SP Mode, 7 Vrms VOUTSP THD+N=2 % Maximum Output Voltage REC Mode, VOUTREC 2.7 Vrms THD+N=2 % REC MODE, 80 dB S/N SN VOUTREC =1 Vrms A-weight Noise Floor VN REC MODE, A-weight 100 µVrms Note) A noise by the Class-D amplifier oscillation frequency and the switching regulator oscillation frequency may be felt in receiver mode. Therefore, please test the circuit carefully to fit your application. NJW1262 Ver.4.0_E -7- NJW1262 Q FUNCTIONAL DESCRIPTION O Signal Input Terminal (INSP, INPREC, INNREC) Analog signal input. The input signal is selected by the operational mode. O Capacitor connection terminal for LPF (EQ1, EQ2, EQ3) The amount of current passing through a capacitive load increases proportionately with frequency of audio signal. Input filters should be put in the input line to reduce load current at high frequency-band. The input low pass filters are composed of feedback resister (R1) and capacitor (CLPF). Refer to the following expression. R1= 120kΩ, CLPF= 330pF 1 1 = ≒4.0[kHz] fLPF = 2πR1CLPF 2 × 3.14 × 120kΩ × 330pF R1=120[kΩ] Figure 2: Input LPF composition O Signal Output Terminal (OUTP, OUTN) The output signals are PWM signals, which will be converted to analog signal via external 2nd-order or higher LC filter. Should be connected to the damping resistor (RDAMP) between OUTP pin and coil, and between OUTN pin and coil to reduce the current consumption with signal-input close to cutoff-frequency of LPF (fc). Set the value of LOUT, CL, and RDAMP to become Q<1. Refer to the following expression. LOUT =22µH, CL=1.5µF, RDAMP=3.9Ω, Equivalent series resistance of L (RDCR) =0.8Ω fc = 1 2π 2L OUT CL Q= -8- = 1 RDAMP + RDCR 1 2 × 3.14 × 2 × 22µH × 1.5µF ≒19.6[kHz] L OUT 1 22µH ≒0.63 = × 2 × CL 3 .9 Ω + 0 .4 Ω 2 × 1.5µF NJW1262Ver.4.0_E NJW1262 NJU3555 O Standby Terminal (STBYb) By setting the STBYb pin to “L” level, it switches the NJW1262 into standby condition. During the standby condition, output pins (OUTP, OUTN, SW) become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. Keep the STBYb pin to “L” level at least 13.3ms once switched into the standby condition. For normal operation, the STBYb pin requires “H” level. Time from the standby release to class-D power amplifier operation is 6.7ms(TYP). Do not change to the standby mode until the power amplifier operation. Set the standby mode at power supply ON/OFF. O Capacitor connection terminal for soft start (SOFT) Capacitor connection terminal for soft start and soft mute. VDD RSFT RSFT=50[kΩ] CSFT=0.1[µF] SOFT SOFT START CIRCUIT RSFT CSFT VSS O Step-up switching regulator The switching regulator is used as power supply (VDDO) for power amplifier of class-D. The PWM controlled switching regulator works with external components, which are coil, capacitor, Schottky barrier diode. NJW1262 Ver.4.0_E -9- NJW1262 O Mode SP/REC mode selection terminal. The output power-supply voltage, the input selector, and the voltage gain change when the mode is switched. MODE= H :SP（Speaker）Mode Audio input terminal: INSP(Shingle end input) Class-D amplifier output power-supply voltage: Step-up switching regulator ⎛ R ⎞ VSWSP = 1.0V × ⎜⎜1 + 1 ⎟⎟ = 13.0V (TYP) ⎝ R2 SP ⎠ Voltage gain: 27.6 dB (TYP) MODE= L ：REC（Receiver）Mode Audio input terminal: INPREC、INNREC(Difference input) Class-D amplifier output power-supply voltage: Step-up switching regulator ⎛ R1 VSWREC = 1.0V × ⎜⎜1 + ⎝ R2 REC ⎞ ⎟⎟ = 4.5V (TYP) ⎠ Voltage gain: 5.1 dB (TYP) Switching regulator circuit Note) Reset it when you switch MODE. (STBYb“L") O Low Voltage Detector When the power-supply voltage drops down to below VDD, the output driver is turned off output pins (OUTP, OUTN, SW) become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. - 10 - NJW1262Ver.4.0_E NJW1262 NJU3555 O Short Circuit Protection The short-circuit protection circuit operates at the condition of the following. -Short between OUTP and OUTN - Power supply short and earth fault of OUTP terminal - Power supply short and earth fault of OUTN terminal - Power supply short of SW terminal When OUTP and OUTN of the short-circuit protection circuit operates, the OUTP and OUTN become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. It restarts by pulse-by-pulse of built-in clock of class-D amplifier. When SW terminal of the short-circuit protection circuit operates, the SW terminal become high impedance. It restarts by pulse-by-pulse of built-in clock of the switching regulator. Note) *1 The detectable current and the period for the protection depend on the power supply voltage, chip temperature and ambient temperature. *2 The short protector is not effective for a long term short-circuit current but for an instantaneous accident. Continuous high current may cause permanent damage to the NJW1262. O Thermal protection When the junction temperature is more than specified value, the output driver is turned off output pins (OUTP, OUTN, SW) become high impedance and class-D amplifier output is connected with VSS with about 100kΩ. When the junction temperature is less than specified value, protection is released. O OUTTEST pin This pin is JRC’s test pin. Q TOTAL HARMONIC DISTORTION MEASUREMENT CIRCUIT NJW1262 Ver.4.0_E - 11 - NJW1262 Q TYPICAL APPLICATION CIRCUIT Q Recommended Parts CL: VSLBP2115E1100-T1(muRata) CSW1: GRM31CB31E106KA75L (muRata) ×2 CDD1: GRM31CB31E106KA75L(muRata) CDD2,CSW2, CSFT: GRM155B31E104KA87D(muRata) CCSP, CCPREC, CCNREC: GRM033B10J333KE01D(muRata) CLPF1, CLPF2: GRM155B11H331KA01D(muRata) CCM: GRM155B31A105KE15D(muRata) LSW: LQH44PN6R8MPO(muRata) LOUT: LQH44PN220MP0(muRata) DSW: RSX201VA-30(ROHM) RDAMP: ERJ-14YJ3R9U(Panasonic) Q specifiedParts Rosc1, Rosc2 = RK73H1JTTD8202F(KOA) Note) De-coupling capacitors must be connected between each power supply terminal and GND (VDD-VSS, VDDO-VSS). Note) CDD2 (VDD-VSS) should be connected at a nearest point to the IC on PCB. Note) VSS and V should be connected at a nearest point to the IC on PCB. Note) INSP, INPREC, INNREC, EQ1, EQ2 and EQ3 should be not designed near OUTP,OUTN and SW, which emit PWM noise. Note) The transition time for MODE and STBYb signals must be less than 100µs. Otherwise, a malfunction may be occurred. Note) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carefully to fit your application. Note) The speaker should be designed at a near the IC. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 12 - NJW1262Ver.4.0_E NJW1262 NJU3555 Q PACKAGE INFORMATION NJW1262 Ver.4.0_E - 13 - NJW1262 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 14 - NJW1262Ver.4.0_E