® RT9108N 15W Stereo Class-D Audio Power Amplifier General Description Features The RT9108N is a 15W per channel, high efficiency Class D stereo audio amplifier for driving Bridge Tied Load (BTL) speakers. The RT9108N can drive stereo speakers with load as low as 4Ω. Its high efficiency eliminates the need for an extra heat sink when playing music. The gain of the amplifier can be controlled by two gain select pins. The outputs are fully protected against shorts to GND, PVCC, and output to output with an auto recovery feature z z z z z z z z 8V to 25.5V Input Supply Range 15W/CH for an 8Ω Ω Load, 16V Supply at 10% THD +N 88% Efficiency Eliminates Need for Heat Sinks Four Selectable or Fixed Gain Settings Robust Pin- to-Pin Short Circuit Protection Thermal Protection with Auto Recovery Option Surface Mount TSSOP-28 (Exposed Pad) Package RoHS Compliant and Halogen Free and monitored output. Applications The RT9108N is available in a TSSOP-28 (Exposed Pad) package. z z z Ordering Information LCD-TV Monitors DVD Players RT9108N Marking Information Package Type CP : TSSOP-28 (Exposed Pad-Option 3) RT9108NZCP : Product Number RT9108N ZCPYMDNN Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) YMDNN : Date Code Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Simplified Application Circuit RT9108N PVCC LINP Audio Source BSPL PVCCx FB OUTPL PGND OUTNL GAIN0 GAIN0 BSNL FB GAIN1 BSNR OUTNR FB GAIN1 RINP PGND OUTPR BSPR FB AGND Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9108N Pin Configurations (TOP VIEW) SD FAULT LINP LINN GAIN0 GAIN1 AVCC AGND GVDD PLIMIT RINN RINP NC MUTE PVCCL NC BSPL OUTPL PGND OUTNL BSNL BSNR OUTNR PGND OUTPR BSPR NC PVCCR 28 2 27 3 26 4 25 5 24 6 7 8 23 AGND 22 21 9 20 10 19 11 18 12 17 13 14 29 16 15 TSSOP-28 (Exposed Pad) Functional Pin Description Pin No. Pin Name Pin Function 1 SD Shutdown Logic Input for Audio Amp (High = outputs enabled). TTL logic levels with compliance to AVCC. 2 FAULT Open Drain Output for Short Circuit Fault Status. Short circuit faults can be set to auto recovery by connecting FAULT pin to SD pin. 3 LINP Positive Audio Input for Left Channel. Biased at 2V. 4 LINN Negative Audio Input for Left Channel. Biased at 2V. 5 GAIN0 Gain Select Least Significant Bit. 6 GAIN1 Gain Select Most Significant Bit. 7 AVCC 8, AGND 29 (Exposed Pad) 9 GVDD Analog Supply Input. Analog Ground. Connect to the thermal pad. The exposed pad must be soldered to a large PCB and connected to AGND for maximum power dissipation. High Side FET Gate Drive Supply. Nominal voltage is 4.6V. 10 PLIMIT Power Limit Level Adjustment. 11 RINN Negative Audio Input for Right Channel. Biased at 2V. 12 RINP Positive Audio Input for Right Channel. Biased at 2V. NC No Internal Connection. 14 MUTE Mute Logic Input for Audio Amp (Low = outputs enabled). 15 PVCCR Power Supply Input for Right Channel H-Bridge. Right channel and left channel power supply inputs are connected internally. 17 BSPR Bootstrap I/O for Right Channel, Positive High Side FET. 18 OUTPR Class-D H-Bridge Positive Output for Right Channel. 13, 16, 27 Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9108N-00 June 2012 RT9108N Pin No. 19, 24 Pin Name Pin Function PGND Power Ground for H-Bridges. 20 OUTNR Class-D H-Bridge Negative Output for Right Channel. 21 BSNR Bootstrap I/O for Right Channel, Negative High Side FET. 22 BSNL Bootstrap I/O for Left Channel, Negative High Side FET. 23 OUTNL Class-D H-Bridge Negative Output for Left Channel. 25 OUTPL Class-D H-Bridge Positive Output for Left Channel. 26 BSPL Bootstrap I/O for Left Channel, Positive High Side FET. 28 PVCCL Power Supply Input for Left Channel H-Bridge. Right channel and left channel power supply inputs are connected internally. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9108N Function Block Diagram SD PVCCL GVDD VDDP FAULT BSNL DRIVER OUTNL BSPL PLIMIT DRIVER OUTPL PGND LINN Modulator LINP PVCCR VDDP RINN BSNR DRIVER RINP OUTNR BSPR MUTE GAIN0 DRIVER GAIN Control OUTPR PGND GAIN1 AVCC UVLO OVP OTP OCP AGND Operation The RT9108N is a 15W (per channel) efficient Class-D audio power amplifier for driving bridged-tied stereo speakers. The RT9108N uses the three-level modulation scheme (BD model) that allows operation without the classic LC reconstruction filter when the amplifier drives is driving an inductive load. The internal close-loop modulator enables the negative error feedback, which improves the THD+N of output signal. An adjustable power limiter is included in the modulator to protect the load speaker. The adjustable power limiter allows the user to set a “virtual” voltage rail lower than the chip supply to limit the amount of current through the speaker. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 RT9108N has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the shortcircuit protection latch. The RT9108N can drive stereo speakers as low as 4Ω. The high efficiency of the RT9108N, 88%, eliminates the need for an external heat sink when playing music. is a registered trademark of Richtek Technology Corporation. DS9108N-00 June 2012 RT9108N Absolute Maximum Ratings z z z z z z z z z z z (Note 1) Supply Voltage, PVCCR, PVCCL, AVCC --------------------------------------------------------------Input Voltage, SD, GAIN0, GAIN1, FAULT ------------------------------------------------------------Output Voltage, OUTPR, OUTPL, OUTNR, OUTNL ------------------------------------------------Bootstrap Voltage, BSPR, BSPL, BSNR, BSNL ---------------------------------------------------Other Pins -----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C TSSOP-28 (Exposed pad) ---------------------------------------------------------------------------------Package Thermal Resistance (Note 2) TSSOP-28 (Exposed pad), θJA ---------------------------------------------------------------------------TSSOP-28 (Exposed pad), θJC --------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) --------------------------------------------------------------------------------MM (Machine Model) ---------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 28.5V −0.3V to (AVCC + 0.3V) −0.3V to (PVCCx + 0.3V) −0.3V to (PVCCx + GVDD) −0.3V to (GVDD + 0.3V) 3.571W 28°C/W 7°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage, PVCCR = PVCCL ---------------------------------------------------------------------- 8V to 25.5V Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (PVCCx = 12V, RL = 8Ω, TA = 25°C, unless otherwise specified) Parameter SD, GAIN0, GAIN1, MUTE Input Voltage Symbol Test Conditions Min Typ Max Unit Logic-High VIH 3 -- -- V Logic-Low VIL -- -- 0.8 V Low Level Output Voltage VOL FAULT, RPULL-UP = 100kΩ -- -- 0.8 V High Level Input Current IIH SD, GAIN0, GAIN1, MUTE, VI = 3V, -- -- 50 μA Low Level Input Current IIL SD, GAIN0, GAIN1, MUTE, VI = 0.8V, -- -- 10 μA VI = 0V, Gain = 36dB -- 5 30 mV IQ VSD = 3V, no load -- 20 50 mA IQ_SHDN VSD = 0.8V, no load -- 250 400 μA R DS(ON) IO = 500mA, TJ = 25°C High Side Low Side --- 250 250 --- mΩ VGAIN0 = 0.8V 19 20 21 VGAIN0 = 3V 25 26 27 VGAIN0 = 0.8V 31 32 33 VGAIN0 = 3V 35 36 37 Class-D Output Offset Voltage |VOS| (measured differentially) Quiescent Supply Current Quiescent Supply Current in Shutdown Mode Drain-Source On-State Resistance VGAIN1 = 0.8V Gain G VGAIN1 = 3V Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 dB is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9108N Parameter Symbol Test Conditions Min Typ Max Unit Turn-On Time tON VSD = 3V -- 50 -- ms Turn-Off Time tOFF VSD = 0.8V -- 2 -- ms Gate Drive Supply VGVDD IGVDD = 2mA 4.2 4.6 5 V Power Supply Ripple Rejection PSRR 200mVPP ripple at 1kHz, Gain = 20dB, Inputs ac-coupled to AGND -- −60 -- dB Continuous Output Power Total Harmonic Distortion + Noise PO THD + N = 10%, fIN = 1kHz, PVCC = 13V -- 10 -- W THD + N fIN = 1kHz, PO = 5W -- 0.15 -- % Output Integrated Noise VN 20Hz to 22kHz, A-weighted filter, Gain = 20dB ---- 120 −80 −80 ---- μV dBV dB -- 95 -- dB 220 300 380 kHz Crosstalk Signal-to-Noise Ratio SNR Oscillator Frequency fOSC VO = 1VRMS, Gain = 20dB, fIN = 1kHz Maximum output at THD + N < 1%, fIN = 1kHz, Gain = 20dB, A-weighted filter (PVCCx = 24V, RL = 8Ω, TA = 25°C, unless otherwise specified) Parameter SD, GAIN0, GAIN1, MUTE Input Voltage Symbol Test Conditions Min Typ Max Unit Logic-High VIH 3 -- -- V Logic-Low -- -- 0.8 V VIL Low Level Output Voltage VOL FAULT, RPULL-UP = 100kΩ -- -- 0.8 V High Level Input Current IIH SD, GAIN0, GAIN1, MUTE, VI = 3V, -- -- 50 μA Low Level Input Current IIL SD, GAIN0, GAIN1, MUTE, VI = 0.8V, -- -- 10 μA Class-D Output Offset Voltage (measured differentially) |VOS| VI = 0V, Gain = 36dB -- 8 30 mV IQ VSD = 3V, No Load -- 30 50 mA IQ_SHDN VSD = 0.8V, No Load -- 550 600 μA VGAIN0 = 0.8V 19 20 21 VGAIN0 = 3V 25 26 27 VGAIN0 = 0.8V 31 32 33 VGAIN0 = 3V 35 36 37 -- 26.5 -- V Quiescent Supply Current Quiescent Supply Current in Shutdown Mode VGAIN1 = 0.8V Gain G VGAIN1 = 3V dB PVCC Over Voltage Lockout OVP Turn-On Time tON VSD = 3V -- 50 -- ms Turn-Off Time tOFF VSD = 0.8V -- 2 -- ms Gate Drive Supply VGVDD IGVDD = 2mA 4.2 4.6 5 V PSRR 200mVPP ripple at 1kHz, Gain = 20dB, Inputs ac-coupled to AGND -- −60 -- dB Power Supply Ripple Rejection Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9108N-00 June 2012 RT9108N Parameter Symbol Continuous Output Power PO Total Harmonic Distortion + Noise THD + N Output Integrated Noise VN Crosstalk Test Conditions THD + N = 10%, fIN = 1kHz, PVCC = 16V PV CC = 16V, fIN = 1kHz, PO = 7.5W (half-powe) Min Typ Max Unit -- 15 -- W -- 0.15 -- % 20Hz to 22kHz, A-weighted filter, Gain = 20dB -- 120 -- μV -- −80 -- dBV VO = 1V RMS , Gain = 20dB, fIN = 1kHz -- −80 -- dB Maximum output at THD + N < 1%, fIN = 1kHz, Gain = 20dB, A-weighted filter -- 95 -- dB Signal-to-Noise Ratio SNR Oscillator Frequency fOSC 220 300 380 kHz Thermal Trip Point TSD -- 150 -- °C Thermal Hysteresis ΔTSD -- 15 -- °C Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity single-layer test board per JEDEC 51-3. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9108N Typical Application Circuit PVCC 1k SD 0.22µF 3 0.22µF 4 5 GAIN0 6 GAIN1 PVCC 10 Audio Source 7 1µF PVCC RT9108N 100k 28 PVCCL 1 SD 2 FAULT LINP BSPL LINN GAIN0 21 BSNR 20 OUTNR 19 PGND 18 OUTPR 17 BSPR AVCC GVDD 0.22µF 12 1nF 1nF FB 0.22µF FB 1nF 1nF FB PVCC PLIMIT PVCCR 11 FB 0.22µF 1µF 0.22µF 1nF 0.22µF GAIN1 AGND 10 0.1µF 0.22µF 25 OUTPL 24 PGND 23 OUTNL 22 BSNL 8, 29 (Exposed Pad) 9 26 100µF 15 100µF RINN MUTE 14 RINP 0.1µF 1nF 0.1µF 1nF MUTE Figure 1. Typical Application Circuit PVCC PVCC RT9108N PVCCL 28 100k 1k SD 1 SD 2 FAULT 3 LINP 0.22µF 0.22µF 4 5 GAIN0 6 GAIN1 PVCC 10 Audio Source 1µF 7 8, 29 (Exposed Pad) 9 LINN GAIN0 100µF BSPL 26 AGND GVDD 1µF 22µH 25 OUTPL 24 PGND 23 OUTNL 22 BSNL 0.47µF 22µH 0.47µF 0.22µF GAIN1 AVCC 0.22µF 21 BSNR 20 OUTNR 19 PGND 18 OUTPR 17 BSPR 0.22µF 22µH 0.47µF 22µH 0.47µF 0.22µF 10 0.22µF 0.22µF 11 12 PLIMIT PVCC PVCCR 15 RINN RINP 100µF MUTE 14 0.1µF 1nF MUTE Figure 2. Typical LC Output Filter Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9108N-00 June 2012 RT9108N Typical Operating Characteristics Efficiency vs. Output Power 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Efficiency vs. Output Power 100 60 50 40 30 60 50 40 30 20 20 PVCC = 12V, f = 1kHz, Gain = 20dB LC Filter = 22μH + 0.47μF, ZL = 8Ω 10 PVCC = 24V, f = 1kHz, Gain = 20dB LC Filter = 22μH + 0.47μF, ZL = 8Ω 10 0 0 0 1 2 3 4 5 6 7 8 9 0 10 2 4 Output Power (W) THD+N (%) THD+N (%) 10kHz PVCC = 12V, RL = 8Ω, Gain = 20dB 2 5 PVCC = 24V, RL = 8Ω, Gain = 20dB 2 1 1 1W 7W PVCC = 12V, RL = 8Ω, Gain = 20dB 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 THD+N (%) THD+N (%) 0.5W 50 5 10 20 50 5W 0.5 0.2 0.1 20 2 THD+N vs. Frequency 2 0.001 20 Output Power (W) 10 5 0.005 0.002 18 20Hz THD+N vs. Frequency 0.02 0.01 16 10kHz 10m 20m 50m 100m 200m 500m 1 10 20 10 5 0.05 14 1kHz Output Power (W) 0.5 12 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20Hz 10m 20m 50m 100m 200m 500m 1 10 THD+N vs. Output Power 1kHz 0.02 0.01 0.005 0.002 0.001 8 Output Power (W) THD+N vs. Output Power 20 10 5 2 1 0.5 0.2 0.1 0.05 6 0.2 0.1 0.05 10W 1W 0.02 0.01 0.005 0.002 0.001 PVCC = 24V, RL = 8Ω, Gain = 20dB 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9108N Output Power vs. Supply Voltage Crosstalk vs. Frequency 40 -20 -30 35 Output Power (W) -40 Crosstalk (dB) -50 -60 -70 R to L -80 L to R -90 -100 -110 THD + N = 10% 25 20 THD + N = 1% 15 10 5 -120 -130 30 PVCC = 24V, RL = 8Ω, VOUT = 1VRMS, Gain = 20dB 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 ZL = 8Ω + 66μH, Gain = 20dB, Stereo Out 0 6 8 10 12 14 16 18 20 22 24 26 Supply Power (V) is a registered trademark of Richtek Technology Corporation. DS9108N-00 June 2012 RT9108N Application Information Amplifier Gain Setting The gain of the RT9108N amplifier can be set by two input terminals, GAIN0 and GAIN1, shown as Table 1. The gain setting is realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by the ratios of the resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. GAIN1 Table 1. Gain Setting Amplifier Input Impedance GAIN (dB) (kΩ) GAIN0 Typ Typ 0 0 20 100 0 1 26 50 1 0 32 25 1 1 36 12.5 SD Operation The RT9108N employs a shutdown mode operation designed to reduce supply current (ICC) to the absolute minimum level for power saving. The SD input terminal should be held high (see specification table for trip point) in normal operation. Pulling SD low causes the outputs to mute and the amplifier to enter a low current state. Leaving SD floating will cause the amplifier operation to be unpredictable. Never leave SD pin unconnected! Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 For the best power-off pop performance, turn off the amplifier in the shutdown mode prior to removing the power supply voltage. GVDD Supply The GVDD is used to supply the Gate Drivers for the output full bridge transistors. Connect a 1μF capacitor from this pin to ground for good bypass. The typical GVDD output voltage is 4.6V. Power Limit The output power limit is programmable by the PLIMIT pin voltage level. Table 2 and Table 3 show the WidthFactor and maximum output power with different PLIMIT voltages. The voltage setting at PLIMIT pin can be achieved by using a resistive divider between GVDD pin and AGND pin or using an external reference voltage. It's recommended to add a 1μF capacitor from the PLIMIT to AGND for noise reduction. The output power can be estimated by the following equation. Output Power = PVCC2 × (Width_Factor) RL × 1.35 Table 2. PLIMIT Voltage and Width-Factor PLIMIT Voltage (V) Width_Factor 4.6 (GVDD) 2.8 to 2.9 2.4 to 2.5 2.1 to 2.2 1.6 to 1.7 1.3 to 1.4 1 0.765 0.578 0.41 0.265 0.149 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9108N Table 3. Typical PLIMIT Operation at 24V Power Supply PVCC = 24V, VIN = 1.5VRMS, RL = 8Ω Gain = 20dB Gain = 26dB Gain = 32dB Gain = 36dB PLIMIT Voltage (V) Output Power (W) Output Power (W) Output Power (W) Output Power (W) 4.6 (GVDD) 2.8 to 2.9 26.4 24.6 (Thermal Limited) (Thermal Limited) (Thermal Limited) (Thermal Limited) 2.4 to 2.5 20.8 26.3 2.1 to 2.2 1.6 to 1.7 1.3 to 1.4 16.1 11.2 6.9 19.2 12.8 7.52 (Thermal Limited) (Thermal Limited) 28.1 (Thermal Limited) 20.3 13.5 7.78 (Thermal Limited) 21.1 13.8 7.85 Short Circuit Protection and Automatic Recovery Thermal Considerations The RT9108N has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. For continuous operation, do not exceed absolute maximum junction temperature. The maximum power If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit protection latch. PD(MAX) = (TJ(MAX) − TA) / θJA Thermal Protection Thermal protection on the RT9108N prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction. Thermal protection faults are NOT reported on the FAULT terminal. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For TSSOP-28 (Exposed Pad) packages, the thermal resistance, θJA, is 28°C/W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (28°C/W) = 3.571W for TSSOP-28 (Exposed Pad) package The maximum power dissipation depends on the operating ambient temperature for fixed T J (MAX) and thermal resistance, θJA. The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. is a registered trademark of Richtek Technology Corporation. DS9108N-00 June 2012 RT9108N Maximum Power Dissipation (W)1 4.0 Layout Considerations Single Layer PCB 3.6 For the best performance of the RT9108N, the below PCB Layout guidelines must be strictly followed. 3.2 2.8 ` 2.4 2.0 1.6 1.2 0.8 0.4 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Place the decoupling capacitors as close as possible to the AVCC, PVCCL, PVCCR and GND pins. For achieving a good quality, consider adding a small, good performance low ESR ceramic capacitor between 220pF and 1000pF and a larger mid-frequency capacitor between 0.1μF and 1μF to the PVCC pins of the chip. Do not trace out the NC pins (Pin13, 16 and Pin27) to avoid the pin short issue. ` Keep the differential output traces as wide and short as possible. Figure 3. Derating Curve of Maximum Power Dissipation ` The traces of (LINP & LINN, RINP & RINN) and (OUTPL & OUTNL, OUTPR & OUTNR) should be kept equal width and length respectively. ` The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be larger for application. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. GND The decoupling capacitor (CS) must be placed as close to the IC as possible SD FAULT LINP Audio CIN Input LINN GAIN0 GAIN1 PVCC CS AVCC AGND GVDD GND CG PLIMIT RINN Audio CIN Input RINP NC MUTE 28 2 27 3 26 4 25 5 24 6 23 7 8 AGND 22 21 9 20 10 19 11 18 12 17 13 14 29 16 15 CS PVCCL NC BSPL OUTPL PGND OUTNL BSNL BSNR OUTNR PGND OUTPR BSPR NC PVCCR CS CB Do not trace out The decoupling capacitor (CS) must be placed as close to the IC as possible FB GND FB CB CB FB GND FB Do not trace out GND The decoupling capacitor (CS) must be placed as close to the IC as possible Figure 4. PCB Layout Guide Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9108N-00 June 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9108N Outline Dimension Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 1.000 1.200 0.039 0.047 A1 0.000 0.150 0.000 0.006 A2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 D 9.600 9.800 0.378 0.386 e 0.650 0.026 E 6.300 6.500 0.248 0.256 E1 4.300 4.500 0.169 0.177 L 0.450 0.750 0.018 0.030 U 4.410 5.510 0.174 0.217 V 2.400 3.000 0.094 0.118 U 5.500 6.170 0.217 0.243 V 1.600 2.210 0.063 0.087 U 5.800 6.200 0.228 0.244 V 2.600 3.000 0.102 0.118 Option 1 Option 2 Option 3 28-Lead TSSOP (Exposed Pad) Plastic Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 14 DS9108N-00 June 2012