RICHTEK RT9367C

RT9367C
I2C Programmable White LED Driver with Dual LDO
General Description
The RT9367C is an integrated solution for backlighting
and phone camera input supply. The part contains a charge
pump white LED driver and dual low dropout linear
regulators. This IC can be shutdown by pulling ENA low.
In the section of charge pump, The RT9367C can power
up 4 white LEDs with regulated constant current for uniform
intensity. Each channel (LED1-LED4) can support up to
25mA. The part maintains highest efficiency by utilizing
a x1/x1.5/x2 fractional charge pump and low dropout
current regulators. An internal 5-bit DAC is used for
brightness control. Users can easily configure up to 32step of LED current by I2C interface.
In the section of linear regulator, The RT9367C comprises
a dual channel, low noise, and low dropout regulator
sourcing up to 300mA at each channel. The range of output
voltage can be configured from 1.1V to 3.3V by I2C
interface. The outputs of LDO offer 3% accuracy and low
dropout voltage of 250mV @300mA. The LDO also
provides current limiting and output short circuit thermal
folded back protection.
Ordering Information
RT9367C
Package Type
QW : WQFN-20L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Features
An Integrated Solution for Backlighting and Phone
Camera Input Supply
I2C Programmable, 32 Steps Dimming Control and
Independent Channel On/Off Control
Over Temperature Protection
Power On Reset for Data Register
Typical 1uA Low Shutdown Current with Interface
Fully On
Charge Pump White LED Driver
` Over 93% Peak Efficiency Over Li-ion Battery
Discharge
` Typical 85% Average Efficiency Over Li-ion Battery
Discharge
` Support Up to 4 White LEDs
` Output Current Up to 25mA/Channel 100mA Total
` 60mV Typical Current Source Dropout
` 1% Typical LED Current Accuracy
` 0.7% Typical LED Current Matching
` Automatic x1/x1.5/x2 Charge Pump Mode
Transition
` Low Input Noise and EMI Charge Pump
` 5.5V Over Voltage Protection
` Power On/Mode Transition In-rush Protection
` 1MHz Random Frequency Oscillator
` Typical 0.1uA Low Shutdown Current
Dual LDO
` Wide Operating Voltage Range
` Low-Noise Output
` No Noise Bypass Capacitor Required
` Fast Response in Line/Load Transient
` Low Temperature Coefficient
` Dual LDO Outputs (300mA/300mA)
` 3% Max Output Accuracy
` Current Limit Protection
` Short Circuit Thermal Folded Back Protection
` Typical 0.1uA Low Shutdown Current
RoHS Compliant and Halogen Free
Applications
Camera Phone, Smart Phone
White LED Backlighting, CMOS Sensor Input Supply
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RT9367C
Pin Configurations
Marking Information
(TOP VIEW)
RT9367CGQW
VOUT
LED1
LED2
LED3
LED4
FM= : Product Code
FM=YM
DNN
20 19 18 17 16
C1N
C2N
PGND
C2P
C1P
1
15
2
14
GND
3
4
13
21
5
12
11
7
8
RT9367CZQW
9 10
FM : Product Code
PVIN
SCL
SDA
ENA
NC
6
NC
LDO2
AVIN
LDO1
AGND
YMDNN : Date Code
FM YM
DNN
WQFN-20L 3x3
YMDNN : Date Code
Typical Application Circuit
CIN1
2.2µF
Chip Enable
CIN2
1µF
C2P
C1N
4
2
LED4 16
LED3 17
6 PVIN
LED2 18
RT9367C
LED1
13 AVIN
9 ENA
12
14
PGND
(2k to 10k)
1
LDO2
I C
7 SCL
8 SDA
C1P
2
2
I C
VIN
2.8V to 5.5V
5
R2
LDO1
R1
CFLY2
1µF
CFLY1
1µF
C2N
VCC
2.5V to 5.5V
19
20
VOUT
AGND 11
COUT
1µF
3,
21 (Exposed Pad)
CLDO1 CLDO2
1µF
1µF
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RT9367C
Timing Diagram
The 1st Word (Chip
Address, R/W)
I2C Adress
SCL
The 2nd Word (Sub
Address, Data)
Sub
Adress
R/W
The 3rd Word (data)
Channel
selection ON/OFF Test Mode
Data II
Start
A6 A5 A4 A3 A2 A1 A0 0
B7 B6 B5 B4 B3 B2 B1 B0
C7 C6 C5 C4 C3 C2 C1 C0
Stop
Start
A6 A5 A4 A3 A2 A1 A0 0
B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 C4 C3 C2 C1 C0
Stop
S
P
1
SDA
0
S
W
R
ACK
P
2
3
4
5
6
7
A6 A5 A4 A3 A2 A1 A0
8
9
1
2
3
4
W ACK B7 B6 B5
0
5
6
7
8
9
1
2
3
B3 B2 B1 B0 ACK 0
0
C5 C4 C3 C2 C1 C0 ACK
4
5
6
7
8
9
= Start Condition
= Write (SDA = “0＂)
= Read (SDA = “1＂)
= Acknowledge
= Stop Condition
Figure 1. I2C Interface Trimming Diagram
ENA
SDA
V IH(MIN)
V IL(MAX)
tSU,DAT
tLOW
SCL V IH(MIN)
V IL(MAX)
tHD,DAT
tHIGH
tf
tHD,STA
tSU,STO
tBUF
tr
S
P
S
Figure 2
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RT9367C
Functional Pin Description
C1P
Function Block Diagram
C2N
GND
Pin Function
Fly Capacitor 1 Negative Connection.
Fly Capacitor 2 Negative Connection.
Power Ground.
Fly Capacitor 2 Positive Connection.
Fly Capacitor 1 Positive Connection.
Power Input.
I2C Clock Input.
I2C Data Input.
Chip Enable (Active High).
No Internal Connection.
Analog Ground.
LDO 1 Output.
Analog Power Input.
LDO 2 Output.
Current Sink for LED4.
Current Sink for LED3.
Current Sink for LED2.
Current Sink for LED1.
Charge Pump Output.
The exposed pad must be soldered to a large PCB and connected to GND for
maximum power dissipation.
C2P
21 (Exposed Pad)
Pin Name
C1N
C2N
PGND
C2P
C1P
PVIN
SCL
SDA
ENA
NC
AGND
LDO1
AVIN
LDO2
LED4
LED3
LED2
LED1
VOUT
C1N
Pin No.
1
2
3
4
5
6
7
8
9
10, 15
11
12
13
14
16
17
18
19
20
x1/x1.5/x2
Charge Pump
Non-overlap
driving signal
PVIN
OVP
x1/x1.5/x2
Mode Decision
Soft Start
Circuit
UVLO
Current
Limitation
Current
Bias
V r1
Low Dropout Current
Source
32 Steps
Current Setting
Register
1MHz
Oscillator
LED4
LED3
LED2
LED1
AVIN
-
Channel
Selecting
Register
+
ENA
SCL
AVIN
+
-
Gate Driver
BandGap
Reference
VOUT
R SET
2
I C
OTP
SDA
+
LDO2
AGND
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4
-
DAC
32 Step Voltage
Reference Register 1
+
-
32 Step Voltage
Reference Register 2
LDO1
PGND
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RT9367C
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, AVIN, PVIN ---------------------------------------------------------------------------------------- −0.3V to 6V
Output Voltage, VOUT ------------------------------------------------------------------------------------------------------ −0.3V to 6V
Other Pins ---------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
Power Dissipation, PD @ TA = 25°C
WQFN-20L 3x3 --------------------------------------------------------------------------------------------------------------- 1.471W
Package Thermal Resistance (Note 2)
WQFN-20L 3x3, θJA ---------------------------------------------------------------------------------------------------------- 68°C/W
WQFN-20L 3x3, θJC --------------------------------------------------------------------------------------------------------- 7.5°C/W
Junction Temperature -------------------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------------------- 260°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)
Junction Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = AVIN = PVIN = 3.6V, CIN1 = 2.2uF, CIN2 = 1uF, COUT = 1uF, CFLY1 = CFLY2 = 1uF, VF = 3.5V, ILED1 = ILED2= ILED3 = ILED4 =
15mA, TA = 25°C, unless otherwise specification)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
2.8
--
5.5
V
--
1
7
μA
1.8
2.0
2.5
V
--
100
--
mV
Input Power Supply
Input Supply Voltage
VIN
Shutdown Current
ISHDN
VIN = 5V, ENA = 0V
Charge Pump LED Driver Block
Under-Voltage Lockout Threshold
VIN Rising.
Under-Voltage Lockout Hysteresis
Quiescent of x1 Mode
IQ_x1
--
1
2.5
mA
Quiescent of x2 Mode
IQ_x2
--
3.5
7
mA
ILEDX = 15mA
−8
0
+8
%
ILEDX = 15mA
−5
0
+5
%
--
1000
--
kHz
--
3.65
3.8
V
--
250
--
mV
LED Current
I LEDX Accuracy
ILED-ERR
Current Matching
Oscillator Frequency
f OSC
Mode Decision
x1 Mode to x2 Mode
Transition Voltage
Mode Transition Hystersis
VTS_x2
VIN Falling
To be continued
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RT9367C
(VIN = AVIN = PVIN = VLDOX + 1V, CIN2 = CLDO1 = CLDO2 = 1uF, TA = 25°C, unless otherwise specified.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
--
240
--
mV
1.1
--
3.3
V
LDO Block
Dropout Voltage
VDROP
VLDOx = 3.3V, I OUT = 300mA
Output Voltage Range
VLDOx
VOUT Accuracy
ΔV
I OUT = 1mA
−3
--
3
%
Line Regulation
ΔVLINE
VIN = (VOUT + 0.3V) to 5.5V or
VIN > 2.5V, whichever is larger
--
0.01
0.2
%/V
Load Regulation
ΔVLOAD
1mA < IOUT < 300mA
--
0.01
0.6
%
Current Limit
ILIM
RLOAD = 1Ω
330
500
700
mA
Quiescent Current
IQ
--
60
100
μA
--
100
--
ppm/°C
Output Voltage Temperature
Coefficent
Thermal Shutdown
TSD
--
170
--
°C
Thermal Shutdown Hysteresis
ΔTSD
--
40
--
°C
Input High Voltage
VIH
1.5
--
5.5
V
Input Low Voltage
VIL
0
--
0.4
V
Clock Operating Frequency
fSCL
--
--
400
kHz
Output Low Level
VOL
--
--
0.4
V
Input High Level Current of SCL,
SDA
IIH
--
2
--
μA
Bus Free Time Between a STOP
and START Condition
tBUF
(Note 5)
1.3
--
--
μs
Hold Time After START Condition
tHD,STA
(Note 5)
0.6
--
--
μs
Data Setup Time
tSU,DAT
(Note 5)
200
--
ns
Set-Up Time for STOP Condition
tSU,STO
(Note 5)
0.6
--
--
μs
Input Date Hold Time
tHD,DAT
(Note 5)
200
--
900
ns
Low Period of the SCL Clock
tLOW
(Note 5)
1.3
--
--
μs
High Period of the SCL Clock
tHIGH
(Note 5)
0.6
--
--
μs
Clock Data Fall Time
tf
(Note 5)
20
--
300
ns
Clock Data Rise Time
tr
(Note 5)
20
--
300
ns
Input Low Time for Shutdown
tSHDN
(Note 6) Both SCL and SDA are
floating
400
1000
2000
μs
Logic-High Voltage
ENA
Threshold Logic-Low Voltage
VIH
1.5
--
--
VIL
--
--
0.4
2
I C Block
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6
I SDA = 3mA
V
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RT9367C
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the WQFN package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. All values are referred to VIH and VIL levels.
Note 6. In normal operation, the low time of both SCL and SDA must be less than 200us.
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RT9367C
Typical Operating Characteristics
Efficiency vs. Input Voltage
Efficiency vs. Input Voltage
90
90
80
80
70
70
Efficiency (%)
100
Efficiency (%)
100
60
50
40
30
60
50
40
30
20
10
20
10
Vf = 3.1V, LED = 15mA
0
Vf = 3.3V, LED = 25mA
0
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
2.6
3.1
3.6
Input Voltage (V)
4.1
4.6
5.1
5.6
Input Voltage (V)
LED Current vs. Input Voltage
LED Current vs. Input Voltage
20
30
19
25
LED Current (mA)
LED Current (mA)
18
17
16
15
LED1
LED2
LED3
LED4
14
13
12
11
10
LED1
LED2
LED3
LED4
20
15
10
5
Vf = 3.1V, LED = 15mA
0
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
Vf = 3.3V, LED = 25mA
2.8
3.3
3.8
Input Voltage (V)
x1 Mode Quiescent Current vs. Input Voltage
2.0
6.0
LDE1 to 4 Short
5.5
Quiescent Current (mA)
Quiescent Current (mA)
1.6
1.4
1.0
4.8
5.3
5.8
x2 Mode Quiescent Current vs. Input Voltage
1.8
1.2
4.3
Input Voltage (V)
15mA
0.8
0.6
0.4
0.2
LDE1 to 4 Open
5.0
4.5
4.0
3.5
15mA
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
2.8
3.2
3.6
4
4.4
Input Voltage (V)
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8
4.8
5.2
5.6
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
Input Voltage (V)
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RT9367C
Frequency vs. Temperature
Shutdown Current vs. Input Voltage
1.2
5.0
1.1
4.0
Frequency (MHz)
Shutdown Current (uA)
4.5
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
1.0
0.6
0.5
0.0
0.5
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Input Voltage (V)
Temperature (°C)
x1.5 Mode Inrush Current Response
x1.5 Mode Inrush Current Response
VIN = 3.7V, Vf = 3.7V, LED = 25mA
VIN = 3.3V, Vf = 3.7V, LED = 15mA
C1P
(5V/Div)
C1P
(5V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
SDA
(5V/Div)
SDA
(5V/Div)
I IN
(200mA/Div)
I IN
(200mA/Div)
Time (100μs/Div)
Time (100μs/Div)
x2 Mode Inrush Current Response
x2 Mode Inrush Current Response
VIN = 2.8V, Vf = 3.7V, LED = 15mA
VIN = 3V, Vf = 3.7V, LED = 25mA
C1P
(5V/Div)
C1P
(5V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
SDA
(5V/Div)
SDA
(5V/Div)
I IN
(200mA/Div)
I IN
(200mA/Div)
Time (100μs/Div)
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Time (100μs/Div)
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RT9367C
x1.5 Mode Ripple & Spike
x2 Mode Ripple & Spike
VIN
(100mV/Div)
VIN
(100mV/Div)
VOUT
(100mV/Div)
VOUT
(100mV/Div)
C1P
(5V/Div)
C1P
(5V/Div)
I IN
(100mA/Div)
I IN
(100mA/Div)
VIN = 3.3V, Vf = 3.7V, LED = 15mA
Time (500ns/Div)
Time (500ns/Div)
x1.5 Mode Ripple & Spike
x2 Mode Ripple & Spike
VIN
(100mV/Div)
VIN
(100mV/Div)
VOUT
(100mV/Div)
VOUT
(100mV/Div)
C1P
(5V/Div)
C1P
(5V/Div)
I IN
(100mA/Div)
VIN = 2.8V, Vf = 3.7V, LED = 15mA
VIN = 3.7V, Vf = 3.7V, LED = 25mA
I IN
(100mA/Div)
VIN = 3V, Vf = 3.7V, LED = 25mA
Time (500ns/Div)
Time (500ns/Div)
Power On from ENA
Power Off from ENA
VIN = 4.2V, VLDO1 = 2.6V, ILDO1 No Load
VENA
(2V/Div)
VENA
(2V/Div)
VSDA
(5V/Div)
VSDA
(5V/Div)
VSCL
(5V/Div)
VSCL
(5V/Div)
VLDO1
(2V/Div)
VLDO1
(2V/Div)
VIN = 4.2V, VLDO1 = 2.6V, ILDO1 No Load
Time (1ms/Div)
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Time (1ms/Div)
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RT9367C
2
2
LDO2 Output Voltage vs. I C Code
3.5
3.5
3.0
3.0
ST
= 85°C
T = 25°C
T = −40°C
2.5
2.0
Output Voltage (V)
Output Voltage (V)
LDO1 Output Voltage vs. I C Code
1.5
1.0
0.5
ST
= 85°C
T = 25°C
T = −40°C
2.5
2.0
1.5
1.0
0.5
0.0
0.0
00
03
06
09
0C
0F
12
15
18
1B
1E
00
03
06
09
0C
2
15
18
1B
1E
I C Code
LDO Output Voltage vs. Load Current
3.312
LDO Output Voltage vs. Temperature
3.320
VIN = 5V
VIN = 5V, ILOAD = 1mA
3.315
3.308
Output Voltage (V)
3.310
Output Voltage (V)
12
2
I C Code
LDO1
3.306
LDO2
3.304
3.302
3.300
3.310
3.305
LDO1
3.300
LDO2
3.295
3.290
3.285
3.280
3.298
3.275
0
50
100
150
200
250
300
-50
-25
Load Current (mA)
0
25
50
75
100
125
Temperature (°C)
LDO2 Dropout Voltage vs. Load Current
LDO1 Dropout Voltage vs. Load Current
300
300
VLDO1 = 3.3V
250
VLDO2 = 3.3V
250
200
150
T = 85°C
T = 25°C
T = -40°C
100
50
0
Dropout Voltage (mV)
Dropout Voltage (mV)
0F
200
150
T = 85°C
T = 25°C
T = -40°C
100
50
0
0
50
100
150
200
Load Current (mA)
DS9367C-01 March 2011
250
300
0
50
100
150
200
250
300
Load Current (mA)
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RT9367C
LDO1 PSRR
20
VLDO1 = 3.3V
Load
Load
Load
Load
-20
= 0mA
= 1mA
= 10mA
= 100mA
VLDO2 = 3.3V
Load
Load
Load
Load
0
PSRR (dB)
PSRR (dB)
0
LDO2 PSRR
20
-40
-60
-20
= 0mA
= 1mA
= 10mA
= 100mA
-40
-60
-80
-80
-100
-100
10
0.01
100
0.1
1000
1
10000
10
100000
100
0.01
10
1000000
1000
1
1000
10
10000
100
100000
1000
1000000
(kHz)
Frequency (Hz)
(kHz)
Frequency (Hz)
LDO Line Transient Response
LDO Line Transient Response
IOUT1 = IOUT2 = 10mA
IOUT1 = IOUT2 = 1mA
VIN 5
(V)
0.1
100
VIN 5
(V)
4
4
VLDO1
(10mV/Div)
VLDO1
(10mV/Div)
VLDO2
(10mV/Div)
VLDO2
(10mV/Div)
VIN = 4V to 5V, VLDO1 = VLDO2 = 3.3V
VIN = 4V to 5V, VLDO1 = VLDO2 = 3.3V
Time (250μs/Div)
Time (250μs/Div)
LDO Load Transient Response
LDO Load Transient Response
IOUT
(100mA/Div)
IOUT
(50mA/Div)
VLDO1
(50mV/Div)
VLDO1
(20mV/Div)
VLDO2
(50mV/Div)
VLDO2
(20mV/Div)
IOUT1 = IOUT2 = 10mA to 50mA
VIN = 5V, VLDO1 = VLDO2 = 3.3V
Time (250μs/Div)
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IOUT1 = IOUT2 = 10mA to 150mA
VIN = 5V, VLDO1 = VLDO2 = 3.3V
Time (250μs/Div)
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RT9367C
Applications Information
The RT9367C is a high efficiency charge pump white LED
driver. It provides 4 channels low dropout voltage current
source to regulated 4 white LEDs current. For high
efficiency, the RT9367C implements a smart mode
transition for charge pump operation. The RT9367C
provides I2C dimming function for LED brightness control.
Input UVLO
The input operating voltage range of the RT9367C is 2.8V
to 5.5V. An input capacitor at the VIN pin could reduce
ripple voltage. It is recommended to use a ceramic 1uF or
larger capacitance as the input capacitor. This IC provides
an under voltage lockout (UVLO) function to prevent it from
unstable issue when startup. The UVLO threshold of input
rising voltage is set at 2V typically with a hysteresis 0.1V.
efficiency of the system. The lower value will improve
efficiency, but it will limit the LED's current at low input
voltage. For 4 X 25mA load over the entire input voltage
range of 2.8V to 5.5V, it is recommended to use 1μF
ceramic capacitor on the flying capacitor CFLY1 & CFLY2.
Power Sequence
In order to assure the RT9367C's operation in normal
condition, the Input voltage and ENA should be ready
before the RT9367C get the I2C signal showed in Figure 3
and the RT9367C can be shut down by pulling ENA low.
When ENA is reset, the I2C signal also needs to be resent
again for operating at normal condition.
ENA
Soft Start
The RT9367C includes a soft start circuit to limit the inrush
current at power on and mode switching. The soft start
circuit limits the input current before output voltage
reaching a desired voltage level.
SDA
……………
SCL
……………
Figure 3. The power sequence
Mode Decision
Dual LDO
The RT9367C uses a smart mode decision method to
select the working mode for maximum efficiency. The
charg pump can operation at x1, x1.5 or x2 mode. The
mode decision circuit senses the output voltage and LED
voltage for up/down selection.
Like any low-dropout regulator, the external capacitors
used with the RT9367C must be carefully selected for
regulator stability and performance. Using a capacitor
whose value is > 1μF on the RT9367C input and the amount
of capacitance can be increased without limit. The input
capacitor must be located at a distance of not more than
0.5 inch from the input pin of the IC and returned to a
clean analog ground. Any good quality ceramic or tantalum
can be used for this capacitor. The capacitor with larger
value and lower ESR (equivalent series resistance) provides
better PSRR and line-transient response. The output
capacitor must meet both requirements for minimum
amount of capacitance and ESR in all LDOs application.
The RT9367C is designed specifically to work with low
ESR ceramic output capacitor in space-saving and
performance consideration. Using a ceramic capacitor
whose value is at least 1μF with ESR is > 20mΩ on the
RT9367C output ensures stability. The RT9367C still
works well with output capacitor of other types due to the
wide stable ESR range. Figure 4. shows the curves of
allowable ESR range as a function of load current for various
Selecting Capacitors
To get better performance of RT9367C, the selection of
peripherally appropriate capacitor and value is very
important. These capacitors determine some parameters
such as input/output ripple voltage, power efficiency and
maximum supply current by charge pump. To reduce the
input and output ripple effectively, the low ESR ceramic
capacitors are recommended. For LED driver applications,
the input voltage ripple is more important than output
ripple. The input ripple is controlled by input capacitor
CIN, increasing the value of input capacitance can further
reduce the ripple. Practically, the input voltage ripple
depends on the power supply's impedance. The flying
capacitor CFLY1 and CFLY2 determine the supply current
capability of the charge pump that will influence the overall
DS9367C-01 March 2011
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13
RT9367C
output capacitor values. Output capacitor of larger
capacitance can reduce noise and improve load transient
response, stability, and PSRR. The output capacitor should
be located at not more than 0.5 inch from the LDO1 and
LDO2 pin of the RT9367C and returned to a clean analog
ground.
Region of Stable COUT ESR vs. Load Current
VIN = 5V
CIN = COUT1 =
COUT2 = 1uF/X7R
10
1
Stable Range
0.01
Simulation Verify
0.001
0
50
100
150
200
250
300
Load Current (mA)
Figure 4. Stable Cout ESR Range
Thermal Protection
Thermal protection limits power dissipation in RT9367C.
When the operation junction temperature exceeds 170°C,
the OTP circuit starts the thermal shutdown function and
turns the pass element off. The pass element turn on again
after the junction temperature cools by 40°C. The RT9367C
lowers its OTP trip level from 170°C to 110°C when output
short circuit occurs (LDO1 and LDO2 < 0.4V) as shown
in Figure 5. It limits IC case temperature under 110°C and
provides maximum safety to customer while output short
circuit occurring.
V OUT Short to GND
0.4V
V OUT
IOUT
TSD
170 °C 110 C
°
OTP Trip Point
110 °C
80 °C
IC Temperature
Figure 5. Short Circuit Thermal Folded Back Protection
when Output Short Circuit Occurs (Patent)
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14
PD(MAX) = (TJ(MAX) − TA) / θJA
Where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
Unstable Range
0.1
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
For recommended operating conditions specification of
RT9367C, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. For WQFN-20L 3x3 packages, the thermal
resistance θJA is 68°C/W on the standard JEDEC 51-7
four layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula:
PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for
WQFN-20L 3x3 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. For RT9367C packages, the Figure 6 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
1.6
Maximum Power Dissipation (W)
Region
ESR (Ω)
(Ω)
OUT ESR
RegionofofStable
StableCCOUT
100
Thermal Considerations
Four Layers PCB
1.4
1.2
WQFN-20L 3x3
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curves
DS9367C-01 March 2011
RT9367C
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The RT9367C
address is 1010100 (54h) and is a receive-only (slave)
device. The second word selects the register to which
the data will be written. The third word contains data to
write to the selected register.
I2C Compatible Interface
The figure 1 shows the timing diagram of I2C interface.
The RT9367C communicates with a host (master) using
the standard I2C 2-wire interface. The two bus lines of
SCL and SDA must be pulled to high when the bus is not
in use. External pull-up resistors between VCC and SDA/
SCL pin are necessary. The recommended pull-up resistor
value range is from 2kΩ to 10kΩ.
⌧
I2 C Writing Cycles of LDO1
Start
⌧
A6 A5 A4 A3 A2 A1 A0 0
0
0
1
0
0
0
0
1
32-step Voltage Setting
0
0
0 C4 C3 C2 C1 C0
ON/OFF
A6 A5 A4 A3 A2 A1 A0 0
0
0
1
0
0
1
0
32-step Voltage Setting
1
0
I2 C Writing Cycles of LED Driver
0
0 C4 C3 C2 C1 C0
Stop
OR
Channel Selecting
0
x
0
x B3
x B2
x B1
x B0
32-step Current Setting
0
0
0 C4 C3 C2 C1 C0
Stop
LED1
0
1
LED2
0
LED3
A6 A5 A4 A3 A2 A1 A0 0
LED4
Start
Stop
OR
I2 C Writing Cycles of LDO2
Start
⌧
ON/OFF
Figure 7. RT9367C I2C Writing Cycles for LDO and LED Driver
Figure 7 shows the writing information of dual LDO and
LED current. In the second word, the sub-address of dual
LDO is “001” and the sub-address of LED Driver is “010”.
For LDO, the LDO1 address is defined as “000”, LDO2
address is defined as “001”.
2.5
1.75
0
0F
1F
HEX Code
LED Current vs Input Code
3.3
25
Typical LDO Current (mA)
3.3
LDO2 Output Voltage vs Input Code
Typical LDO Output Voltage (V)
Typical LDO Output Voltage (V)
LDO1 Output Voltage vs Input Code
The data of second byte (B0 to B3), a “0” indicates a
DISABLE and a “1” indicates an ENABLE function. The
data of third byte (C0 to C4) indicates a 32-steps setting
of LDO1, LDO2 output voltage or the LED current of
backlight.
2.5
1.8
1.1
0
0E 0F
1F
12.5
0.78
0
HEX Code
0F
1F
HEX Code
Figure 8. LDO Voltage Setting and LED Current Setting
DS9367C-01 March 2011
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15
RT9367C
Table 1. LDO Voltage Setting
LDO2
Code
C4~C0
LDO1
LDO2
2.55
2.55
11000
2.95
2.95
10001
2.60
2.60
11001
3.00
3.00
1.60
10010
2.65
2.65
11010
3.05
3.05
2.30
1.65
10011
2.70
2.70
11011
3.10
3.10
01100
2.35
1.70
10100
2.75
2.75
11100
3.15
3.15
01101
2.40
1.75
10101
2.80
2.80
11101
3.20
3.20
LDO2
Code
C4~C0
LDO1
2.15
1.50
10000
01001
2.20
1.55
1.20
01010
2.25
1.90
1.25
01011
00100
1.95
1.30
00101
2.00
1.35
LDO2
Code
C4~C0
LDO1
1.75
1.10
01000
00001
1.80
1.15
00010
1.85
00011
Code
C4~C0
Voltage (V)
LDO1
00000
Voltage (V)
Voltage (V)
Voltage (V)
00110
2.05
1.40
01110
2.45
1.80
10110
2.85
2.85
11110
3.25
3.25
00111
2.10
1.45
01111
2.50
2.50
10111
2.90
2.90
11111
3.30
3.30
Table 2. LDO Current Setting
Code
LED Current
Code
LED Current
Code
LED Current
Code
LED Current
C4~C0
(mA)
C4~C0
(mA)
C4~C0
(mA)
C4~C0
(mA)
00000
0.8
01000
7.0
10000
13.3
11000
19.5
00001
1.6
01001
7.8
10001
14.0
11001
20.3
00010
2.3
01010
8.6
10010
14.8
11010
21.1
00011
3.1
01011
9.4
10011
15.6
11011
21.8
00100
3.9
01100
10.1
10100
16.4
11100
22..6
00101
4.7
01101
10.9
10101
17.2
11101
23.4
00110
5.5
01110
11.7
10110
17.9
11110
24.2
00111
6.2
01111
12.5
10111
18.7
11111
25.0
Figure 8. illustrates the dual LDOs' output voltage and
LED current setting information. The output voltage of LDO1
could be divided to 32-step levels between 1.75V (HEX
Code = 0) and 3.3V (HEX Code = 1F). And the output
voltage of LDO2 is separated to two regions, one is from
1.1V (HEX Code = 0) to 1.8V (HEX Code = 0E) and the
other is from 2.5V (HEX Code = 0F) to 3.3V (HEX Code =
1F). In addition, the LED current could be divided to 32step levels between 0.8mA (HEX Code = 0) and 25mA
(HEX Code = 1F).
C1P, C1N, C2P, C2N, and GND pin respectively. A short
connection is highly recommended. The following
guidelines should be strictly followed when designing a
PCB layout for the RT9367C.
`
The exposed GND pad must be soldered to a large
ground plane for heat sinking and noise prevention. The
throughhole vias located at the exposed pad is
connected to ground plane of internal layer.
`
VIN traces should be wide enough to minimize
inductance and handle the high currents. The trace
running from battery to chip should be placed carefully
and shielded strictly.
`
Input and output capacitors must be placed close to the
part. The connection between pins and capacitor pads
should be copper traces without any through-hole via
connection.
Layout Consideration
The RT9367C is a high-frequency switched-capacitor
converter. Careful PCB layout is necessary. For best
performance, place all peripheral components as close to
the IC as possible. Place CIN1, CIN2, COUT, CLDO1, CLDO2,
CFLY1, and CFLY2 near to AVIN, PVIN, VOUT, LDO1, LDO2,
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16
DS9367C-01 March 2011
RT9367C
`
The flying capacitors must be placed close to the part.
The traces running from the pins to the capacitor pads
should be as wide as possible. Long traces will also
produce large noise radiation caused by the large dv/dt
on these pins. Short trace is recommended.
`
All the traces of LED and VIN running from pins to LCM
module should be shielded and isolated by ground plane.
The shielding prevents the interference of high frequency
noise coupled from the charge pump.
`
Output capacitor must be placed between VNG and
VOUT to reduce noise coupling from charge pump to
LEDs.
Output capacitor must be
placed between GND and
VOUT to reduce noise coupling
from charge pump to LEDs.
C OUT
GND Plane
LED2
LED3
LED4
20
19
18
17
16
C1N
1
15
NC
C2N
2
14
LDO2
PGND
3
13
AVIN
5
21
PVIN
6
The exposed pad, GND
pad should be connected
to a strong ground plane
for heat sinking and noise
prevention.
7
8
9
12
LDO1
11
AGND
C IN1
All the traces of LED
and VIN running from
chip to LCM module
should be shielded
and isolated by
ground plane.
C LDO2
Battery
10
NC
C1P
ENA
C2P
4
SCL
C FLY2
GND
SDA
C FLY1
LED1
The traces running from pins
to flying capacitor should be
short and wide to reduce
parasitic resistance and
prevent noise radiation.
VOUT
GND Plane
C LDO1
C IN2
GND Plane
Figure 9. PCB Layout Guide
DS9367C-01 March 2011
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17
RT9367C
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
2.900
3.100
0.114
0.122
D2
1.650
1.750
0.065
0.069
E
2.900
3.100
0.114
0.122
E2
1.650
1.750
0.065
0.069
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 20L QFN 3x3 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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DS9367C-01 March 2011