Ordering number : ENA1957 CMOS IC LC749870W Silicon gate NTSC/PAL/SECAM Digital Video Decoder Overview The LC749870W is a digital video decoder that converts NTSC, PAL and SECAM video signals into digital component video signals. Digital video data can be output easily by inputting NTSC, PAL and SECAM video signals. The output data format is compatible with ITU-R BT.656. Features • Supports NTSC (M, 4.43), PAL (B, D, G, H, I, M, N, 60), and SECAM video signal inputs. • On-chip video switch that supports 4 video inputs • 10-bit ADC (sampling at 27MHz) • Automatic gain control (AGC) function • Digital clamp circuit • Digital automatic color control (ACC) circuit • Sync separation circuit • Signal-to-noise (S/N) detection capabilities • Non-standard signal detection function • No signal detection function • Adaptive two-dimensional Y/C separation circuit • NTSC/PAL/SECAM demodulator circuit • Clock rate conversion circuit • Picture quality improvement (sharpness, contrast, brightness, CTI, UV gain, HUE) • 8-bit ITU-R BT.656 output format ITU-R BT.656 (8bit YCbCr 4:2:2 with SAV/EAV) 8bit YCbCr 4:2:2 with Syncs • I2C control (100k/400kbps, 2 types of slave address selectable) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 62911HKPC 20110419-S00002 No.A1957-1/45 LC749870W IC Specifications • Power supply voltage I/O: Analog 3.3V, Digital 1.8V or 3.3V Core: Analog 1.8V, Digital 1.1V • Maximum operating frequency: 30MHz • Package: SQFP64 Applications • Small-size monitors Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter Symbol Maximum supply voltage (I/O) Conditions Ratings unit DVDD33 XVDD33 AVDD33 -0.3 to +3.95 V Maximum supply voltage (Core) DVDD11 -0.3 to +1.8 V Digital input voltage XVDD11 VI -0.3 to DVDD33+0.3 V Digital output voltage VO -0.3 to DVDD33+0.3 V Operating temperature Topr -40 to +85 °C Storage temperature Tstg -55 to +125 °C max unit Allowable Operation Ranges at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter Symbol Conditions min typ Supply voltage (I/O) AVDD33 XVDD33 3.0 3.3 3.6 V DVDD33 1.7 1.8 or 3.3 3.6 V Supply voltage (Core) DVDD11 1.0 1.1 1.2 V Input voltage range XVDD11 VIN DVDD33 V 0 DC Characteristics at Ta = -30 to +70°C, DVDD33 = 1.7 to 3.63V, AVDD33 = 3.0 to 3.63V, DVDD11 = 1.0 to 1.2V Parameter Symbol Conditions min typ max unit Input high-level voltage VIH CMOS level inputs 0.7DVDD33 CMOS level Schmitt inputs 0.7DVDD33 Input low-level voltage VIL CMOS level inputs 0 0.3DVDD33 V CMOS level Schmitt inputs 0 0.3DVDD33 V 10 μA Input high-level current IIH V V VI = VDD VI = VDD, with pull-down resistance 100 μA -10 μA VDD-0.4 V Input low-level current IIL VI = VSS Output high-level voltage VOH CMOS (Pin E/G: IOH = -4mA, F: IOH = -6mA) Output low-level voltage VOL CMOS Output leakage current IOZ When in high-impedance output mode Pull-down register RDN DVDD11 = 1.1V, DVDD33 = 3.3V 159 kΩ DVDD11 = 1.1V, DVDD33 = 1.8V 95 kΩ Operating current drain IDDOP Output open, tck=27MHz, natural image. 42 mA Ta = 25°C, DVDD33 = 1.8V, 38 mA AVDD33 = 3.3V, DVDD11 = 1.1V Output open, VI = VSS, Ta = 25°C 10 μA Ta = 25°C, DVDD33 = 3.3V, -10 0.4 V 10 μA AVDD33 = 3.3V, DVDD11 = 1.1V Output open, tck=27MHz, natural image. Static current drain *1 IDDST *1: There is an input pin which builds in pull down resistance. Note that there is no guarantee about static consumption current depending on circuit configuration. No.A1957-2/45 LC749870W Package Dimensions unit : mm (typ) 3190A 12.0 0.5 10.0 48 33 64 12.0 32 10.0 49 17 1 16 0.5 0.15 0.18 0.1 1.7max (1.5) (1.25) SANYO : SQFP64(10X10) DVDD33 DVDD11 GPIO3 DVSS GPIO1 VS CK13 HS DE GPIO2 DVDD11 FIELD DVSS XVSS XVDD11 XOUT Pin Assignment 64 1 49 48 LC749870W 16 17 33 32 XIN XVDD33 XVSS AFEVRTC SVO AVSS33 AIN0 AVDD33 AIN1 AVSS33 AIN2 AVDD33 AIN3 AVSS33 VRB VRT INTREQ DVSS MD0 DVSS MD2 SCL MD1 SDA RESET PDWN DVDD11 TEST DVSS DVSS REFPKV REFNKV CKO DVSS GPIO0 DATA6 DATA4 DATA7 DVSS DATA5 DATA3 DATA2 DATA1 2 I CSEL DATA0 DVSS DVDD11 DVDD33 Top view No.A1957-3/45 LC749870W Pin Descriptions Pin No. 1 I/O Type Symbol CKO Connected to I/O Type O F CMOS Notes Digital Data synchronous clock output 2 DVSS P GND Digital 3 GPIO0 I/O G CMOS Digital For test 4 DATA6 I/O G CMOS Digital Video signal output 5 DATA4 I/O G CMOS Digital Video signal output 6 DATA7 I/O G CMOS Digital Video signal output (MSB) 7 DVSS P GND Digital 8 DATA5 I/O G CMOS Digital Video signal output 9 DATA3 I/O G CMOS Digital Video signal output 10 DATA2 I/O G CMOS Digital Video signal output 11 DATA1 I/O G CMOS Digital Video signal output Digital I2C slave select L = 0x88, H = 0x8A Video signal output (LSB) 2 12 I CSEL I C CMOS 13 DATA0 I/O G CMOS Digital 14 DVSS P GND Digital 15 DVDD11 P Core voltage Digital 16 DVDD33 P I/O voltage Digital 17 INTREQ O E CMOS Digital 18 DVSS P GND Digital 19 MD0 I D CMOS Digital 20 DVSS P GND Digital 21 MD2 I D CMOS Digital For test (Connect to GND) 22 SCL I D CMOS Digital I2C clock 23 MD1 I D CMOS Digital For test (Connect to GND) 24 SDA I/O G CMOS Digital I2C data input/output 25 RESET I B CMOS Digital System reset (“L” active) 26 PDWN I B CMOS Digital Power down control 27 DVDD11 P Core voltage Digital For test (Connect to GND) 28 TEST I CMOS Digital 29 DVSS P GND Digital 30 DVSS P GND Digital 31 REFPKV I A Analog ADC top reference buffer-amp input 32 REFNKV I A Analog ADC bottom reference buffer-amp input 33 VRT I A Analog ADC top reference voltage input A Analog ADC bottom reference voltage input 34 VRB I 35 AVSS33 P 36 AIN3 I 37 AVDD33 P C Interrupt (“H” active) GND A Analog Analog Analog Voltage A For test (Connect to GND) Video signal input (CVBS) Analog 38 AIN2 I 39 AVSS33 P Analog 40 AIN1 I 41 AVDD33 P 42 AIN0 I 43 AVSS33 P 44 SVO O A Analog AFE SVO output 45 AFEVRTC I A Analog ADC D-range control voltage external input 46 XVSS P 47 XVDD33 P I/O Voltage Digital 48 XIN I H CMOS Digital X’tal input 49 XOUT O H CMOS Digital X’tal output 50 XVDD11 P Core Voltage Digital GND A Analog Analog Voltage A GND Video signal input (CVBS) Analog Analog GND Video signal input (CVBS) Analog Video signal input (CVBS) Analog Digital Continued on next page. No.A1957-4/45 LC749870W Continued from preceding page. Pin No. I/O Type Pin symbol I/O 51 XVSS Connected to P 52 DVSS P 53 FIELD I/O 54 DVDD11 P 55 GPIO2 I/O 56 DE 57 HS 58 Notes Type GND Digital GND Digital CMOS Digital Core voltage Digital G CMOS Digital For test I/O G CMOS Digital Data enable signal I/O G CMOS Digital Horizontal sync signal CK13 O F CMOS Digital Clock output (13.5MHz) 59 VS I/O G CMOS Digital Vertical sync signal 60 GPIO1 I/O G CMOS Digital For test 61 DVSS P GND Digital 62 GPIO3 I/O CMOS Digital 63 DVDD11 P Core voltage Digital 64 DVDD33 P I/O voltage Digital G G Field signal For test No.A1957-5/45 LC749870W Pin Circuits I/O type A Function Analog input/output Equivalent Circuit Applicable Pins AIN0, AIN1, AIN2, AIN3, VRT, VRB, REFPKV, REFNKV, SVO, AFEVRTC B Schmitt trigger CMOS input PDWN, RESET C CMOS input with built-in I2CSEL, TEST pull-down resistor D E CMOS input SCL, MD0, MD1, MD2 2mA/4mA switching INTREQ 3-STATE drive CMOS output F 4mA/8mA switching CKO, CK13 3-STATE drive CMOS output G 2mA/4mA switching SDA, 3-STATE drive CMOS GPIO0, GPIO1, GPIO2, GPIO3, input/output DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, FIELD, DE, VS, HS H Oscillator XIN, XOUT No.A1957-6/45 LC749870W Pin Connection 1) ADC and its peripherals REFPKV VRT VRB REFNKV 0.1μF AIN* 0.1μF 10μF 10μF 0.1μF AFEVRTC Capacitors must be placed as close as possible to the IC. 2) Unused Pin Handling (Please be sure to perform except input open processing) AIN0 to AIN3: Open PDWN: Pull up TEST, MD0, MD1, MD2: Pull down RESET: Must always be configured for input. GPIO0 to GPIO3: Open DATA0 to DATA7: Open FIELD, DE, VS, HS: Open CKO, CK13: Open INTREQ: Open SVO: Open No.A1957-7/45 PDWN TEST AIN3 AIN2 AIN1 AIN0 RESET XIN AFE + ADC 1ch 2 IC Data Interpolation LPF APC AGC Timing Gen Digital Clamp Sync Separation 2D Y/C Separation SRAM NT/PAL Demodulation SECAM Demodulation SRAM LC749870 MUX Clock Rate Conversion SRAM CTI HUE UV Gain Sharpness Contrast Brightness Output Formatter INTREQ FIELD DE VS HS DATA[7:0] CK13 CKO LC749870W Block Diagram SDA SCL I CSEL 2 No.A1957-8/45 LC749870W Input/Output Timing 1) Input clock timing tCK tHI DVDD33/2 XIN tLI Pin Name XIN Parameter Clock cycle Symbol min typ tCK Duty max unit 37 ns 50 % 2) Output data timing tHO tCK DVDD33/2 CKO tLO tAC Output data DVDD33/2 Pin Name CKO Parameter Clock cycle Symbol min typ tCK Duty Output data delay time max unit 37 ns 50 % tAC -3 3 ns tAC -3 6 ns tAC -5 4 ns tAC -6 9 ns (DVDD33 = 2.6 to 3.6V) Pins E,G: 4mA setting Pin F: 8mA setting Output data delay time DATA*, HS,VS,DE,FIELD, INTREQ (DVDD33 = 2.6 to 3.6V) Pins E,G: 2mA setting Pin F: 4mA setting Output data delay time (DVDD33 = 1.7 to 1.9V) Pins E,G: 4mA setting Pin F: 8mA setting Output data delay time (DVDD33 = 1.7 to 1.9V) Pins E,G: 2mA setting Pin F: 4mA setting No.A1957-9/45 LC749870W Register Specifications BANK0 (AFE + ADC) Register Specification Subaddress Bit- Bit Name 7 I2C_BGRPWDB 1 6 I2C_SVOPWDB 1 5 4 I2C_ SELFCLPPWDB I2C_AFEPWDB Size Function Name 0: Power down 0: SVO AMP circuit OFF 1 0: Self clamp OFF 01H 02H 03H 04H 05H 1 0 1 0: AFE power down Power down control 0: Power down 0: Power down 2 Input switch control 4 I2C_CLPLPFON 1 LPF enable control 3:2 - 2 For test 1:0 - 2 For test 7 I2C_SCARTON 1 AGC mode control 6 - 1 For test 5:0 - 6 For test 7 - 1 For test 3:1 - 3 For test 0 - 1 For test 5:4 - 2 For test 3 - 1 For test 2:0 - 3 For test 1 4 - 1 1: Normal operation 1: Normal operation 0: Power down 01: AIN1 11: AIN3 LPF enable control of AFE self clamp circuit 0: LPF OFF For test For test 0H Normally set to 0H AFE D-range control voltage external input select control 1: Non-AGC mode For test Normally set to 0H For test Normally set to 00H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 1H For test Normally set to 4H Normally set to 0H For test Normally set to 0H For test Normally set to 0H 0H 0H Normally set to 0H 0: AGC mode 0H 0H 1: LPF ON For test For test 10: AIN2 0H 0H 1: Normal operation AFE 4-input selector control signal (when in normal operation) 00: AIN0 0H 0H 1: Normal operation LPF buffer circuit power down control I2C_AINSEL 5 1: Normal operation Clock generation circuit power down control 6:5 1 0: Power down Reference voltage generation circuit 2 power down control 1 6 ×2 AMP circuit and ×2 AMP bias circuit power down control 0: Power down I2C_LPFPWDB 1 0H 1: AFE normal operation Reference voltage generation circuit 1 power down control 7 7 0H 1: Self clamp ON AFE power down control I2C_ADCPWDB 1 0H 1: SVO AMP circuit ON AFE self clamp circuit power down control 00H 2 0H 1: Normal operation AFE SVO AMP power down control 1 1 value Band gap reference power down control 1 3 Initial Functions 0H 0H 00H 0H 0H 0H 0H 0H 0H 0H 0H 0H Reserved 0H 3 1 Reserved 0H 2 1 Reserved 0H 1 1 Reserved 0H 0 1 For test Normally set to 0H 0H Continued on next page. No.A1957-10/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Function Name For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 06H - For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test For test 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H Clock output 1 I2C_IOSEL2 1 0 I2C_IOSEL1 1 - - - - 7 I2C_SRST 1 Soft reset 0 - 1 For test 7:6 - 2 For test 1:0 - 2 For test 0 I2C_CKINV 1 6:4 - 3 2:0 - 3 14H 7:0 - 8 15H 7:0 - 8 16H 7:0 - 8 09H to Normally set to 0H Normally set to 0H 07H 08H Functions current drive capability Signal output current drive capability Clock output current drive capability switching 0: 4mA 1: 8mA Signal output current drive capability switching 0: 2mA 1: 4mA - Initial value 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H - 0FH 10H 11H 12H Clock output invert Software reset of digital video signal processing block 0: Reset ON 1: Reset OFF For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H Clock output (CKO) invert control 0: Normal 1: Invert For test Normally set to 0H 13H For test Normally set to 0H For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 0H 0H 0H 0H 0H 0H 0H 00H 00H 00H No.A1957-11/45 LC749870W BANK1 (Digital Video Signal Processing Block 1) Register Specifications Subaddress Bit- Bit Name 5:4 - 2 For test 0 - 1 For test 7:6 I2A_ACCON 2 ACC control 5:4 I2A_ACCFRAME 2 3:0 - 4 7:3 I2A_ACCSELAMP 5 2:0 I2A_TMCTRL 3 Size Function Name 00H 01H Number of update frames For test ACC amplifier fixed mode 02H value For test 0H Normally set to 0H For test 0H Normally set to 0H ACC ON/OFF switching 00: OFF 01: ON 1H 1x: Amplifier fixed Number of update frame select 00: 1 frame 01: 2 frames 10: 4 frames 11: 8 frames For test ACC amplifier fixed mode Gain adjustment 0H 0H Normally set to 0H 00H -5 to +26dB Auto/manual mode switching Auto mode switching 000: Auto 100: PAL-M 03H 7:0 - 8 For test 04H 7:0 - 8 For test 05H 7:0 - 8 06H 7:0 - 8 07H 7:0 - 8 For test 08H 7:0 - 8 For test 09H 7:0 - 8 For test 7:5 - 3 For test 4 - 1 For test 3:0 - 4 For test 7:4 - 4 0BH - 4 7 - 1 For test 6:0 - 7 For test 0DH 7:0 - 8 For test 0EH - - - - 0FH 7:0 - 8 For test 10H 7:0 - 8 For test For test 4 7:6 - 2 5:4 - 2 12H - 1 2:0 - 3 Normally set to 80H Normally set to 40H For test For test Normally set to 80H For test Normally set to 00H For test Normally set to 80H For test Normally set to 5H For test Normally set to 0H For test Normally set to 2H Normally set to 3H For test For test Normally set to 0H For test Normally set to 18H For test Normally set to A0H For test Normally set to 60H For test Normally set to 80H Normally set to CH For test Normally set to 8H For test For test Normally set to 3H For test For test 3 For test For test 4 3:0 Normally set to 20H Normally set to 3H 0CH - For test For test 3:0 11H 101: PAL-N Normally set to 10H For test 7:4 001: NTSC-M For test For test 0AH Initial Functions Normally set to 3H For test Normally set to 1H For test For test Normally set to 0H 010: NTSC-4.43 110: PAL-60 011: PAL 0H 111: SECAM 20H 80H 40H 10H 80H 00H 80H 5H 0H 2H 3H 3H 0H 18H A0H 60H 80H CH 8H 3H 3H 1H 0H Continued on next page. No.A1957-12/45 LC749870W Continued from preceding page. Sub- Bit- Bit Name 6:4 - 3 For test 1:0 - 2 For test 14H 7:0 - 8 15H 7:0 - 8 16H 7:0 - 8 address Size Function Name 13H Initial Functions value For test 0H Normally set to 0H For test 2H Normally set to 2H For test 96H Normally set to 96H For test For test 64H Normally set to 64H For test 64H Normally set to 64H Auto mode switching (It takes effect at I2A_TMCTRL=3’h0.) 0000: Manual mode 0001: Auto0 (NTSC/PAL) 0010: Auot1 (PAL/SECAM) 0011: Auto2 (NTSC/PAL-N/PAL-M) 7:4 I2A_ATMODE 4 Video system auto-detect switch 0100: Auto3 (NTSC/PAL/SECAM) FH 0101: Auto4 (NTSC/PAL/SECAM/PAL-N/PAL-M) 0110: Auto5 (Auto0+NTSC-443/PAL-60) 0111: Auto6 (Auto1+NTSC-443/PAL-60) 1000: Auto7 (Auto2+NTSC-443/PAL-60) 17H 1001: Auto8 (Auto3+NTSC-443/PAL-60) 1010: Auto9 (Auto4+NTSC-443/PAL-60) 1011 to 1111: Full Fsc select at manual mode 3:2 I2A_FSCSEL 2 1 I2A_SCANSEL 1 0 I2A_NTPALSEL 1 7:6 - 2 Fsc select Scanning line number select at manual mode 0: 525i NTSC/PAL select 1CH 1H 0H 1: 625i NTSC/PAL select at manual mode 0: NTSC 0H 1: PAL For test 5:4 - 2 1 - 1 For test 0 I2A_SECAMSEL 1 SECAM select 6:0 - 7 3H Normally set to 3H For test 0H Normally set to 0H For test 1H Normally set to 1H SECAM select at manual mode 0: not SECAM 0H 1: SECAM For test For test 1BH 11: 3.58205625MHz Scanning line 18H 1AH 01: 4.43361875MHz 10: 3.57561149MHz number select For test 19H 00: 3.579545MHz 6:0 - 7 2 I2A_DCON 1 1 I2A_DCLINE 1 0 - 1 For test 6:0 I2A_STDLEVY 7 Pedestal level setting 7:5 I2A_TCDC 3 Time constant setting 7FH Normally set to 7FH For test 00H Normally set to 00H Digital clamp Digital clamp ON/OFF setting 1H ON/OFF setting 0: OFF Detection level Pedestal level update unit switching update unit switching 1: ON 0: Each frame 0H 1: Each line For test 0H Normally set to 0H Target pedestal level setting 40H Level setting range: 236 to 363LSB Digital clamp time constant setting 000: Time constant none 100: 1/16 1DH Update field 4:0 I2A_FRAMEDC 5 1EH 6:0 - 7 For test 1FH 4:0 - 5 For test number setting 101: 1/32 001: 1/2 110: 1/64 010: 1/4 Pedestal level update field number setting Setting range: 0 to 31 fields For test Normally set to 00H For test Normally set to 17H 011: 1/8 0H 111: 1/128 10H 00H 17H Continued on next page. No.A1957-13/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Initial Functions value LPF characteristic switching for sync separation 7 6 I2A_FILSEL I2A_AUTOFIL 1 1 20H LPF characteristic switch LPF characteristic auto-switching setting 5 - 1 For test 4 - 1 For test 3:0 - 4 7:0 - 8 7 - 1 - 5 22H 1 0: OFF 1H 1: ON For test 1H Normally set to 1H For test 0H Normally set to 0H FH Normally set to FH For test 55H 1H Normally set to 1H For test 0: Auto setting 0H 0H 1: Manual setting Input signal line number auto/manual setting 0: Auto setting Input signal system 3 separation Input signal system auto/manual setting 1 I2A_TVMODE 1.4MHz LPF characteristics automatic switching setting for sync Normally set to 0H I2A_MANMODE 2:0 1: Cutoff frequency 1H For test 1 4 0.35MHz Normally set to 55H For test 6 0: Cutoff frequency For test For test 21H (It takes effect at I2A_AUTOFIL = 1’b0.) setting 0H 1: Manual setting Input signal system setting (It takes effect at I2A_MANMODE[1] = 1’b1) 000: NTSC-M 001: PAL-M 011: PAL-GBI 100: SECAM 0H 010: PAL-N Input signal line number setting 6 I2A_INSIG 1 (It takes effect at I2A_MANMODE[0] = 1’b0) 0: 625 lines 23H 5:4 - 2 For test 3:0 - 4 For test 7 I2A_SLDET 1 Slice level setting 5:4 I2A_TCLEV 2 24H Slice level time constant setting 1H 1: 525 lines For test 1H Normally set to 1H For test 1H Normally set to 1H Sync separation slice level auto-setting 0: Manual setting 1H 1: Auto setting Slice level time constant setting 00: 1/2 01: 1/4 10: 1/8 1H 11: 1/16 Slice level initial value setting 3:2 I2A_LEVAD 2 Initial slice level setting 00: 60LSB 01: 80LSB 10: 100LSB 11: 120LSB As for an initial value of the slice level, the above value is 3H added to the detected sync tip level. Slice level Level setting 25H 7:0 I2A_SLST 8 range: 236 to 363LSB setting 7:4 - 4 3:0 - 4 7:4 - 4 3:2 - 2 - 2 7:4 - 4 28H For test - 4 08H Setting range: 0 to 1020LSB For test Normally set to 9H For test Normally set to 7H For test Normally set to 3H For test Normally set to 0H For test For test 3:0 Settable in 4 LSB units Normally set to 7H For test 1:0 (It takes effect at I2A_SLDET = 1’b0) For test 26H 27H Slice level setting Normally set to 3H For test Normally set to 1H 7H 9H 7H 3H 0H 3H 1H Continued on next page. No.A1957-14/45 LC749870W Continued from preceding page. Subaddress 29H Bit- Bit Name 7 - 1 6:4 - 3 Size Function Name For test - 3 2AH 7:0 - 8 2BH 7:0 - 8 For test - 8 2DH 7:0 - 8 2EH 6:4 - 3 2FH 5:0 - 6 30H 5:0 - 6 31H 7:0 I2A_HSPAD 8 H-sync positioning 7 - 1 For test 6 - 1 4 - 1 Normally set to 03H For test Normally set to 4H For test For test Normally set to 02H For test Normally set to 01H H-sync position adjustment For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test 3:0 - 4 33H 7:0 - 8 For test 34H 7:0 - 8 For test 35H 7:0 - 8 For test 6 - 1 For test 5 - 1 For test 4 I2A_FIXLN 1 Normally set to 1H For test Normally set to 0H Line number fixed mode ON/OFF setting 37H For test For test For test 36H Normally set to 14H Normally set to 00H For test 1 For test Normally set to 04H 7:0 - Normally set to 1H For test 2CH 5 Normally set to 1H Normally set to 7H For test 32H For test For test For test 2:0 Functions For test Normally set to CBH For test Normally set to CAH For test Normally set to CDH For test Normally set to 1H For test Normally set to 0H Line number fixed mode ON/OFF setting 0: OFF 1: ON Initial value 1H 1H 7H 04H 14H 00H 03H 4H 02H 01H 05H 0H 1H 1H 1H 0H CBH CAH CDH 1H 0H 1H 2:0 I2A_VSTART 3 V-sync positioning V-sync position adjustment 3H 7:5 I2A_VBSTART 3 V-blank positioning V-blank position adjustment 3H H-blank rising position adjustment 0FH V-blank width adjustment 3H H-blank falling position adjustment 0FH 4:0 I2A_HBSTART 5 7:5 I2A_VBWIDTH 3 4:0 I2A_HBEND 5 38H H-blank rising positioning V-blank width adjustment H-blank falling positioning Continued on next page. No.A1957-15/45 LC749870W Continued from preceding page. Sub- Bit- Bit Name 39H 7:0 - 8 For test 3AH 7:0 - 8 For test 3BH 7:0 - 8 For test 3CH 7:0 - 8 For test 3DH 7:0 - 8 For test 3EH 7:0 - 8 For test 3FH 7:0 - 8 For test 40H 7:0 - 8 For test 41H 7:0 - 8 For test 42H 7:0 - 8 For test 43H 7:0 - 8 For test address 7 Size Function Name No signal detection I2A_NSDON 1 ON/OFF setting 44H 45H 46H - 1 For test 3:2 I2A_NSDTHH 2 No signal detection 1:0 I2A_NSDTHL 2 threshold setting 5 - 1 For test 3:2 - 2 For test 1:0 - 2 For test 4:0 - 5 5:0 - 6 For test 5 - 1 For test 3 - 1 For test 2 - 1 For test 1 I2A_EXAGCON 1 7:0 - 8 External AGC ON/OFF setting For test 7:0 - 8 4BH 7:0 I2A_SYNLEV 8 6:4 I2A_FRMCNT 3 3:0 I2A_FIXGAIN 4 4CH 24H Normally set to 24H For test F1H Normally set to F1H For test 93H Normally set to 93H For test 50H Normally set to 50H For test 30H Normally set to 30H For test 18H Normally set to 18H For test 25H Normally set to 25H For test 23H Normally set to 23H For test C8H Normally set to C8H 0: OFF Forced no signal mode ON/OFF setting Update field number setting Fixed gain setting 1H (It takes effect at I2A_NSDON[1] = 1’b0) 1: ON For test 0H Normally set to 0H Threshold setting where signals can be measured 0H Threshold setting where no signal can be measured 1H For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H Normally set to 10H For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H External AGC ON/OFF setting 0: OFF 1: ON Normally set to 00H For test Normally set to 00H Sync level setting 1H 1: ON For test For test 4AH 10H Normally set to 10H Normally set to 3FH 48H 49H 50H Normally set to 50H For test For test 47H For test 0: OFF 4 value No signal detection ON/OFF setting 1 6 Initial Functions AGC target sync level setting Setting range: 158 to 413LSB AGC update field number setting Fixed gain setting Setting range: -6 to +9dB 0H 1H 1H 10H 3FH 0H 0H 0H 0H 00H 00H 80H 0H 6H Continued on next page. No.A1957-16/45 LC749870W Continued from preceding page. Subaddress Bit- Bit Name 7:6 I2A_TCAGC 2 4:0 I2A_EXAGCINIT 5 7:6 I2A_AMPLIMIT 2 4:0 - 5 Size 4DH 4EH Function Name Time constant setting External AGC gain value setting Amplifier limit switching For test Initial Functions value AGC time constant setting 00: No time constant 01: 1/2 10: 1/4 0H 11: 1/8 External AGC initial gain value setting 0FH AGC amplifier limit switching 00: ±3dB 01: ±6dB 10: ±9dB 0H 11: ±12dB For test 00H Normally set to 00H Noise detection results update field number setting 7:5 I2A_NLFIELD 3 4FH Update field number setting 4:0 - 5 For test 5:4 - 2 For test 3:0 - 4 For test I2A_NLTH 15 50H 51H 6:0 52H 7:0 Noise detection threshold setting 000: 1 field 001: 2 fields 010: 4 fields 011: 8 fields 100: 16 fields 101: 32 fields 110: 64 fields 111: 128 fields 0H For test 0FH Normally set to 0FH For test 2H Normally set to 2H For test 0H Normally set to 0H Threshold value setting of noise detection 0C80H System detection select 5:4 I2A_SELNTPAL 2 System detection select 00: Both NTSC/PAL (Line number is distinguished.) 01: Only NTSC 0H 10: Only PAL 11: Both NTSC/PAL 53H System 2 I2A_AUTODET 1 auto-detection ON/OFF setting Non-standard 0 I2A_NOSTDDET 1 detection ON/OFF setting System auto-detection ON/OFF setting 0: OFF 1: ON Non-standard detection ON/OFF setting 0: OFF 1: ON 0H 0H Input signal system designation 54H 1:0 I2A_HSELFORMAT 2 System designation (It takes effect at I2A_AUTODET = 1’b0) 00: 576i 01: 480i 10: 576i (Non-standard) 5 - 1 For test 4 - 1 For test 3:2 - 2 For test 1:0 - 2 For test 6:4 - 3 For test 2:0 - 3 For test 6:4 - 3 For test 3 - 1 For test 2 - 1 55H 56H 57H - 2 Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 3H For test Normally set to 0H For test Normally set to 0H For test Normally set to 5H For test Normally set to 1H For test For test 1:0 For test Normally set to 0H For test Normally set to 2H 1H 11: 480i (Non-standard) 0H 0H 0H 3H 0H 0H 5H 1H 0H 2H Continued on next page. No.A1957-17/45 LC749870W Continued from preceding page. Sub- Bit- Bit Name 58H 7:0 - 8 59H 5:0 - 6 5AH 7:0 - 8 5BH 5:0 - 6 address Size Function Name For test Normally set to 0CH For test Normally set to 32H For test Normally set to F0H For test For test 5C 7:0 - 8 6:4 - 3 2:0 - 3 7:0 - 8 7:6 - 2 5:4 - 2 3:2 - 2 1:0 - 2 Normally set to 4H For test Normally set to 3H For test Normally set to 0AH For test Normally set to 3H For test Normally set to 3H For test Normally set to 3H For test For test - 2 5:4 - 2 3:2 - 2 1:0 - 2 7:4 - 4 Normally set to 3H For test Normally set to 3H For test Normally set to 3H 60H 61H For test For test 5FH 7:6 Normally set to 05H Normally set to 28H 5DH 5EH Functions For test Normally set to 3H For test Normally set to 3H For test For test 3:0 - 4 62H to - - - - 6FH 70H 1:0 - 10 For test 71H 7:0 72H 0 NOSIG 1 No signal detection 73H to - - - - 7 NLDOUT 1 Normally set to 0H For test Normally set to 0H Initial value 0CH 32H F0H 05H 28H 4H 3H 0AH 3H 3H 3H 3H 3H 3H 3H 3H 0H 0H - - Read only - No signal detection result Read only - - - 74H 75H 6:0 76H 7:0 77H 0 78H S/N detection result Read only S/N detection NLDET 15 - 1 Noise level Read only For test Read only System detection result 5:4 HSYSFORMAT 2 System detection 1 - 1 For test Read only 0 - 1 For test Read only Read only - - Continued on next page. No.A1957-18/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Functions Initial value Non-standard detection result (H) 3 DOUTH When non-standard is detected in field-blanking period 1 0: Normal 1: Special reproduction - Read only Non-standard detection result (H) 2 DOUTH2 1 79H Non-standard detection 1 DOUTV 1 0: Standard 1: Non-standard - Read only Non-standard detection result (V) 0: Standard 1: Non-standard - Read only Stability judgment result 0 DOUTSTA 1 0: Stable 1: Unstable - Read only 7AH 7BH 4:0 - 5 For test to - - - - 8BH 0 - 1 For test 8CH 0 - 1 For test 8DH - - - - 8EH 0 - 1 For test Read only - - - 8AH For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H 0H 0H 0H No.A1957-19/45 LC749870W BANK2 (Digital Video Signal Processing Block 2) Register Specification Subaddress Bit Name 7 - 6 00H 5:3 I2BYC_ SOFTRESET I2BYC_ SEL_FORMAT 2 1 I2BYC_INSEL 0 BitSize Function Name 1 For test 1 Soft reset 3 Input switching setting 1 For test 1 For test 1 Input switching setting - 8 For test 02H 7:0 - 2 For test 7:6 2 5 1 1 3:0 4 7:4 4 3 1 - 1 1 0H Input switching (It takes effect at I2BYC_INSEL[0] = 0) 000: NTSC 010: PAL-M 110: PAL-N xx1: SECAM 100: PAL 0H For test 1H Normally set to 1H For test 1H Normally set to 1H Input switching setting 0: I2BYC_SEL_PAL[7:6] 1H 1: INSEL(input port) For test 16H Normally set to 16H For test 16H Normally set to 16H 3H For test 0H Normally set to 0H For test 1H Normally set to 1H For test 4H Normally set to 4H For test 4H Normally set to 4H For test 0H Normally set to 0H For test For test 0H Normally set to 0H For test 1 0H Normally set to 0H For test 0H Normally set to 0H 7 1 6:5 2 4 1 I2BYC_2DCOMB2 3 1 2 1 For test Vertical high region line comb setting For test 1:0 2 7:5 3 3 1 1 0 1 0H Normally set to 0H Line comb vertical high region element BSF coefficient select 00: BSF1 01: BSF2 10: BSF3 For test Normally set to 0H Dot interference Dot interference reduction BSF 0: OFF 1: ON For test Normally set to 1H For test Normally set to 2H For test Normally set to 2H For test For test 1 For test reduction setting For test 06H Y/C separation is initialized on the rising edge of the register Normally set to 3H 0 05H 0H Normally set to 0H For test For test 4 2 For test clock 7:0 04H value Soft reset 01H 03H Initial Functions Normally set to 0H For test Normally set to 0H For test Normally set to 0H 11: BSF4 3H 0H 1H 1H 2H 2H 0H 0H 0H Continued on next page. No.A1957-20/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize 7 1 6 1 5 1 4 1 07H I2BYC_2DCOMB4 3 Function Name For test Cross color reduction ON/OFF 09H 1 For test 0 1 For test 7 1 For test 6 1 For test 5 1 1 0 1 7 1 6 - 0AH 7 1 6 1 5 1 4 I2BYC_2DCOMB8 1 1 0 1 7:4 4 0BH - For test 4 7:4 4 0CH 3:0 1H For test 1H Normally set to 1H For test 0H Normally set to 0H For test 0H Normally set to 0H For test 1H Normally set to 1H 1H 1H For test 1H Normally set to 1H For test 1H Normally set to 1H For test 1H Normally set to 1H For test For test 1H Normally set to 1H For test 1H Normally set to 1H For test 1H Normally set to 1H One dimensional filter setting Adaptive two dimensional filter 0: Two dimensional For test Normally set to 1H For test Normally set to 1H For test Normally set to 1H For test Normally set to 3H For test Normally set to 1H For test Normally set to 1H For test For test 3:0 For test Normally set to 1H For test 2 1H Normally set to 1H For test 1 3:2 0H 1: ON Normally set to 1H For test 1 0: OFF For test 1 5 Cross color reduction Normally set to 1H 1 1 1H For test 1 2 1H Normally set to 1H Normally set to 1H 1 3:2 For test For test 1 - 1H Normally set to 1H 2 4 value For test For test 08H Initial Functions Normally set to 4H For test Normally set to 4H For test For test 4 Normally set to 7H For test Normally set to 8H 0DH 7:0 - 8 For test 0EH 7:0 - 8 For test For test Normally set to 0CH For test Normally set to 14H enable/disable setting 1: Adaptive two dimensional 1H 1H 1H 1H 3H 1H 1H 4H 4H 7H 8H 0CH 14H Continued on next page. No.A1957-21/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Initial Functions value Vertical enhancer gain setting 0FH 7:4 I2BYC_2DVENH 3:0 10H 11H 12H 13H 14H 7:0 4 setting - 8 1 6 1 5 1 - 1 2 1 1 1 0 1 7 1 6 1 5 1 4 - 1 2 1 1 1 0 1 7 1 5 1 4 1 3 - 1 2 1 1 1 0 1 0 - 1 For test 001: 2/8 times to 0111: 8/8 times to 1111: 16/8 times For test Normally set to 4BH For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test For test Normally set to 0H For test Normally set to 0H For test Normally set to 1H For test Normally set to 1H For test 0H 000: OFF Vertical enhancer coring setting 4 7 4 Vertical enhancer For test Normally set to 0H 0H 4BH 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 1H 1H 0H Continued on next page. No.A1957-22/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name 7 1 For test 6 1 For test 5:4 2 15H 16H 1 1 7:4 4 3:1 I2BYC_1DFIL 0 17H to 3 1 0H Normally set to 0H For test 0H Normally set to 0H 0H For test For test 1 For test Normally set to 0H 1 2 value For test 3 Initial Functions 0H Normally set to 0H For test 0H Normally set to 0H For test 0H Normally set to 0H One dimensional BPF select BPF for SECAM select One dimensional filter ON One dimensional BPF select 4H 000: BPF0 to 1011: BPF11 One dimensional BPF select for SECAM 2H 000: BPF0 to 111: BPF7 One dimensional filter ON/OFF setting 0: Line comb filter 0H 1: One dimension filter - - - - - - 7:0 - 8 For test 5 - 1 For test 4 - 1 For test 3 - 1 For test 2:0 - 3 For test 22H to - - - - 25H 26H 7:0 I2BCD_UGAIN 8 Cb gain setting Gain control of Cb signal 80H 27H 7:0 I2BCD_VGAIN 8 Cr gain setting Gain control of Cr signal 80H 28H - - - - 1FH 20H 21H 4:3 - 2 2:0 - 3 For test 29H 7:0 - 8 2BH - - - 2CH Normally set to 2CH For test 0H Normally set to 0H For test 1H Normally set to 1H For test 1H Normally set to 1H For test 0H Normally set to 0H - - - - For test 0H Normally set to 0H For test For test 2AH For test 0H Normally set to 0H For test 80H Normally set to 80H - 2CH 7:0 - 8 For test 2DH to - - - - 3 - 1 For test - - For test 80H Normally set to 80H - - 2FH 30H 2 1:0 31H 7:0 32H 3:0 33H 1:0 I2BAC_ SW_ACC_NTPAL I2BAC_ACC_ON I2BAC_ ACC_BSTLV I2BAC_ ACC_TIMCON - 1 2 ACC NTSC/PAL setting ACC ON 0H Normally set to 0H 0: NTSC = 286LSB 1: PAL = 300LSB 0H (when ACC_BSTLV is center value) ACC ON/OFF setting 1H 00: OFF 01: ON 1x: Gain fix ACC target value setting 8 ACC setting 4 2 For test Maximum value of time constant, characteristics select Setting range: 1 time to 16 times For test 80H 158 to 413LSB For test Normally set to 0H 3H 0H Continued on next page. No.A1957-23/45 LC749870W Continued from preceding page. Subaddress Bit Name BitSize Function Name Initial Functions value Color killer ON/OFF setting 0000: OFF 0001: ON by APC 0010: ON by ACC 0011: ON by APC + ACC 34H 3:0 I2BAC_CKILL_ON 7H 0100: ON at the time of noncompliant signal input 4 0101: ON by APC and at the time of noncompliant signal input Color killer setting 0110: ON by ACC and at the time of noncompliant signal input 0111: ON by APC + ACC and at the time of noncompliant signal input 1xxx: Forced ON 35H 4:0 I2BAC_CKILL_LV I2BAC_ 5 Threshold value killer is turned on by burst-amplitude 3H 5 Threshold value killer is turned off by burst-amplitude 0H 36H 4:0 37H 1:0 - 2 For test 38H to - - - - 4:0 - 5 CKILL_HYST For test Normally set to 1H - 1H - 3AH 3BH For test For test 3CH 2:0 - 3 3DH 1:0 - 2 For test 3EH 4:0 5 ACC setting 3FH - - - I2BAC_ ACC_SELAMP - Normally set to 0H For test Normally set to 0H For test Normally set to 0H Gain setting at ACC_ON = 2’b1x Setting range: -6 to 32dB - 0H 0H 0H 0H - For test 5 - 1 For test 4 - 1 For test 3:0 I2BSE_BELLF0 4 Bell filter f0 select 8H 7:4 I2BSE_BELLQ 4 Bell filter Q select 8H 3:2 I2BSE_BELLAMP 2 2 - 1 1:0 I2BSE_CLPFSEL 2 43H 5:0 - 6 44H 7:0 - 8 40H 41H 42H Bell filter setting - 2 1:0 - 2 45H For test Normally set to 0H Bell filter amplifier select 0: 1 time For test LPF setting after FM demodulation 1: 2 times For test Normally set to 1H LPF select after FM demodulation For test Normally set to 28H For test For test 3:2 Normally set to 1H Normally set to 40H For test Normally set to 3H For test Normally set to 3H 1H 0H 1H 1H 2H 28H 40H 3H 3H Continued on next page. No.A1957-24/45 LC749870W Continued from preceding page. Sub- Bit- Bit Name 6:4 - 3 3 - 1 2:1 - 2 0 - 1 47H 5:0 - 6 48H 3:0 - 4 49H 6:0 - 7 4AH 6:0 - 7 4BH 5:0 - 6 For test 4CH 5:0 - 6 For test 4DH to - - - - 2 - 1 1 - 1 0 - 1 7:0 I2BSE_UGAIN 8 address Size Function Name For test Functions For test Normally set to 1H For test Normally set to 1H 46H For test Normally set to 3H For test Normally set to 0H For test For test Normally set to 1H For test Normally set to 1H For test Normally set to 40H For test Normally set to 40H For test Normally set to 3H For test Normally set to AH - Initial value 1H 1H 3H 0H 1H 1H 40H 40H 3H AH - 4FH 50H 51H For test Normally set to 1H For test For test Normally set to 0H For test Normally set to 0H Cb/Cr gain control 1H 0H 0H 80H 0 to 3.984375 0=0 52H 7:0 I2BSE_VGAIN 64 = 1 8 SECAM chroma adjustment 53H 7:0 I2BSE_UOFFSET 8 80H 128 = 2 255 = 3.984375 Cb/Cr offset adjustment 80H -128 to 127 0 = -128 54H 7:0 I2BSE_VOFFSET 8 128 = 0 80H 255 = 127 5 - 1 4:3 I2BSE_DEIIR 2 2:0 - 3 For test - - - - 60H 7:0 - 8 For test 61H 7:0 - 8 For test 55H 56H to For test De-emphasis filter setting For test Normally set to 0H De-emphasis filter select For test Normally set to 0H - 0H 0H 0H - 5FH For test Normally set to FH For test Normally set to 64H FH 64H Continued on next page. No.A1957-25/45 LC749870W Continued from preceding page. Subaddress 62H 63H Bit Name 1 For test 6 1 For test 1 For test 4 1 For test 3 1 For test - - 5 - - - 7 1 For test 6 1 For test I2BCV_TVMODE 3 1 TV mode select 2 1 Frequency select 1:0 2 System setting 7:6 65H 68H to 2 For test 3 For test - - 2:0 67H Function Name 7 64H 66H BitSize - - 7:6 2 For test 5 1 For test 1 For test 3:1 3 For test 0 1 For test 4 - - - - - 6AH 7:0 - 8 For test 6BH to - - - - 70H 71H Initial Functions value For test 0H Normally set to 0H For test 1H Normally set to 1H For test 0H Normally set to 0H For test 0H Normally set to 0H For test 0H Normally set to 0H - - For test 0H Normally set to 0H For test 0H Normally set to 0H 0: Auto setting 1: Manual setting with TVMODE[2: 0] 0H 0: 50Hz (625 lines) 0H 0: NTSC 1: 60Hz (525 lines) 1: PAL-M For test Normally set to 0H For test Normally set to 1H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H For test Normally set to 0H - 2: PAL 3: PAL-N 0H 0H 1H 0H 0H 0H 0H 0H - 69H 5:0 I2BSR_GAIN 6 Sub contrast/ 72H 73H 5:0 I2BSR_OFST 6 brightness setting to - - - - 1 - 1 For test 0 I2BSR_SETUP 1 Setup - - - - 0 - 1 For test Normally set to 10H - 10H - Contrast adjustment 20H Brightness adjustment 20H - - 7BH 7CH 7DH to For test Normally set to 0H Setup processing - 0H 1H - 7FH 80H For test For test 81H 0 - 1 82H to - - - Normally set to 1H For test Normally set to 0H - - 1H 0H - 9FH Continued on next page. No.A1957-26/45 LC749870W Continued from preceding page. Subaddress A0H Bit Name 2:0 - BitSize Function Name For test 3 For test A1H 2:0 - 3 Functions Normally set to 0H For test Normally set to 0H Initial value 0H 0H No.A1957-27/45 LC749870W BANK3 (Digital Video Signal Processing Block 3) Register Specification Sub- Bit- Name 2 I2DSH_LPFOFF 1 Sharpness setting 1 - 1 For test 0 I2DSH_ON 1 01H 5:0 I2DSH_ATT 6 02H 2:0 I2DSH_CORR 3 Sharpness coring threshold 0H 03H 3:0 I2DSH_FILTER 4 Sharpness characteristic select 1H 2 - 1 1 - 1 0 - 1 05H 0 - 1 06H 7:0 I2DCB_CONT 8 Contrast/ 07H 7:0 I2DCB_BRIGHT 8 Brightness setting 08H 6:0 I2DHU_HUE 7 HUE setting HUE adjustment 40H 09H 7:0 I2DUV_UGAIN 8 U/V gain Cb gain control B4H 0AH 0BH 7:0 I2DUV_VGAIN 8 setting Cr gain control B4H to - - - - 1:0 - 2 For test 3:1 I2DCT_SMP 3 0 I2DCT_CTIEN 1 7:4 I2DCT_CORR 4 00H 04H Size Function Name Functions Initial Bit address Sharpness LPF ON/OFF setting 0: ON 1: OFF For test Sharpness ON/OFF setting 1: ON Sharpness ATT value setting Sharpness setting Setting range: -47.5 to 12dB For test For test 10H 0H Normally set to 0H For test 1H Normally set to 1H For test 0H 0H Normally set to 0H For test 0H 0H Normally set to 0H 0: OFF value For test 0H Normally set to 0H Contrast adjustment 80H Brightness adjustment 80H - - 0EH 0FH 10H 11H 3:0 I2DCT_GAIN 4 7:4 - 4 12H 5:4 3 13H 14H to I2D65_ AUTOBBACK I2D65_SEPIA 1H Normally set to 1H CTI correction tap coefficient CTI ON/OFF setting CTI setting 0: OFF CTI Coring threshold 0H GAIN=C_GAIN/8 (0 ≤ C_GAIN ≤ 15) For test 1 0H 0H 1: ON CTI gain For test 3:0 For test 6H 0H Normally set to 0H For test 0H Normally set to 0H No signal output mode 2 00: Black background 01: Blue background 10: OFF 1 2 I2D65_601LIM 1 1 I2D65_AVOFF 1 656 conversion setting 0: Normal output 1: Sepia output 0: Signal level 1 to 254 1: Y level 16 to 235, C level 16 to 240 0: 656 with SAV,EAV 1: No SAV, EAV 0 - 1 For test - - - - 1:0 - 2 For test Normally set to 0H - 0H 11: BL 0H 0H 1H 0H - 1FH 20H For test For test 21H 1:0 - 2 Normally set to 0H For test Normally set to 0H 0H 0H No.A1957-28/45 LC749870W Function Descriptions 1. CPU I/F The LC749870W registers are controlled by I2C. 1) I2C The LC749870W supports high-speed mode slave operation (400 kHz) and the slave address is as follows. bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] (MSB) 1 bit[0] (LSB) 0 0 0 1 0 I2CSEL R/W *Note: The bit 1 is decided according to the I2CSEL pin condition. bit 0 R/W: 0 = write, 1 = read ■Write Mode • Auto address increment. • As shown below, after the start condition, the settings must be made in the following order: slave address (W), ACK waiting, write start sub address, ACK waiting, write data. The stop condition must be set last. Data can be transmitted continuously from the write start sub address using the auto address increment function. [ST] [Slave Address(W)] [A] [Sub address] [A] [Data] [A] [Data] • • • [SP] ■Read Mode • Auto address increment. • The read start sub address must be assigned in write mode. • As shown below, after the start condition, first set the slave address (W), ACK waiting and read start sub address. Next, set the start condition again or set the start condition after setting the stop condition. Next set the slave address (R) and ACK waiting in read mode. The data for each sub address is output continuously from the read start sub address data using the auto address increment function. After receiving the data for each sub address, return the ACK. Finally, set the stop condition. [ST] [Slave Address (W)] [A] [Sub address] [ST] [Slave Address(R)] [A] [Data] [A] [Data] [A] [Data] • • • [SP] or [ST] [Slave Address (W)] [A] [Sub address] [SP] [ST] [Slave Address(R)] [A] [Data] [A] [Data] [A] [Data] • • • [SP] [ST]: Start condition [SP]: Stop condition [A]: ACK [A]: ACK waiting [Data]: Data transmission [Data]: Data reception No.A1957-29/45 LC749870W 2) BANK Each register is allocated to the BANK depending on its function (Refer to Table 1). After the BANK is specified, the register can be controlled. The BANK is specified by setting the BANK code to sub address FFH. Note that the register cannot be transmitted or received if codes other than the BANK codes in Table1 are specified. Table 1 Allocation of BANK BANK BANK Code 0 01H Controlled Function AFE + ADC Digital video signal processing block 1 1 02H (Data interpolator, APC, AGC, digital clamp, sync separator, timing generator, video system detection, S/N detection, non-standard signal detection, No-signal detection) 2 04H 3 08H Digital video signal processing block 2 (Y/C separator, color demodulator, clock rate converter) Digital video signal processing block 3 (Sharpness, contrast/brightness, CTI, HUE, UV gain) • Auto address increment. [ST] [Slave address (W)] [A] [FFH] [A] [BANK Code] [SP] [ST]: Start condition [SP]: Stop condition [A]: ACK [Data]: Data transmission No.A1957-30/45 LC749870W 2. AFE and ADC This IC (LC749870W) incorporates 1-channel of video AFE and 10-bit 30MHz ADC. • Analog clamp (Self-clamp circuit) The self clamp circuit clamps the sync-tip without supplying clamp pulses to AFE module. When the self-clamp function is not used, it can be placed in power down mode using I2C_SELFCLPPWDB. • Sync-tip clamp specifications Digital output Analog input ADC output code 1023 878 1.55V 1.35V 1.0Vp 0.85V 512 (ADC-input reference) 0.65V 356 0.35V 147 1 0.15V 1.4Vp-p range * The figures represent the values under ideal conditions. Clamp Setting Self Clamp Setting SELFCLPPWDB 1: Self Clamp enable Main Clamp Level Setting MAINCLPLVCNT [1:0] 00: Main Clamp Level 0.35V • Low pass filter before self-clamp A primary LPF with a 1MHz cutoff frequency has been inserted in the stage before the self-clamp circuit as a measure to deal with the high-frequency noise that is present in weak electric fields. The LPF function is for minimizing shifts in the clamp levels of the self-clamp when high-frequency noise components are present in the video signals. The LPF can be set to ON or OFF using I2C_CLPLPFON. Sync tip clamp when LPF is OFF Input video signal (SD) Sync tip clamp when LPF is ON High frequency noise of 1MHz or more 0.35V 0V Clamping is performed at the lower limit level of the noise components. Due to the effect of the noise, the clamp level shifts. Clamping is performed at the level at which the noise components are removed. It is clamped at its original position. Fig.1 Self Clamp in Weak Electric Fields No.A1957-31/45 LC749870W • AGC Mode and Non-AGC Mode Switch between non-AGC mode and AGC mode using I2C_SCARTON. Non-AGC mode is used when the amplitude of the video signal is steady in the environment of a strong electric field. The maximum of the sync tip clamped analog video input amplitude assumes 1.0Vp-p in non-AGC mode. The ADC full-scale input range is fixed at 1.4Vp-p. AGC mode is used when the amplitude of the video signal is unsteady in the environment of a weak electric field. The maximum of the sync tip clamped analog video input amplitude assumes a value no greater than from 0.7Vp-p (-3dB) to 1.4Vp-p (+3dB) in AGC mode. Because the AFEVRTC is controlled according to the amplitude of SYNC detected by the decoder, AGC mode is enabled by varying the ADC full-scale input range. 3. Data Interpolator Data interpolator converts the input video signal sampled at 27MHz into 4fsc data. Supported video systems are shown in the following table. Table 2: Supported Video System Video System NTSC Input Output Sampling clock Data transfer rate Clock lock method 27MHz 14.318180MHz Burst Lock PAL-B, G, D, K, I 27MHz 17.734476MHz Burst Lock PAL-M 27MHz 14.302444MHz Burst Lock PAL-N 27MHz 14.328224MHz Burst Lock NTSC4.43 27MHz 17.734476MHz Burst Lock PAL-60 27MHz 17.734476MHz Burst Lock SECAM 27MHz 13.5MHz H Lock 4. APC (Auto Phase Control) In order to burst lock input video signals, the APC circuit detects the color burst phase error. The data interpolation coefficient is calculated using the detected phase error, and is then output to the data interpolator circuit. It is equipped with a function to turn on the color killer when not burst-locked, and also has an ACC circuit to maintain the amplitude of the carrier chrominance signal at a constant level. 5. AGC (Auto Gain Control) The AGC keeps the sync level constant by automatically calculating an appropriate gain value from the input video signal sync level and amplifying the input video signal. Because the AGC circuit includes a time constant circuit, following rapid changes in the input video signal can be suppressed. Pedestal Level Sync Level Before AGC After AGC Sync tip Level Fig.2 Waveform Change Before and After AGC No.A1957-32/45 LC749870W 6. Digital Clamp The digital clamp circuit detects the pedestal level of the input video signal, and keeps the level constant. Because the digital clamp includes a time constant circuit, following rapid changes in the input video signal can be suppressed. Input signal Target pedestal level 0LSB Before clamp After clamp Fig.3 Waveform Change Before and After Digital Clamp 7. Sync Separator The sync separator circuit separates horizontal and vertical sync signals out of the input video signals. Because an LPF is built in, the sync signal can be separated even in a weak electric field. The weak electric field is detected using the S/N detection result. Moreover, the stability of the sync signal in the weak electric field is improved by the internal AFC circuit. Fig. 4 shows the LPF characteristics for the sync separator. “FILSEL = 1’b0” is the characteristic of an LPF for a weak electric field, and “FILSEL = 1’b1” is the characteristic of an LPF for a strong electric field. Fig.4 LPF Characteristic for Sync Separator 8. Timing Generator Using the sync signal separated by the sync separator circuit, the timing generator generates various timing signals to be used for each module as well as for horizontal and vertical blanking signals. The adjustments of timing signals are possible by setting the corresponding register (s) as follows: Positioning of horizontal sync signal: I2A_HSPAD Positioning of vertical sync signal: I2A_VSTART Positioning of horizontal blanking signal: I2A_HBSTART, I2A_HBEND Positioning and width adjustment of vertical blanking signal: I2A_VBSTART, I2A_VBWIDTH No.A1957-33/45 LC749870W 9. Two-dimensional Y/C Separation The Y/C separator switches adaptive two-dimensional Y/C separation and one-dimensional Y/C separation according to the input video system. The table below shows the relationship between input video system and Y/C separation method. Table 3 Relationship Between Input Video System and Y/C Separation Method Video System Y/C Separation Filter NTSC Adaptive two-dimensional Y/C separation NTSC-4.43 One-dimensional Y/C separation PAL-B, G, D, K, I, M, N Adaptive two-dimensional Y/C separation PAL-60 One-dimensional Y/C separation SECAM One-dimensional Y/C separation 1) Adaptive Two-dimensional Y/C Separation The correlation between lines is detected in the vertical LPF and BPF, and the system switches between upper two line processing and lower two or three line processing, based on the results. The adaptive two-dimensional Y/C separation and two-dimensional Y/C separation can be switched using I2BYC_2DCOMB8 [7]. Note that the Y/C separation filter is switched to one-dimensional Y/C separation when I2BYC_1DFIL [0] is set to 1’b1 ( I2BYC_1DFIL [0] = 1’b1). • Y signal = (Vertical low frequency component) + (Horizontal low frequency component of vertical high frequency component) • C signal = Horizontal high frequency component of vertical high frequency component Vertical frequency Vertical frequency 525/4cph 525/4cph Composite signal Input Pass range 3.58MHz horizontal frequency Pass range horizontal 3.58MHz frequency Vertical LPF Separation Y Output horizontalLPF horizontalBPF Vertical BPF Vertical frequency 525/4cph Pass range Vertical frequency 525/4cph Separation C Output Vertical frequency Pass range 525/4cph Pass range horizontal 3.58MHz frequency horizontal 3.58MHz frequency 3.58MHz horizontal frequency Fig.5 Basic Block Diagram of Two-dimensional Y/C Separation (Line Comb Filter) • 1 Line Chroma Detector When 1 line chroma is separated with the two-dimensional Y/C separation, the dot interference is generated because there is no correlation between lines. Therefore, 1 line chroma is detected and dot interference reduction is attempted by subtracting chroma components. When the following conditions exist, it is judged to be 1 line chroma. (1) No chroma changes in the line (horizontal direction). (2) Chroma changes between lines (vertical direction). (3) Luminance changes between lines (vertical direction). No.A1957-34/45 LC749870W • 3 Line Median Processing When the vertical color in the DVD color bar changes and blurs, dot interference may be generated. Dot interference reduction is attempted by detecting this location and removing the chroma components. W Y Cy Gr Ma R B DVD SG Fig.6 Dot interference When the following conditions exist as a result of comparing the BPF values for each line, the chroma components must be removed. (1) When there is a match between the median value of each line and the pixel of the line at the center. (2) When there is a change between lines. • Y Signal Bypass Processing If the chroma band component of the separated Y signal is compared with the chroma band component of the signal before separation, and if the chroma band of the signal before separation is smaller, the signal is output as a Y signal. • C Signal Bypass Processing If a C signal processed by the comb filter is compared with the result processed by the BPF, and if the result of the BPF is smaller, the BPF processing result is output as a C signal. • Dot Interference Reduction The line comb filter need not add HLVH*1 to the Y signal if there is a complete line correlation, such as with the Color Bar. Such an addition will only increase the dot interference shown in Fig. 6 above. Therefore, when a location with strong line correlation is detected, the horizontal BSF pass band of HLVH to be added to the Y signal is narrowed, and the dot interference is reduced. The dot interference reduction BSF can be set to ON or OFF using I2BYC_2DCOMB2[3]. *1: Horizontal low frequency component of vertical high frequency component • Cross Color Reduction When a location with weak line correlation is detected, the BPF pass band in the subsequent stage of the C signal is narrowed, and the cross color is reduced. cross color reduction can be set to ON or OFF using I2BYC_2DCOMB4 [4]. No.A1957-35/45 LC749870W 2) One-dimensional Y/C separation (BPF) Y/C separation is performed by using BPF. The BPF characteristics for NTSC/PAL and for SECAM are selected by I2BYC_1DFIL [7:1]. It is forced to one-dimensional Y/C separation when I2BYC_1DFIL [0] is set to 1’b1 (I2BYC_1DFIL [0] = 1’b1). When performing adaptive two-dimensional Y/C separation, I2BYC_1DFIL [0] must be set to 1’b0 (I2BYC_1DFIL [0] = 1’b0) . Fig.7 and 8 show the characteristics of BPF. 10 0 BPF0 BPF1 BPF2 BPF3 BPF4 BPF5 BPF6 BPF7 BPF8 BPF9 BPF10 BPF11 -10 [dB] -20 -30 -40 -50 -60 0 1 2 3 4 Frequency[MHz] 5 6 7 Fig.7 BPF Characteristic for NTSC/PAL 10 0 BPF0 BPF1 BPF2 BPF3 BPF4 BPF5 BPF6 BPF7 -10 [dB] -20 -30 -40 -50 -60 0 1 2 3 Frequency[MHz] 4 5 6 Fig.8 BPF characteristic for SECAM No.A1957-36/45 LC749870W 10. Chrominance Signal Processing In chrominance signal processing, U/V axial demodulation is performed on the carrier chrominance signal after Y/C separation, and the UV signal is output. 1) ACC (Auto Color Control) ACC maintains a constant carrier chrominance signal amplitude for NTSC and PAL. The amplitude is kept constant by observing the color burst amplitude of the input carrier chrominance signal, and controlling the amplifier according to the amplitude level. It can also turn on the color killer when the color burst amplitude is small. I2BAC_ACC_ON switches between ACC ON and OFF. 2) Color Killer The color killer masks the carrier chrominance signal so that a monochrome image is output. When entering the detection results from APC or ACC circuits or an incompatible signal, the color killer is turned on and off. The color killer can be set using I2BAC_CKILL_ON. 3) NTSC/PAL Color Decoder The NTSC/PAL color decoder demodulates the carrier chrominance signal into color component signals (U/V). • Color Demodulator and Low Pass Filter The Cb/Cr signal is demodulated by multiplying the chrominance signal and phase-controlled color sub-carrier (4Fsc). Fig. 9 shows the block diagram. Chrominance signal × LPF 10 Cb/Cr signal 10 Color sub-carrier Fig.9 Color Demodulator The LPF characteristic after demodulation is shown in Fig.10. 10 0 0 1 2 3 4 5 6 7 Magnitude[dB] -10 -20 -30 -40 -50 -60 Frequency[MHz] Fig.10 LPF Characteristic after Demodulation No.A1957-37/45 LC749870W • UVGAIN (Cb/Cr Gain Control) The UVGAIN adjustment changes the Cb/Cr signal gain based on a center value. Fig.11 shows the block diagram. The gain can be controlled using I2BCD_UGAIN and I2BCD_VGAIN. U(V)GAIN 8bits CBIN (CRIN) 10 − × CBOUT (CROUT) + /128 center(512LSB) Fig.11 UVGAIN Block Diagram 4) SECAM Color Decoder The SECAM color decoder demodulates the carrier chrominance signal into color difference signals (U/V). • Bell Filter The bell filter is used to maintain the color sub-carrier amplitude of the Y/C-separated chrominance signal constant. The f0 parameter can be selected using I2BSE_BELLF0, and the Q parameter using I2BSE_BELLQ. bell filter characteristic 0 I2_BELLQ=0 standard condition I2_BELLQ=15 -2 Gain[dB] -4 -6 -8 -10 -12 -14 3.75 3.95 4.15 4.35 frequency[MHz] 4.55 4.75 Fig.12 Bell Filter characteristics No.A1957-38/45 LC749870W • Low Pass Filter The LPF is used to reduce noise in FM demodulated DB/DR signals. The characteristics of the LPF can be selected using I2BSE_CLPFSEL. LPF characteristic 10 0 Gain[dB] -10 LPF0 LPF1 LPF2 LPF3 -20 -30 -40 -50 -60 0 1 2 3 4 Frequency[MHz] 5 6 Fig.13 LPF Characteristics • UV Gain and Offset Adjustment The UV gain adjustment is performed to convert DB/DR to CB/CR, and the UV offset fine adjustment is also performed. The UV gain can be adjusted by changing I2BSE_UGAIN and I2BSE_VGAIN, and the UV offset can be adjusted by I2BSE_UOFFSET and I2BSE_VOFFSET. DB CB Gain Offset DR CR Fig.14 UV Gain and Offset Adjustment No.A1957-39/45 LC749870W • De-emphasis Filter The de-emphasis filter characteristics can be selected using I2BSE_DEIIR. de-emphasis filter characteristic 0 -5 def0 def1 def2 def3 Gain[dB] -10 -15 -20 -25 0.01 0.1 1 10 Frequency[MHz] Fig.15 De-emphasis Filter Characteristics 11. Automatic Video Standard Recognition The video input standard is recognized automatically. Automatic video standard recognition can be set to ON or OFF using I2A_AUTODET. 12. S/N Detection S/N detection determines the video input noise level. During a vertical blanking period, the detection of noise is processed while the detection enable signal is high. The level of S/N detection can be controlled using I2A_NLTH. ODD line EVEN line Detection enable Signal 128CLK Fig.16 S/N Detection 13. Non-standard Detectionn This function determines whether the video input is non-standard. The video input is judged standard/non-standard by observing any variation from the standard VSYNC cycle. No.A1957-40/45 LC749870W 14. No Signal Detection This function detects no signal state. The result of no signal detection is output to the INTREQ pin. No signal detection function can be turned ON or OFF using I2A_NSDON [1]. Note that I2A_NSDON [0] is available when no signal detection is OFF. 15. Clock Rate Conversion The sampling rate converter converts an input video signal sampled at 4fsc into 13.5MHz, and outputs synchronized signals with video data. 16. Sharpness Sharpness of the image can be adjusted by detecting and forcibly correcting the edge of the luminance signal when the image is scanned horizontally. Adjustments to the enhancing frequency range and level of enhancement are possible. Sharpness can be turned ON or OFF using I2DSH_ON.The enhancing frequency range can be selected using I2DSH_FILTER, and the level of enhancement can be adjusted using I2DSH_ATT. 17. Contrast/Brightness Brightness adjusts the brightness of the entire screen and Contrast adjusts the brightness gain. 1) Contrast Contrast can be controlled using I2DCB_CONT. 00H: × 0 to 80H: × 1 to FFH: × 2 2) Brightness Brightness can be controlled using I2DCB_BRIGHT. 00H: -128 to 80H: ±0 to FFH: +127 18. CTI (Color Transient Improvement) The color transient can be improved by steepening the slope of the input signal. Processed video without overshoot or undershoot can provide more natural video images. The CTI can be switched between ON and OFF using I2DCT_CTIEN. The gain can be controlled using I2DCT_GAIN. The higher the I2DCT_GAIN is set, the more effective the CTI will be. CTI coring can be controlled using I2DCT_CORR. The higher the I2DCT_CORR is set, the less effective coring will be for extremely small amounts of noise. The CTI’s tap parameter can be selected using I2DCT_SMP. The higher the I2DCT_SMP is set, the more the CTI characteristics shift toward lower frequencies. 19. HUE The hue of the screen as a whole can be adjusted. (Refer to Fig.17.) The phase angle can be selected using I2DHU_HUE. 0H: -45° to 80H: 0° to FFH: 44° (with approx. 0.7° increments) plus Standard R minus minus B Standard plus Fig.17 HUE No.A1957-41/45 LC749870W 20. U/ V Gain The saturation (color density) is adjusted by varying the Cb and Cr gain. The Cb gain can be adjusted using I2DUV_UGAIN, and the Cr gain using I2DUV_VGAIN. 21. 8-bit output format conversion The 8-bit output format is converted to a format that is compatible with the ITU-R BT.656 format output. Blue back color can be output in non-signal mode using I2D65_AUTOBBACK. Sepia color can be output using I2D65_SEPIA. Clock 27MHz ♦Input Data Enable Y Y718 Y719 … Y0 Y1 Y2 Y3 Cr Cr359 … Cr0 Cr1 Cb Cb359 … Cb0 Cb1 ♦Output Data Enable ITU-R BT.656 Y715 Cb358 Y716 Cr358 Y717 Cb359 Y718 Cr359 Y719 EAV … SAV Cb0 Y0 Cr0 Y1 Fig.18 Timing Chart (ITU-R BT.656) * The processing is being performed by a 27MHz free-run clock, and so the number of pixels in one line cannot be guaranteed. The data in the period from SAV to EAV can be guaranteed, so read the data using the SAV standard. (Data cannot be read using the EAV standard.) * If equipment without an ITU-R BT.656 interface is connected, connect the HS and VS, or DE and read the data. Clock 27MHz ♦Input Data Enable Y Y718 Y719 … Y0 Y1 Y2 Y3 Cr Cr359 … Cr0 Cr1 Cb Cb359 … Cb0 Cb1 ♦Output Data Enable YCbCr 4:2:2 Y715 Cb358 Y716 Cr358 Y717 Cb359 Y718 Cr359 Y719 … Cb0 Y0 Cr0 Y1 HS tHWBP Figure 19 Timing Chart (YCbCr 4:2:2) * tHWBP shown in Figure 19 has the same value for each format. It can be adjusted by registers. No.A1957-42/45 LC749870W Application Example Digital 3.3V or1.8V 10kΩ 10kΩ 2 I C Controller SDA SCL RESET PDWN Video IN DATA[7:0] AIN0 0.1μF 75Ω AIN1 CK0 AIN2 AIN3 CK13 HS 10μF REFPKV VS VRT DE VRB FIELD 0.1μF LC749870W REFNKV INTREQ 10μF MD0 AFEVRTC MD1 0.1μF MD2 TEST XIN 12pF 27MHz DVSS 1MΩ 0.1μF DVDD11 XOUT 12pF 0Ω AVDD33 AVSS33 DVDD33 Digital 1.1V (Digital core) Digital 3.3 or1.8V (IO) Analog 3.3V (Analog core) DVSS 0.1μF 0.1μF 10μF Analog GND Digital GND No.A1957-43/45 LC749870W Other (usage precautions) 1. Precaution when turning-on the power As shown in the figure below, start transfer of the I2C bus command after factoring in the power-on time (A), RST operation time (B) and command transfer start time (C). DVDD33 XVDD33 AVDD33 3.0V DVDD11 XVDD11 1.0V 2V RESET 0.2VDD 0.75VDD Command A B C A: Power-on time This is the time taken from power-on to when the *VDD11 operating voltage has reached the lowest level (0.99V) and operation has stabilized. The power-on-time depends on the characteristics of the power ICs and other components, so it must be checked separately. With regard to *VDD33 and *VDD11, *VDD11 must be turned on after *VDD33 has turned on. B: RESET operation time This is the time during which the “L”level must be applied continuously for a period of 10ms or more to the RESET pin after the PDWN is released (“H” level). C: Command transfer start time At least an interval of 10ms is required from the time RESET pin is released (“H” level) to the start of command transfer. No.A1957-44/45 LC749870W 2. Precaution when turning-off the power DVDD33 XVDD33 AVDD33 DVDD11 XVDD11 3.0V 0.99V A As a basic rule, power-off must be performed in the reverse sequence of power-on. However, no problems are posed if there is no wait time. A: Power-off time This is the time it takes to reach the IO supply voltage and for operation to stabilize from the lowest level (0.99V) of the *VDD11 operating supply voltage. With regard to *VDD33 and *VDD11, *VDD33 must be turned off after *VDD11 has been turned off or they must be turned off at the same time. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2011. Specifications and information herein are subject to change without notice. PS No.A1957-45/45