Ordering number : ENA0167B Bi-CMOS IC LV8054LP For Digital Cameras Single-chip motor Driver IC Overview LV8054LP is single-chip motor driver IC for digital cameras. Functions • Integrates the digital camera actuator drivers on a single chip • Four constant voltage output channels, two constant current output channels • All actuators can be driven at the same time • The AF and zoom stepping motors are driven by the clock signal • Supports PWM control of a DC zoom motor. • Can switch between an external input or an internal reference for the constant voltage output setting reference voltage • The constant voltage output multiplier can be set to one of 16 levels • The constant current output reference voltage can be set to one of 16 internal reference voltage levels • Built-in photosensor drive transistor • Three built-in Schmitt buffer circuits (the presence or absence of hysteresis can be set individually) Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage 1 VB max 6.0 V Supply voltage 2 VCC max 6.0 V Peak output current IO peak OUT1 to 12 (t≤10mS, ON-duty≤20%) 600 mA Continuous output current IO max1 OUT1 to 12 400 mA IO max2 PI Pd max Mounted on a circuit board* Allowable power dissipation 85 mA 1100 mW Operating temperature Topr -20 to +85 °C Storage temperature Tstg -55 to +150 °C * Standard circuit board: 40×50× 0.8 mm3 glass epoxy four-layer board Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 71807 MS / 20807 MS PC / 10606 MS OT 20051227-S00014 No.A0167-1/23 LV8054LP Recommended Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage range 1 VB 2.7 to 5.5 V Supply voltage range 2 VCC 2.7 to 5.5 V Logic level input voltage VIN 0 to VCC+0.3 V Constant voltage setting VC 0.1 to VCC V input range Clock frequency FCLK CLK1, CLK2/PWM PWM frequency FPWM CLK2/PWM -64 KHz -100 KHz Electrical Characteristics at Ta = 25°C, VB = 5V, VCC = 3.3V Ratings Parameter Symbol Conditions Unit min Quiescent current Current drain 1 ICCO IB typ max 1 µA 500 950 µA 1.5 2.0 mA 2.1 2.35 2.6 V ST = low, BI1/2/3 = low ST = high, IN51/52/61/62 = low, BI1/2/3 = low, With no output load Current drain 2 ICC ST = high, IN51/52/61/62 = low, BI1/2/3 = low, With no output load VCC low-voltage cutoff voltage VthVCC Low-voltage hysteresis VthHYS Thermal shutdown temperature Thermal shutdown hysteresis 100 150 200 mV TSD Design target value 160 180 200 °C ∆TSD Design target value 20 40 60 °C AF/Zoom Motor Drivers (OUT1/2, OUT3/4, OUT5/6, OUT7/8) Output on-resistance 1 Output leakage current 1 Diode forward voltage 1 Internal reference voltage Constant voltage output VC voltage divider voltage ratio Ronu1 Ta = 25°C, IO = 200mA, High side on-resistance 0.7 0.85 Ω Rond1 Ta = 25°C, IO = 200mA, Low side on-resistance 0.5 0.65 Ω 1 µA IOleak1 VD1 ID = -400mA VREF 0.7 0.9 1.2 V 0.84 0.88 0.92 V 4.4 4.6 V VOUT1 VC = 0.88V 4.2 VOUT2 VC = 0.88V (internal reference) 4.2 4.4 4.6 V VCR1 (D3, D4, D5, D6) = (0, 0, 0, 0) 95 100 105 % VCR2 (D3, D4, D5, D6) = (1, 0, 0, 0) 92.8 97.7 102.6 % VCR3 (D3, D4, D5, D6) = (0, 1, 0, 0) 90.7 95.5 100.2 % VCR4 (D3, D4, D5, D6) = (1, 1, 0, 0) 88.5 93.2 97.8 % VCR5 (D3, D4, D5, D6) = (0, 0, 1, 0) 86.4 90.9 95.5 % VCR6 (D3, D4, D5, D6) = (1, 0, 1, 0) 84.2 88.6 93.1 % VCR7 (D3, D4, D5, D6) = (0, 1, 1, 0) 82.0 86.4 90.7 % VCR8 (D3, D4, D5, D6) = (1, 1, 1, 0) 79.9 84.1 88.3 % VCR9 (D3, D4, D5, D6) = (0, 0, 0, 1) 77.7 81.8 85.9 % VCR10 (D3, D4, D5, D6) = (1, 0, 0, 1) 75.6 79.5 83.5 % VCR11 (D3, D4, D5, D6) = (0, 1, 0, 1) 73.4 77.3 81.1 % VCR12 (D3, D4, D5, D6) = (1, 1, 0, 1) 71.2 75.0 78.7 % VCR13 (D3, D4, D5, D6) = (0, 0, 1, 1) 69.1 72.7 76.4 % VCR14 (D3, D4, D5, D6) = (1, 0, 1, 1) 66.9 70.5 74.0 % VCR15 (D3, D4, D5, D6) = (0, 1, 1, 1) 64.8 68.2 71.6 % VCR16 (D3, D4, D5, D6) = (1, 1, 1, 1) 62.6 65.9 69.2 % Continued on next page. No. A0167-2/23 LV8054LP Continued from preceding page. Ratings Parameter Symbol Conditions Unit min Logic pin input current IINL VIN = 0V (ST, CLK1, CLK2/PWM) IINH VIN = 3.3V (ST, CLK1, CLK2/PWM) High-level input voltage VINH ST, CLK1, CLK2/PWM Low-level input voltage VINL ST, CLK1, CLK2/PWM typ max 33 1.0 µA 50 µA 2.5 V 1.0 V Shutter/AE Motor Drivers (OUT9-10, OUT11-12) Output on-resistance 2 Ronu2 Ta = 25°C, IO = 200mA, High side on-resistance 0.7 0.85 Ω Rond2 Ta = 25°C, IO = 200mA, Low side on-resistance 0.5 0.65 Ω 1 µA Output leakage current 2 IOleak2 Diode forward voltage 2 VD2 Constant current output ID = -400mA 0.7 0.9 1.2 V IO Rf = 1Ω, (D3, D4, D5, D6) = (0, 0, 0, 0) 190 200 210 mA Internal current setting VREF1 (D3, D4, D5, D6) = (0, 0, 0, 0) 0.190 0.200 0.210 V reference voltages VREF2 (D3, D4, D5, D6) = (1, 0, 0, 0) 0.162 0.170 0.179 V VREF3 (D3, D4, D5, D6) = (0, 1, 0, 0) 0.157 0.165 0.173 V VREF4 (D3, D4, D5, D6) = (1, 1, 0, 0) 0.152 0.160 0.168 V VREF5 (D3, D4, D5, D6) = (0, 0, 1, 0) 0.147 0.155 0.163 V VREF6 (D3, D4, D5, D6) = (1, 0, 1, 0) 0.143 0.150 0.158 V VREF7 (D3, D4, D5, D6) = (0, 1, 1, 0) 0.138 0.145 0.152 V VREF8 (D3, D4, D5, D6) = (1, 1, 1, 0) 0.133 0.140 0.147 V VREF9 (D3, D4, D5, D6) = (0, 0, 0, 1) 0.128 0.135 0.142 V VREF10 (D3, D4, D5, D6) = (0, 0, 0, 1) 0.124 0.130 0.137 V VREF11 (D3, D4, D5, D6) = (0, 1, 0, 1) 0.119 0.125 0.131 V VREF12 (D3, D4, D5, D6) = (1, 1, 0, 1) 0.114 0.120 0.126 V VREF13 (D3, D4, D5, D6) = (0, 0, 1, 1) 0.109 0.115 0.121 V VREF14 (D3, D4, D5, D6) = (1, 0, 1, 1) 0.105 0.110 0.116 V VREF15 (D3, D4, D5, D6) = (0, 1, 1, 1) 0.100 0.105 0.110 V (D3, D4, D5, D6) = (1, 1, 1, 1) 0.095 0.100 0.105 V 1.0 µA 50 µA VREF16 Logic pin input current IINL VIN = 0V (IN51, IN52, IN61, IN62) IINH VIN = 3.3V (IN51, IN52, IN61, IN62) High-level input voltage VINH IN51, IN52, IN61, IN62 Low-level input voltage VINL IN51, IN52, IN61, IN62 33 2.5 V 1.0 V Photosensor peripheral circuits (PI, BI1, BO1, BI2, BO2, BI3, BO3) Output on-resistance 3 Output leakage current 3 Schmitt buffer threshold level (hysteresis) Schmitt buffer hysteresis Schmitt buffer threshold level Ron3 Ta=25°C, IO= 60mA 2 IOleak3 2.5 Ω 1 µA VthH 1.50 1.70 1.90 V V VthL 0.85 1.05 1.25 Vthhys 0.5 0.7 0.9 V Vth 1.4 1.6 1.8 V (no hysteresis) Continued on next page. No. A0167-3/23 LV8054LP Continued from preceding page. Ratings Parameter Symbol Conditions Unit min typ max Serial Data Transfer Pins Logic pin input current IINL VIN = 0V (SCLK, DATA, STB) IINH VIN = 3.3V (SCLK, DATA, STB) 33 1.0 µA 50 µA High-level input voltage VINH SCLK, DATA, STB Low-level input voltage VINL SCLK, DATA, STB 2.5 V Minimum SCLK high-level pulse Tsch 0.125 µS Tscl 0.125 µS Tlat 0.125 µS 1.0 V width Minimum SCLK low-level pulse width Stipulated STB time Tlatw 0.125 µS Data setup time Tds 0.125 µS Data hold time Tdh 0.125 µS Maximum CLK frequency Fclk Minimum STB pulse width 4 MHz Package Dimensions unit : mm (typ) 3302A Top View Bottom View 0.35 5.0 40 (0.7) 0.4 5.0 31 0.35 30 21 20 11 0.05 0 NOM 0.85MAX 10 1 0.2 (0.7) SANYO : VQLP40(5.0X5.0) No. A0167-4/23 LV8054LP Block Diagram No. A0167-5/23 LV8054LP Pin Functions Pin No. Symbol 26 VB1 5 Pin No. Symbol Power supply for OUT1-4 4 OUT11 Motor driver output VB2 Power supply for OUT5-8 2 OUT12 Motor driver output 33 VB3 Power supply for OUT9-10 30 VC External reference voltage input for the OUT1-8 constant current output 37 VB4 Power supply for OUT11-12 11 ST Chip enable 34 VCC Control system power supply 12 CLK1 Stepping motor clock for OUT1-4 23 PGND1 Power system ground for OUT1-4 18 SCLK Serial data transfer clock 8 PGND2 Power system ground for OUT5-8 20 DATA Serial data 28 RF1 Current detection connection for OUT9-10 19 STB 3 RF2 36 Description Description Serial data latch pulse input Stepping motor clock/PWM signal input for OUT5-8 Current detection connection for OUT11-12 13 CLK2/PWM SGND Control system ground 14 IN51 Control input for OUT9-10 21 OUT1 Motor driver output 15 IN52 Control input for OUT9-10 22 OUT2 Motor driver output 16 IN61 Control input for OUT11-12 24 OUT3 Motor driver output 17 IN62 Control input for OUT11-12 25 OUT4 Motor driver output 35 PI Photosensor drive output 10 OUT5 Motor driver output 1 BI1 Schmitt buffer input 1 9 OUT6 Motor driver output 40 BO1 Schmitt buffer output 1 7 OUT7 Motor driver output 39 BI2 Schmitt buffer input 2 6 OUT8 Motor driver output 38 BO2 Schmitt buffer output 2 27 OUT9 Motor driver output 32 BI3 Schmitt buffer input 3 29 OUT10 Motor driver output 31 BO3 Schmitt buffer output 3 Pin Assignment No. A0167-6/23 LV8054LP Serial Data Input Overview Serial Data Input Timing Chart Data is input in order from D0 to D7. Data is transferred on the SCLK rising edge and, after all data has been transferred, the data is latched by the rising edge of the STB signal. Note that the IC internal circuits will not accept the SCLK signal while the STB signal is high. Timing with which the Serial Data is Reflected in the Outputs Basically, the new values are reflected in the output at the point the data is latched with the STB signal. → Pattern 1 However, the "Excitation direction" and "Excitation mode" settings used in stepping motor clock drive mode for channels 1 through 4 are an exception. In this case only, after the data is latched with the STB signal, the new values are reflected on the next rising edge of the CLK signal. → Pattern 2 No. A0167-7/23 LV8054LP Detailed Description of Serial Data Input Note: This IC's channels are assigned as follows. OUT1/OUT2 → Channel 1 OUT3/OUT4 → Channel 2 OUT5/OUT6 → Channel 3 OUT7/OUT8 → Channel 4 OUT9/OUT10 → Channel 5 OUT11/OUT12 → Channel 6 Stepping motor excitation type for channels 1 through 4 This IC supports connecting stepping motors to channels 1 and 2 and to channels 3 and 4. Either of these stepping motors can be controlled by a single clock signal. When this capability is used, the clock signal input pins and the channels as associated as shown below. CLK1: CLK2/PWM: Controls channel 1 and 2 drive. Controls channel 3 and 4 drive The following state settings related to control of these stepping motors are set using the serial data. (See subsection, Serial Logic Table 1, in section ,Truth Tables, for a detailed description of this data.) • Excitation mode: • Excitation direction: • Step/Hold: • Counter reset: • Output enable: • VC voltage divisor: • VC voltage selection: 2-phase excitation or 1-2 phase excitation CW (clockwise) or CCW (counterclockwise) Clear or Hold Normal Operation or Reset Output Off or Output On Selects one of 16 values Internal or External No. A0167-8/23 LV8054LP Excitation Mode Setting This section presents the timing charts for each excitation mode. Two-Phase Excitation Timing Chart No. A0167-9/23 LV8054LP 1-2 Phase Excitation Timing Chart No. A0167-10/23 LV8054LP Sample Timing Chart for the Excitation Direction Setting The excitation direction setting sets the excitation (rotation) direction of the stepping motor. With the CW (clockwise) setting, the phase of the channel 2 current is delayed from that of the channel 1 current by 90°. With the CCW (counterclockwise) setting, the phase of the channel 2 current leads that of the channel 1 current by 90°. No. A0167-11/23 LV8054LP Step/Hold Operation Overview Sample Timing Chart for the Step/Hold Setting When the Step/Hold data is set to the Hold state, the state of the external clock signal (CLK) at that time is latched and held as the internal clock signal. At the timing with which Step/Hold is set to the Hold state for the first time in the figure below, the internal clock signal will be held at the low level because the external clock (CLK) was at the low level. In contrast, at the timing with which Step/Hold is set to the Hold state for the second time, the internal clock signal will be held at the high level because the external clock (CLK) was at the high level. When Step/Hold is set to the Clear state, the internal clock is synchronized with the external clock (CLK). The output holds the state it was in at the point Step/Hold is set to the Hold state, and advances on the next clock signal rising edge after Step/Hold is set to the Clear state. As long as Step/Hold is in the Hold state, the position number does not advance even if an external clock (CLK) signal is applied. No. A0167-12/23 LV8054LP Sample Timing Chart for the Counter Reset Setting When the Counter Reset setting is set to the Reset state, the output goes to the initial state on the rising edge of the STB signal. Then, when the Counter Reset setting is set to the Normal Operation (cleared) state, the output begins to advance the position number on the rising edge of the CLK signal following the rise of the STB signal. Sample Timing Chart for the Output Enable Setting When the Output Enable setting is set to the Output Off state, the outputs are turned off and set to the high-impedance state on the rising edge of the STB signal. Note, however, that since the internal clock continues to operate, the position number advances as long as a clock signal (CLK) is input. Therefore, when the Output Enable setting is next set to the Output On (cleared) state, the output is turned on at the STB signal rising edge and the output levels at that time will be those for the position number to which the state has advanced due to the CLK signal input. No. A0167-13/23 LV8054LP DC Motor and Voice Coil Motor Drive Methods (Channels 3 and 4) When channels 3 and 4 are used to drive a DC or voice coil motor, the drive polarity is set with the serial data. The procedure for setting the drive polarity is shown below. (See subsection, Serial Logic Table 2, in section, Truth Tables, for a detailed description of this data.) Setting Procedure (1) Select PWM signal input with the CLK2/PWM selection item in the serial data. → This sets up the signal input to the CLK2/PWM pin to be accepted as a PWM signal for channel 3 or channel 4. (In this case, it is not used as a clock signal.) (2) If the output is to be controlled by PWM control, set up PWM mode and PWM signal allocation with the serial data. (3) Set the drive polarity for each channel with the serial data. (4) If the output is to be controlled by PWM control, input the PWM signal to the CLK2/PWM pin. The following tables describe the correspondence between the PWM signal and the output logic. Operation in Slow Decay Mode (forward/reverse ↔ brake) Serial input D4 D5 0 D6 PWM input D7 CLK2/PWM Output Mode OUT5 OUT6 0 OFF OFF 1 0 H L OUT5 → OUT6 0 1 L H OUT6 → OUT5 1 1 L L L OUT7 OUT8 Standby mode Brake mode 0 0 OFF OFF Standby mode 1 0 0 1 H L OUT7 → OUT8 L H 1 1 OUT8 → OUT7 L L Brake mode 0 0 OFF OFF Standby mode 1 0 L L Brake mode 0 1 L L Brake mode 1 1 L L H Brake mode 0 0 OFF OFF Standby mode 1 0 L L Brake mode 0 1 L L Brake mode 1 1 L L Brake mode No. A0167-14/23 LV8054LP Operation in Fast Decay Mode (forward/reverse ↔ standby mode) Serial input D4 D5 0 D6 PWM input D7 CLK2/PWM Output Mode OUT5 OUT6 0 OFF OFF Standby mode 1 0 H L OUT5 → OUT6 0 1 L H OUT6 → OUT5 1 1 L L Brake mode L OUT7 OUT8 0 0 OFF OFF Standby mode 1 0 H L OUT7 → OUT8 0 1 L H OUT8 → OUT7 1 1 L L Brake mode 0 0 OFF OFF Standby mode 1 0 OFF OFF Standby mode 0 1 OFF OFF Standby mode 1 1 L L H Brake mode 0 0 OFF OFF Standby mode 1 0 OFF OFF Standby mode 0 1 OFF OFF Standby mode 1 1 L L Brake mode Constant Voltage Control Setup Procedure for Channels 1 to 4 The constant voltage set value for channels 1 to 4 can be set separately for channels 1 and 2 and for channels 3 and 4. (See subsections, Serial Logic Table 3, and, Serial Logic Table 4, in section, Truth Tables, for a detailed description of this data.) The reference voltage used as the basis for operation can be selected to be either the internal reference voltage (0.88V) or the external input voltage (the voltage applied to the VC pin). The reference voltage selected as described above is voltage divided by the ratio set by the VC voltage divisor set by the serial data. The result of that voltage division operation is multiplied by five by the output constant voltage circuit and then output. The following formulas can be used to calculate the output constant voltage for the individual cases. When the internal reference voltage is used: (output constant voltage) = (internal reference voltage (0.88 V)) × (VC voltage divisor) × 5 When the external reference voltage (VC input voltage) is used: (output constant voltage) = (VC input voltage) × (VC voltage divisor) × 5 No. A0167-15/23 LV8054LP Voice Coil Motor and Stepping Motor Drive Methods (Channels 5 and 6) When channel 5 or 6 is used to drive either a voice coil motor or stepping motor, the drive polarity can be set with either serial data or parallel data (the IN51, IN52, IN61, and IN62 input signals). This section describes the procedures used for these settings. (See subsection, Serial Logic Table 2, in section, Truth Tables, for a detailed description of this data.) Setting Procedure Using Serial Data A: Channel 5 1. Set the IN51 and IN52 pins to the low level. (Alternative, they may be left open.) 2. Set the drive polarity with the serial data B: Channel 6 1. Set the IN61 and IN62 pins to the low level. (Alternative, they may be left open.) 2. Set the drive polarity with the serial data Setting Procedure Using Parallel Data The IN51 and IN52 pins are used to set the channel 5 drive polarity and the IN61 and IN62 pins are used to set the channel 6 drive polarity. The truth table for this function is shown below. Parallel inputs IN51 IN52 IN61 Outputs IN62 OUT9 OUT10 Mode OUT11 OUT12 L L L L Standby mode L H L H OUT10 → OUT9 H L H L OUT9 → OUT10 H H L L Brake L L L L Standby mode L H L H OUT12 → OUT11 H L H L OUT11 → OUT12 H H L L Brake Serial priority Parallel priority Serial priority Parallel priority Constant Current Control Settings (channels 5 and 6) The constant current settings for channels 5 and 6 are set individually for each channel. (See subsection, Serial Logic Table 5, in section, Truth Tables, for a detailed description of this data.) The output constant current is set by the constant current reference voltage set with the serial data and the resistor (RF) connected between the RF1 and RF2 pins. The following formula can be used to calculate the output constant current. (output constant current) = (constant current reference voltage) / (value of the resistor RF) PI Output Drive Method When the PI output is used to drive a photosensor, the drive on/off state is set from the serial data. (See subsection, Serial Logic Table 5, in section, Truth Tables, for a detailed description of this data.) Schmitt Buffer Hysteresis Setting The presence or absence of hysteresis in the BO1, BO2, and BO3 Schmitt buffer outputs can be set individually with the serial data. (See subsection, Serial Logic Table 5, in section, Truth Tables, for a detailed description of this data.) No. A0167-16/23 LV8054LP Truth Tables Serial Logic Table 1 Input D0 0 1 D1 0 0 D2 0 0 Setting mode Content set D3 D4 D5 D6 D7 0 * * * * AF Excitation CW (clockwise) 1 * * * * Direction CCW (counterclockwise) * 0 * * * AF Excitation 2-phase excitation * 1 * * * mode 1-2 phase excitation * * 0 * * * * 1 * * Hold * * * 0 * AF Counter Reset * * * 1 * Reset Clear * * * * 0 AF Output Output Off * * * * 1 Enable Output On 0 * * * * Zoom Excitation CW (clockwise) 1 * * * * Direction CCW (counterclockwise) * 0 * * * Zoom Excitation 2-phase excitation * 1 * * * Mode 1-2 phase excitation * * 0 * * Zoom Clear Hold Notes Channels set 1ch 2ch 3ch 4ch 5ch 6ch AF Step/Hold Serial data PI activation timing CLK1 CLK2 STB Clear * * 1 * * Step/Hold * * * 0 * Zoom Counter Reset * * * 1 * Reset Clear * * * * 0 Zoom Output Output Off * * * * 1 Enable Output On No. A0167-17/23 LV8054LP Serial Logic Table 2 Input D0 D1 D2 D3 0 0 1 0 1 D4 D5 D6 D7 0 0 * * 1 0 * * 0 1 * * 1 1 * * * * 0 0 * * 1 0 * * 0 1 * * 1 1 0 0 * * 1 0 * * 0 1 * * 1 1 * * * * 0 0 1 0 Content set drive polarity (3ch) OUT5 → OUT6 OUT6 → OUT5 drive polarity (4ch) OUT7 → OUT8 OUT8 → OUT7 drive polarity (5ch) OUT9 → OUT10 OUT10 → OUT9 OFF OUT11-12 OUT11 → OUT12 0 1 * * 1 1 0 * * * * CLK2/PWM CLK2 signal input 1 * * * * selection * 0 * * * PWM signal input Slow Decay (Forward/reverse ↔ brake) Fast Decay (Forward/reverse ↔ standby mode) drive polarity (6ch) 1 * * * * * 0 0 * * * 1 0 * PWM signal * * 0 1 * allocation * * 1 1 * * 0 1 OUT12 → OUT11 *3 Brake * * *2 Brake 0 * *1 OFF OU9-10 1 * *1 Brake * * CLK1 CLK2 STB OFF OUT7-8 * * activation timing Brake * * PI OFF OUT5-6 * * Notes 1ch 2ch 3ch 4ch 5ch 6ch PWM mode 1 Serial data Channels set Setting mode *4 *5 *6 OFF Channel 3 only Channel 4 only Both channels 3 and 4 (Dummy data) No. A0167-18/23 LV8054LP Serial Logic Table 3 Input D0 0 D1 0 D2 1 Setting mode Content set D3 D4 D5 D6 D7 0 0 0 0 * 100% (4.4V) 1 0 0 0 * 97.7% (4.3V) 0 1 0 0 * 95.5% (4.2V) 1 1 0 0 * VC voltage 93.2% (4.1V) 0 0 1 0 * divisor 90.9% (4.0V) 1 0 1 0 * 0 1 1 0 * 1 1 1 0 * indicate the 84.1% (3.7V) output voltage 81.8% (3.6V) Notes Channels set Serial data PI 1ch 2ch 3ch 4ch 5ch 6ch (The values in parentheses 86.4% (3.8V) 0 0 1 * 1 0 0 1 * 0 1 0 1 * 1 1 0 1 * 0 0 1 1 * 72.7% (3.2V) 1 0 1 1 * 70.5% (3.1V) 0 1 1 1 * 68.2% (3.0V) 1 1 1 1 * * * * * 0 VC voltage 65.9% (2.9V) Internal reference voltage (0.88V) * * * * 1 selection VC input voltage Setting mode Content set internal reference voltage (0.88V) is used.) CLK1 CLK2 STB 88.6% (3.9V) 0 value when the activation timing *7 79.5% (3.5V) 77.3% (3.4V) 75.0% (3.3V) Serial Logic Table 4 Input D0 1 D1 0 D2 1 D3 D4 D5 D6 D7 0 0 0 0 * 100% (4.4V) 1 0 0 0 * 97.7% (4.3V) 0 1 0 0 * 95.5% (4.2V) 1 1 0 0 * VC voltage 93.2% (4.1V) 0 0 1 0 * Divisor 90.9% (4.0V) 1 0 1 0 * 0 1 1 0 * 1 1 1 0 * indicate the 84.1% (3.7V) 0 0 0 1 * output voltage 81.8% (3.6V) 1 0 0 1 * 0 1 0 1 * 1 1 0 1 * 0 0 1 1 * 72.7% (3.2V) 1 0 1 1 * 70.5% (3.1V) Notes Channels set 1ch 2ch 3ch 4ch 5ch 6ch (The values in parentheses value when the internal reference voltage (0.88V) is used.) Serial data PI activation timing CLK1 CLK2 STB 88.6% (3.9V) 86.4% (3.8V) *7 79.5% (3.5V) 77.3% (3.4V) 75.0% (3.3V) 0 1 1 1 * 68.2% (3.0V) 1 1 1 1 * 65.9% (2.9V) * * * * 0 VC voltage Internal reference voltage (0.88V) * * * * 1 selection VC input voltage No. A0167-19/23 LV8054LP Serial Logic Table 5 Input D0 0 1 D1 1 1 D2 1 Setting mode Content set D3 D4 D5 D6 D7 0 0 0 0 * 0.200V 1 0 0 0 * 0.170V 0 1 0 0 * 0.165V 1 1 0 0 * 0.160V 0 0 1 0 * 0.155V 1 0 1 0 * 0.150V 0 1 1 0 * Constant 0.145V 1 1 1 0 * current 0.140V 0 0 0 1 * reference 0.135V voltage 0 0 1 * 0 1 0 1 * 0.125V 1 1 0 1 * 0.120V 0 0 1 1 * 0.115V 1 0 1 1 * 0.110V 0 1 1 1 * 0.105V 1 1 1 1 * 0.100V * * * * 0 Channel OUT9-10 (5ch) OUT11-12 (6ch) * * * * 1 0 * * * * Photosensor OFF 1 * * * * drive ON Buffer output hysteresis (BI1/BO1) Present Buffer output hysteresis (BI2/BO2) Present Buffer output hysteresis (BI3/BO3) Present 0 * * * 1 * * * * * 0 * * * * 1 * * * * * 0 * * * * 1 * * * * * 0 * * * * 1 1 Serial data PI activation timing CLK1 CLK2 STB 0.130V selection * Channels set 1ch 2ch 3ch 4ch 5ch 6ch 1 * Notes Absent Absent Absent (Dummy data) Notes *1. The operating mode can be switched between forward (or reverse) ↔ brake mode and forward (or reverse) ↔ standby mode operation with the CLK2/PWM pin in combination with notes 5 and 6 below. *2. These serial inputs are only accepted when the parallel inputs IN51 and IN52 are both at the low level. In all other states, the serial input will be ignored. *3. These serial inputs are only accepted when the parallel inputs IN61 and IN62 are both at the low level. In all other states, the serial input will be ignored. *4. Selects whether the CLK2/PWM input functions as a stepping motor clock (CLK2) or a DC motor PWM signal (PWM). *5. Forcibly switches the logic of note 1 to brake mode when the CLK2/PWM input is high. *6. Forcibly switches the logic of note 1 to standby mode when the CLK2/PWM input is high. *7. Voltage divisor for the VC voltage divider circuit. After either the VC input voltage or the internal reference voltage is voltage divided by this ratio, the result of that division is multiplied by five by the output constant voltage circuit. No. A0167-20/23 LV8054LP Pin Internal Equivalent Circuits Pin No. Symbol 1 BI1 39 BI2 32 BI3 4 OUT11 2 OUT12 3 RF2 27 OUT9 29 OUT10 28 RF1 10 OUT5 9 OUT6 7 OUT7 6 OUT8 Equivalent circuit Continued on next page. No.A0167-21/23 LV8054LP Continued from preceding page. Pin No. Symbol 21 OUT1 22 OUT2 24 OUT3 25 OUT4 11 ST 12 CLK1 13 CLK2/PWM 14 IN51 15 IN52 16 IN61 17 IN62 18 SCLK 19 STB 20 DATA 30 VC 40 BO1 38 BO2 31 BO3 35 PI Equivalent circuit No.A0167-22/23 LV8054LP SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2007. Specifications and information herein are subject to change without notice. PS No.A0167-23/23