SANYO LV8041FN

Ordering number : ENN7944
SANYO Semiconductors
DATA SHEET
LV8041FN
Bi-CMOS IC
 Seven-Channel Motor Driver IC
for Digital Cameras
Overview
The LV8041FN is a digital camera motor driver IC that integrates seven driver channels on a single chip.
Features
• Two PWM current control microstepping drive stepping motor driver channels
• One constant current forward/reverse motor driver
• Two PWM drive forward/reverse motor driver channels (one channel of which can be switched to function as a
microstepping drive stepping motor driver)
• Stepping motor drivers 1 and 2 support 2-phase, 1-2 phase, 2W1-2 phase, and 4W1-2 phase drive.
• Stepping motor driver 3 operates in fixed 2W1-2 phase drive mode.
• Microstepping drive step advance can be controlled with a single clock input (stepping motor drivers 1, 2, and 3)
• The constant current control chopping frequency can be adjusted with an external resistor (stepping motor drivers
1, 2, and 3)
• Phase detection monitor pins provided (stepping motor drivers 1, 2, and 3)
• The states of all of the drivers can be set up and controlled over an 8-bit serial data interface.
Specifications
Absolute Maximum Ratings at Ta
Parameter
25qC
Symbol
Conditions
Ratings
Unit
Supply voltage 1
Vmmax
6
Supply voltage 2
VCCmax
6
Peak output current
IOpeak
1ch/2ch/3ch/4ch/5ch/6ch/7ch
Continuous output current
Allowable power dissipation
V
V
600
mA
IOmax
1ch/2ch/3ch/4ch/5ch/6ch/7ch
400
mA
Pd max1
Independent IC
0.35
W
Pd max2
Mounted on a 30 u 50 u 0.8 mm glass epoxy PCB
2.2
W
Operating temperature
Topr
20 to 85
qC
Storage temperature
Tstg
55 to 150
qC
Allowable Operating Ranges at Ta
Parameter
25qC
Symbol
Conditions
Ratings
Unit
Supply voltage range 1
VM
2 to 5.5
V
Supply voltage range 2
VCC
2.7 to 5.5
V
Logic input voltage
Chopping frequency
0 to VCC 0.3
VIN
fchop
1ch, 2ch, 3ch, 4ch, 5ch, 6ch
Clock frequency
fCLK
CLK12, CLK34, CLK56
PWM frequency
fPWM
PWM5, PWM6
50 to 200
V
KHz
Up to 64
KHz
Up to 100
KHz
„
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control
systems, or other applications whose failure can be reasonably expected to result in serious physical and/or
material damage. Consult with your SANYO representative nearest you before using any SANYO products
described or contained herein in such applications.
„
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
81004TN (OT) No. 7944-1/24
LV8041FN
Electrical Characteristics at Ta = 25°C, VM = 5 V, VCC = 5 V
Parameter
Standby mode current drain
Symbol
Istn
IM
Current drain
ICC
Conditions
ST
Ratings
min
typ
max
1
PA
50
100
PA
3.5
4.5
5.5
mA
low
ST high
PWM5
PWM6
IN72
high, No load
PWM6
IN72 high, No load
ST high
PWM5
Unit
VCC low-voltage cutoff voltage
VthVCC
2.1
2.35
2.6
V
Low-voltage sensing hysteresis
VthHIS
100
150
200
mV
VG reference voltage
VGL
4.5
4.7
5.0
V
Charge pump step-up voltage
VGH
8.5
9
9.5
V
Charge pump startup time
tONG
C (VGH)
0.1
0.2
ms
Charge pump oscillator frequency
Fchg
R
100
125
150
kHz
TSD
Design guarantee value
150
160
170
qC
'TSD
Design guarantee value
5
10
20
qC
0.45
0.55
:
0.45
0.55
:
1
50
PA
0.9
1.2
V
1.0
PA
70
PA
Thermal shutdown temperature
Thermal shutdown hysteresis
0.1 PF
20 k:
Stepping Motor Drivers (Channels 1, 2, 3, and 4)
Ronu
Output on-resistance
Rond
Ta
25qC, IO
400mA,
Upper side on-resistance
Ta
25qC, IO
400mA,
Lower side on-resistance
Output leakage current
IOleak
Diode forward voltage
VD1
ID
IINL
VIN
0 V (ST, CLK12, CLK34)
5 V (ST, CLK12, CLK34)
Logic pin input current
400mA
IINH
VIN
Logic high-level input voltage
VINH
ST, CLK12, CLK34
Logic low-level input voltage
VINL
ST, CLK12, CLK34
4W1-2 phase
drive
Current selection
reference voltage
levels
2W1-2 phase
drive
1-2 phase
drive
2-phase drive
Chopping frequency
Monitor pin (MO pin) output voltage
Fchop
0.6
50
3.5
V
1.5
V
Step 16 (Initial state, channel 1 comparator
level)
0.188
0.2
0.218
V
Step 15 (Initial state 1)
0.188
0.2
0.218
V
Step 14 (Initial state 2)
0.188
0.2
0.218
V
Step 13 (Initial state 3)
0.177
0.192
0.207
V
Step 12 (Initial state 4)
0.170
0.185
0.200
V
Step 11 (Initial state 5)
0.163
0.178
0.193
V
Step 10 (Initial state 6)
0.156
0.171
0.186
V
Step 9 (Initial state 7)
0.148
0.163
0.178
V
Step 8 (Initial state 8)
0.133
0.148
0.163
V
Step 7 (Initial state 9)
0.117
0.132
0.147
V
Step 6 (Initial state 10)
0.100
0.115
0.130
V
Step 5 (Initial state 11)
0.083
0.098
0.113
V
Step 4 (Initial state 12)
0.065
0.080
0.095
V
Step 3 (Initial state 13)
0.050
0.062
0.077
V
Step 2 (Initial state 14)
0.030
0.043
0.058
V
Step 1 (Initial state 15)
0.010
0.023
0.038
V
Step 16 (Initial state, channel 1 comparator
level)
0.188
0.2
0.218
V
Step 14 (Initial 1)
0.188
0.2
0.218
V
Step 12 (Initial 2)
0.170
0.185
0.200
V
Step 10 (Initial 3)
0.156
0.171
0.186
V
Step 8 (Initial 4)
0.133
0.148
0.163
V
Step 6 (Initial 5)
0.100
0.115
0.130
V
Step 4 (Initial 6)
0.065
0.080
0.095
V
Step 2 (Initial 7)
0.030
0.043
0.058
V
Step 16 (Initial state, channel 1 comparator
level)
0.188
0.2
0.218
V
Step 8 (Initial state + 1)
0.133
0.148
0.163
V
Step 8
0.188
0.2
0.218
100
125
150
4.5
4.9
VCC
V
0
0.1
0.5
V
R
20 k:
VMOH
IMO
50 PA, VM
VMOL
IMO
50 PA
5V
V
kHz
Continued on next page
No.7944-2/24
LV8041FN
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
H Bridge Drivers (Channels 5 and 6)
Ronu
Output on-resistance
Rond
Ta
25qC, IO
400 mA,
Upper side on-resistance
Ta
25qC, IO
400 mA,
Lower side on-resistance
Output leakage current
IOleak
Diode forward voltage 1
VD1
ID
IINL
VIN
0 V (PWM5, PWM6)
5 V (PWM5, PWM6)
Logic pin input current
400 mA
IINH
VIN
Logic high-level input voltage
VINH
PWM5, PWM6
Logic low-level input voltage
VINL
PWM5, PWM6
0.6
2W1-2
phase
drive
Monitor pin (MO56 pin) output
voltage
Current control reference voltage
0.55
:
0.45
0.55
:
1
50
PA
0.9
1.2
V
1.0
PA
70
PA
50
3.5
Step 16 (Initial state, channel 5 comparator
level)
Current selection
reference levels when
microstepping is
selected
0.45
0.188
V
0.2
1.5
V
0.218
V
Step 14 (Initial state +1)
0.188
0.2
0.218
V
Step 12 (Initial state +2)
0.170
0.185
0.200
V
Step 10 (Initial state +3)
0.156
0.171
0.186
V
Step 8 (Initial state +4)
0.133
0.148
0.163
V
Step 6 (Initial state +5)
0.100
0.115
0.130
V
Step 4 (Initial state +6)
0.065
0.080
0.095
V
Step 2 (Initial state +7)
0.030
0.043
0.058
V
4.5
4.9
VCC
V
0
0.1
0.5
V
VMOH
IMO
50 PA, VM
VMOL
IMO
50 PA
VSEN1
(D7, D6)
(0, 0)
0.188
0.2
0.218
V
VSEN2
(D7, D6)
(0, 1)
0.119
0.134
0.149
V
VSEN3
(D7, D6)
(1, 0)
0.085
0.1
0.115
V
VSEN4
(D7, D6)
(1, 1)
0.051
0.066
0.081
V
0.5
0.6
:
0.5
0.6
:
1
50
PA
0.9
1.2
V
1.0
PA
70
PA
5V
Constant Current Forward/Reverse Motor Driver (Channel 7)
Ronu
Output on-resistance
Rond
Ta
25qC, IO
400 mA,
Upper side on-resistance
Ta
25qC, IO
400 mA,
Lower side on-resistance
Output leakage current
IOleak
Diode forward voltage 1
VD1
ID
IINL
VIN
0 V (IN71, IN72)
5 V (IN71, IN72)
Logic pin input current
400 mA
IINH
VIN
Logic high-level input voltage
VINH
IN71, IN72
Logic low-level input voltage
VINL
IN71, IN72
Constant current output
VREF7 output voltage
LIM7 input current
IOUT
Rload
3 :, RF
LIM7
0.2 V
LIM7
0V
0.6
0.5 :,
VREF7
ILIM7
50
3.5
V
1.5
V
mA
384
400
416
0.19
0.2
0.21
V
1.0
PA
FC7 Rapid charge current
Irafc7
500
670
850
PA
FC7 steady-state charge current
Ichfc7
5
10
15
PA
FC7 steady-state discharge current
Idisfc7
5
10
15
PA
1.0
PA
70
PA
Serial Data Transfer Pins
IINL
VIN
0 V (SCLK, DATA, STB)
IINH
VIN
5 V (SCLK, DATA, STB)
Logic high-level input voltage
VINH
SCLK, DATA, STB
Logic low-level input voltage
VINL
SCLK, DATA, STB
Minimum SCLK high-level pulse width
Tsch
Minimum SCLK low-level pulse width
Stipulated STB time
Logic pin input current
50
3.5
V
1.5
V
0.125
Ps
Tscl
0.125
Ps
Tlat
0.125
Ps
Tlatw
0.125
Ps
Data setup time
Tds
0.125
Ps
Data hold time
Tdh
0.125
Maximum CLK frequency
Fclk
Minimum STB pulse width
Ps
4
MHz
No.7944-3/24
LV8041FN
Fclk
Tsch Tscl
CLK
Tds Tdh
DATA
D0
D1
D7
D6
D2
Tlat
SET
Tlatw
Package Dimensions
unit: mm
3305
SANYO : VQFN52 (7.0 u 7.0)
Allowable power dissipation, Pd max -- W
Pd max
-- Ta
2.5
Specified PCB: 30.0
2.2
× 50.0 × 0.8 mm
PCB material: glass epoxy
2.0
1.5
1.14
1.0
0.5
Independent IC
0.35
0.18
0
--20
0
20
40
Ambient temperature, Ta
60
--
80
°C
100
ILV00179
No.7944-4/24
CLK12
MO12
IN72
IN71
VREF7
LIM7
FC7
VGH
CPH2
CPH1
VGL
CPL2
Pin Assignment
PGND1
LV8041FN
52
51
50
49
48
47
46
45
44
43
42
41
40
OUT1A 1
39
CPL1
SEN1 2
38
VM7
OUT1B 3
37
OUT7B
VM12 4
36
SEN7
OUT2A 5
35
OUT7A
SEN2 6
34
PGND
33
OUT6B
32
SEN6
SEN3 9
31
OUT6A
OUT3B 10
30
VM56
VM34 11
29
OUT5B
OUT4A 12
28
SEN5
SEN4 13
27
OUT5A
LV8041FN
OUT2B 7
STB
SCLK
VCC
R
PWM5/
CLK56
CLK12
PGND12 PWM6/
MO56
MO12
DATA
52
IN72
GND
51
IN71
26
VREF7
25
LIM7
24
FC7
23
VGH
22
MO34
21
CPH2
20
CLK34
19
CPH1
18
OUT4B
17
VGL
16
PGND3
15
CPL2
14
ST
OUT3A 8
40
41
42
43
44
45
46
47
48
49
50
Top view
CPL1
39
1
OUT1A
VM7
38
2
SEN1
OUT7B
37
3
OUT1B
SEN7
36
4
VM12
OUT7A
35
5
OUT2A
PGND
34
6
SEN2
OUT6B
33
7
OUT2B
SEN6
32
8
OUT3A
OUT6A
31
9
SEN3
VM56
30
10
OUT3B
OUT5B
29
11
VM34
SEN5
28
12
OUT4A
OUT5A
27
13
SEN4
24
23
22
21
20
19
18
17
16
15
14
VCC
SCLK
STB
DATA
GND
ST
MO34
CLK34
OUT4B
PGND3
25
PWM5/
CLK56
PWM6/
MO56
26
R
LV8041FN
Bottom view
No.7944-5/24
OUT1A
SEN1
LVS
OUT1B
Charge pump circuit
LVS
TSD
VGH VGL
VGL
VGH
Channel 5
Bridge driver
TSD LVS
logic
Output control
4
2
Reference
voltage
circuit
Channel 6
Bridge driver
Constant
current
selection
circuit
0.2 V
Current
selection
circuit
logic
VGL
VGH
VGL
Channel 7
Bridge driver
Channel 3
Bridge driver
VGH
OUT3A
GND
SEN2
TSD
OUT2A
VCC
CLK12
VCC
SCLK
OSC
R
ST
DATA
Current
selection
circuit
MO34
Output control
CLK34
converter
OUT3B
logic
5
SEN3
Channel 2
MO12
Output control
STB
Serial-parallel
TSD LVS
VGL
VGH
logic
Output control
Channel 4
Bridge driver
VM34
Channel 1
OUT2B
Bridge driver
5
TSD LVS
OUT4B
PGND12
VM12
Bridge driver
TSD LVS
M
SEN4
VGL
VGH
M
PGND7
LIM7
VREF7
VM7
PGND34
LV8041FN
Block Diagram
IN72
IN71
FC7
OUT4A
SEN7
OUT7B
OUT7A
OUT6B
OUT6A
SEN6
PWM6/
MO56
PWM5/
CLK56
SEN5
OUT5B
OUT5A
VM56
VGH
CPH2
CPH1
VGL
CPL2
CPL1
No.7944-6/24
LV8041FN
Pin Functions
Pin No.
Symbol
4
VM12
Pin description
1
OUT1A
3
OUT1B
2
SEN1
5
OUT2A
7
OUT2B
6
SEN2
52
PGND12
51
CLK12
STP 1: Clock signal input
50
MO12
STP 1: Phase detector monitor
22
SCLK
Serial data transfer clock input
20
DATA
Serial data input
21
STB
24
R
STP 1: Motor power supply
STP 1: Channel 1 OUTA output
STP 1: Channel 1 OUTB output
STP 1: Channel 1 current sensing resistor connection
STP 1: Channel 2 OUTA output
STP 1: Channel 2 OUTB output
STP 1: Channel 2 current sensing resistor connection
STP 1: Power system ground
Serial data latch pulse input
Oscillator frequency setting resistor connection
11
VM34
8
OUT3A
STP 2: Motor power supply
STP 2: Channel 3 OUTA output
10
OUT3B
STP 2: Channel 3 OUTB output
9
SEN3
12
OUT4A
STP 2: Channel 3 current sensing resistor connection
15
OUT4B
13
SEN4
14
PGND34
16
CLK34
17
MO34
STP 2: Phase detector monitor
30
VM56
PWM: Channels 5 and 6 motor power supply
27
OUT5A
PWM: Channel 5 OUTA output
STP 3: Channel 5 OUTA output
29
OUT5B
PWM: Channel 5 OUTB output
STP 3: Channel 5 OUTB output
STP 2: Channel 4 OUTA output
STP 2: Channel 4 OUTB output
STP 2: Channel 4 current sensing resistor connection
STP 2: Power system ground
STP 2: Clock signal input
28
SEN5
25
PWM5/CLK56
STP 3: Channel 5 current sensing resistor connection
31
OUT6A
PWM: Channel 6 OUTA output
STP 3: Channel 6 OUTA output
33
OUT6B
PWM: Channel 6 OUTB output
STP 3: Channel 6 OUTB output
PWM: Channel 5 PWM signal input
STP 3: Clock signal input
32
SEN6
26
PWM6/MO56
STP 3: Channel 6 current sensing resistor connection
38
VM7
45
FC7
36
SEN7
35
OUT7A
37
OUT7B
Constant current drive: Channel 7 OUTB output
48
IN71
Constant current drive: Channel 7 logic input 1
49
IN72
Constant current drive: Channel 7 logic input 2
34
PGND7
47
VREF7
46
LIM7
Constant current drive: Channel 7 constant current setting
39
CPL1
Charge pump capacitor connection
40
CPL2
Charge pump capacitor connection
42
CPH1
Charge pump capacitor connection
43
CPH2
41
VGL
44
VGH
18
ST
PWM: Channel 6 PWM signal input
STP 3: Phase detector monitor
Constant current drive: Channel 7 motor power supply
Constant current drive: Channel 7 phase compensation capacitor connection
Constant current drive: Channel 7 current sensing resistor connection
Constant current drive: Channel 7 OUTA output
Constant current drive: Channel 7 power system ground
Constant current drive: Channel 7 current control reference voltage output
Charge pump capacitor connection
Lower side DMOS gate voltage capacitor connection
Upper side DMOS gate voltage capacitor connection
Chip enable
23
VCC
Logic system power supply
19
GND
Signal system ground
No.7944-7/24
LV8041FN
Serial Data Input Specifications
x Register (D1, D0): Data transfer target register selection
D1
D0
0
0
Monitor/channels 5 and 6 drive mode settings
Mode
0
1
STP1 settings
1
0
STP2 settings
1
1
PWM/STP3 settings
The D1 and D0 bits in the serial data select the register used to set the motor driver state as shown above.
x Monitor/channel 5 and 6 drive mode settings
Register No.
Data
D0
0
RG_SELECT1
Symbol
Register selection 1
Functions
D1
0
RG_SELECT2
Register selection 2
D2
1 or 0
MO_SELECT1
MO12 output selection 1
D3
1 or 0
MO_SELECT2
MO12 output selection 2
D4
1 or 0
MO12_MD
MO12 output mode setting
D5
1 or 0
MO34_MD
MO34 output mode setting
D6
1 or 0
MO56_MD
MO56 output mode setting
D7
1 or 0
PWM/MICRO
Channel 5 and 6 drive mode setting
x STP1 Settings
Register No.
Data
D0
1
RG_SELECT1
Symbol
Functions
D1
0
RG_SELECT2
Register selection 2
D2
1 or 0
F/R1
Forward/reverse setting
D3
1 or 0
MS11
Microstep selection 1
D4
1 or 0
MS12
Microstep selection 2
D5
1 or 0
HOLD1
Step/hold setting
D6
1 or 0
RESET1
Logic reset
D7
1 or 0
OUT ENABLE1
Output enable
Channel
Register selection 1
1ch, 2ch
(STP1)
x STP2 Settings
Register No.
Data
D0
0
RG_SELECT1
Symbol
Functions
D1
1
RG_SELECT2
Register selection 2
D2
1 or 0
F/R2
Forward/reverse setting
D3
1 or 0
MS21
Microstep selection 1
D4
1 or 0
MS22
Microstep selection 2
D5
1 or 0
HOLD2
Step/hold setting
D6
1 or 0
RESET2
Logic reset
D7
1 or 0
OUT ENABLE2
Output enable
Channel
Register selection 1
3ch, 4ch
(STP2)
x Channel 5 and 6 Driver Settings
Symbol
Functions
Channel 5 and 6 drive mode
setting register D7
Register No.
Data
D0
1
RG_SELECT1
D1
1
RG_SELECT2
D2
1 or 0
“0”
F/R5
PWM mode
STP3 mode
Channel
“1”
Register selection 1
Register selection 2
F/R3
Forward/reverse setting
Forward/reverse setting
Step/hold setting
D3
1 or 0
DECAY5
HOLD3
Current attenuation mode
setting
D4
1 or 0
F/R6
RESET3
Forward/reverse setting
Logic reset
OUT
ENABLE3
Current attenuation mode
setting
Output enable
5ch
PWM
5ch/6ch
STP
6ch
PWM
D5
1 or 0
DECAY6
D6
1 or 0
VSEN1
Current control reference voltage selection 1
5ch/6ch
D7
1 or 0
VSEN2
Current control reference voltage selection 2
STP
No.7944-8/24
LV8041FN
Serial Data Input Settings
ST
DATA
D0
D1
D2
D3
D4
D5
D6
D7
SCLK
STB
State setting data latched
Data is input in order from data bit 0 to data bit 7. The data is transferred on the clock signal rising edge and after all
the data has been transferred, it is latched on the rising edge of the STB signal.
x Timing with which the serial data is reflected in the output
Type 1: For the forward/reverse (FR) and drive mode (MS) settings in STP setting mode, after the data is latched,
after the clock falling edge is detected, the new settings are reflected in the output on the next rising edge
on the clock signal.
Type 2: For the reset and output enable settings, after the data is latched, the new settings are reflected in the output
on the next rising edge on the clock signal.
Type 3: For settings other than those listed above, the new settings are reflected in the output at the same time as
the data is latched with the STB signal.
CLK
CLK
Falling edge detection
STB
STB
Data latch timing
F/R (STP)
MS
Example: 2-phase drive
Data latch timing
Reflected on the
rising edge
Example:
4W1-2 phase drive
RESET
ENABLE
Example: reset
Reflected on the rising edge
Example: Reset cleared
STB signal timing
Cases other
than those shown
at the left or above
No.7944-9/24
LV8041FN
Stepping Motor Drivers (STP1 (channels 1 and 2) and STP2 (channels 3 and 4))
Clock Function (STP1 (Items in parentheses refer to STP2))
Input
ST
CLK12 (CLK34)
Low
High
Operating mode
Charge pump circuit
Standby mode
Stopped
Drive step operate
Operating
High
Drive step hold
STP State Setting Serial Data Truth Table: Six bits (STP1/STP2 settings register)
D7 (OE)
D6 (RES)
D5 (HOLD)
D4 (MS2)
D3 (MS1)
D2 (F/R)
0
Clockwise (forward)
Operating mode
1
Counterclockwise (reverse)
0
0
2-phase drive
0
1
1-2 phase drive
1
0
2W1-2 phase drive
1
1
4W1-2 phase drive
0
Step/hold clear
1
Step/hold
0
Counter reset (Drive returns to the initial position)
1
Counter reset clear
0
Outputs set to the high-impedance state
1
Outputs set to the operating state
Note : Don’t Care
Initial Drive Position
Drive mode
1ch (3ch)
2ch (4ch)
2-phase
100
100
1-2 phase
100
0
2W1-2 phase
100
0
4W1-2
100
0
Procedure for Calculating the Set Current
IOUT = (reference voltage u set current ratio)/(sense resistor (SEN) value)
Since the reference voltage is 0.2 V, the following output current flows when the set current ratio is 100% and the
sense resistor is 1 :.
IOUT 0.2 V u 100/1 :
200 mA
Vary the value of the sense resistor (SEN) to vary the output current.
No.7944-10/24
LV8041FN
Output Current Vector Locus (One step is normalized to 90°)
T15
T16
T14
T13
100
T12
T8 (2-phase)
T11
T10
T9
80
Channel 1 (channel 3) phase current ratio (%)
T8
T7
60
T6
T5
40
T3
20
T2
T1
T0
0
0
20
40
60
80
100
Channel 2 (channel 4) phase current ratio (%)
Set Current Ratios in the Various Drive Modes
STEP
T0
4W1-2 phase (%)
1ch(3ch)
2W1-2 phase (%)
2ch(4ch)
1ch(3ch)
0
100
T1
8.69
100
T2
17.39
100
T3
26.08
95.65
T4
34.78
91.3
T5
43.48
86.95
T6
52.17
82.61
T7
60.87
78.26
T8
69.56
69.56
T9
78.26
60.87
T10
82.61
52.17
T11
86.95
43.48
T12
91.3
34.78
T13
95.65
26.08
T14
100
17.39
T15
100
8.69
T16
100
0
1-2 phase (%)
2ch(4ch)
1ch(3ch)
0
100
17.39
100
34.78
91.3
52.17
82.61
69.56
69.56
82.61
52.17
91.3
34.78
100
17.39
100
0
2 phase (%)
2ch(4ch)
1ch(3ch)
0
100
69.56
69.56
100
0
100
2ch(4ch)
100
No.7944-11/24
LV8041FN
2-Phase Drive (D4 = 0, D3 = 0, D2 = 0: clockwise mode)
CLK
MO
(%)
100
I1
0
100
(%)
100
I2
0
100
1-2 Phase Drive (D4 = 0, D3 = 1, D2 = 0: clockwise mode)
CLK
MO(initial)
MO(quarter)
(%)
100
I1
0
100
(% )
100
I2
0
100
No.7944-12/24
LV8041FN
2W1-2 Phase Drive (D4 = 1, D3 = 0, D2 = 0: clockwise mode)
CLK
MO(initial)
MO(quarter)
11(%)
2W1-2 phase drive (channel 1 (channel 3): clockwise)
100
80
60
40
20
0
-20 0
-40
-60
-80
-100
10
20
30
12(%)
2W1-2 phase drive (channel 2 (channel 4): clockwise)
100
80
60
40
20
0
-20 0
-40
-60
-80
-100
10
20
30
No.7944-13/24
LV8041FN
4W1-2 Phase Drive (D4 = 1, D3 = 1, D2 = 0: clockwise mode)
CLK
MO(initial)
MO(quarter)
100
80
60
11()
40
20
0
-20 0
10
20
30
40
50
60
10
20
30
40
50
60
-40
-60
-80
-100
100
80
60
12 ()
40
20
0
-20 0
-40
-60
-80
-100
No.7944-14/24
LV8041FN
Set Current Step Switching (CLK pin), Forward/Reverse Switching (D2 (F/R)) Basic Operation
D2 (F/R)
Clockwise mode
Counterclockwise
mode
Clockwise mode
CLK
Position
number
j
i
h
g
f
e f
g h
g f
Channel
1 output
Channel
2 output
The IC internal D/A converter advances by one bit on the rising edge of each input clock pulse.
The clockwise/counterclockwise direction mode is switched by the D2 (F/R) data bit, and the direction in which the
position number advances is changed by switching this mode.
In clockwise mode, the channel 2 current phase is delayed by 90° as seen from the channel 1 current.
In counterclockwise mode, the channel 2 current phase leads by 90° as seen from the channel 1 current.
Output Enable (D7) and Reset (D6) Operational Description
Power saving
mode
OE(D7)
CLK
CLK
MO
MO
Channel
1 output
Channel
1 output
0%
0%
Channel
2 output
Initial mode
RST(D6)
Channel
2 output
The outputs are in the high-impedance state
When OE (D7) is set to 0, the outputs will be turned off on the next clock rising edge and set to the high-impedance
state. However, since the internal logic circuits continue to operate, the position number will advance if the clock signal
is input. Therefore, when OE (D7) is returned to 1, the IC will output levels according to the position number that has
been advanced by the clock input.
When RST (D6) is set to 0, the outputs are set to the initial state at the next clock rising edge, and the MO output goes
to the low level. When RST (D6) is set to one after that, the operation starts from the initial state on the next clock
input, and the position number begins advancing.
No.7944-15/24
LV8041FN
logic
Hold Bit (D5) Operational Description
(External) clock
Internal clock
logic
Internal logic
HOLD(D5)
Step/hold
(1)
Step/hold
release
Step/hold
(2)
Step/hold
release
HOLD (D5)
(External)
clock
Held at the
low level
Internal
clock
Held at the
high level
Channel
1 output
0%
Channel
2 output
Hold state
Hold state
When the HOLD bit (D5) is set to 1, the internal clock signal is held at the state of the external clock at that point.
Since the external clock is low at the timing of the step/hold (1) operation in the figure, the internal clock is then held at
the low level. Similarly, since the external clock is high at the timing of the step/hold (2) operation in the figure, the
internal clock is then held at the high level.
When the HOLD bit (D5) is set to 0, the internal clock is synchronized with the normal (external) clock.
The outputs retain their states at the time the step/hold operation was input, and after the step/hold is released, they
proceed with the timing of the next input clock rising edge.
As long as the IC is in the hold state, the position number will not be advanced even if the external clock signal is input.
No.7944-16/24
LV8041FN
Current Control Operation Specifications
x Sine Wave Increasing Direction
CLK
Set current
Coil current
Set current
fchop
Current
mode
CHARGE
SLOW
FAST
CHARGE
SLOW
FAST
x Sine Wave Decreasing Direction
Each current mode operates with the following sequence.
CLK
S e t c u rre n t
C o il c u rre n t
S e t c u rre n t
fc h o p
C u rre n t
m ode
CHARGE
SLO W
FA S T
CHARGE
FA S T
CHARGE
SLO W
x The IC goes to charge mode during chopping oscillation startup. (A period in which the IC forcibly operates in
charge mode exists as 1/8 of a single chopping period regardless of the relationship between the magnitudes of the
coil current (ICOIL) and the set current (IREF).)
x During charge mode, the IC compares the coil current (ICOIL) and the set current (IREF).
If the ICOIL < IREF state occurs during charge mode:
Charge mode continues until ICOIL t IREF. After that, the IC switches to slow decay mode and then switches to
fast decay mode for the last 1/8 of a single chopping period.
If the ICOIL < IREF state does not occur during charge mode:
The IC switches to fast decay mode and the coil current is attenuated in fast decay mode until the end of the
single chopping period.
The IC repeats the above operation. Normally, in the sine wave increasing direction, the IC operates in slow (+ fast)
decay mode, and in the sine wave decreasing direction, the IC operates in fast decay mode until the current is attenuate
to the set level, and then the IC operates in slow decay mode.
No.7944-17/24
LV8041FN
x Setting the Chopping Frequency (fchop)
When this IC performs constant current control, it uses a chopping operation based on a frequency set by an
external resistor.
The chopping frequency set by the value of the resistor connected to the R pin (pin 24) is set as shown in the figure
below.
Chopping
frequency
ƒ`ƒ‡ƒbƒsƒ“ƒO
ü”g ”(kHz)
300
250
200
150
100
50
0
0
10
20
30
40
50
60
70
80
90
100
R’ ï Ri
kƒR¶j
Resistance,
(k:)
We recommend that a frequency in the range 50 kHz to 200 kHz be used.
Serial Data Truth Table for Monitor Output Settings (Monitor/channel 5 and 6 drive mode settings
register)
x MO12 Output Setting: 2 bits
D3(MO_SELECT2)
D2(MO_SELECT1)
0
0
The STP1 monitor is output
MO12 output state
0
1
The STP2 monitor is output
1
0
The STP3 monitor is output (If PWM/MICRO is 1.)
1
1
A fixed high level is output
The MO12 pin can be set up to output any of the stepping motor driver states shown in the table above with the monitor
settings register settings shown in that table.
x Monitor Output Mode Setting: 3 bits
D6 (MO56_MD)
D5 (MO34_MD)
D4 (MO12_MD)
Monitor output mode state
0
A low level is output from MO12 in the STP1 initial state
(Only when (D3, D2) (0, 0))
1
A low level is output from MO12 each STP1 1/4 period
(Only when (D3, D2) (0, 0))
0
A low level is output from MO34 in the STP2 initial state
(When (D3, D2) (0, 1) this is also output from MO12)
1
A low level is output from MO34 each STP2 1/4 period
(When (D3, D2) (0, 1) this is also output from MO12)
0
A low level is output from MO56 in the STP3 initial state
(When (D3, D2) (1, 0) this is also output from MO12)
1
A low level is output from MO56 each STP3 1/4 period
(When (D3, D2) (1, 0) this is also output from MO12)
Note : Don’t Care
The stepping motor driver monitor outputs can be switched between a mode in which an output is only provided in the
initial position and a mode in which an output is provided each 1/4 period by setting the monitor setting register as
shown in the table above.
No.7944-18/24
LV8041FN
PWM Drive Forward/Reverse Motor Driver (Channels 5 and 6)
Drive Mode Setting Serial Data Truth Table: 1 bit (Monitor/channel 5 and 6 drive mode settings register)
D7(PWM/MICRO)
Operating mode
Low
High
Pin functions
Pin 25
Pin 26
PWM: 2 systems
PWM5
PWM6
One microstep drive STP system
CLK56
MO56
The circuit operating mode can be switched between direct PWM drive H bridge drive operation and 2W1-2 phase
microstep drive stepping motor drive operation by setting the D7 bit (PWM/MAICRO) as shown in the table above.
PWM Drive Mode (Channels 5 and 6 drive mode setting register bit D7 = 0)
x Truth Table (Channels 5 and 6 driver settings register)
Inputs
PWM5
(PWM6)
ST
Outputs
D2
(D4)
D3
(D5)
OUTA
OUTB
Charge pump
circuit
Operating mode
Low
OFF
OFF
Standby mode
High
High
Low
High
Low
Clockwise (forward)
High
High
High
Low
High
Counterclockwise (reverse)
High
Low
Low
OFF
OFF
Fast decay (output off)
High
Low
High
Low
Low
Slow decay (short-circuit braking)
Stopped
Operating
Note : Don’t care
x Output Stage Transistor Functions
VM
VM
OFF
ON
U1
OUTB
L1
U2
OUTA
ON
OFF
U2
OUTA
L2
ON
(Forward)
OFF
U1
OUTB
L1
L2
OFF
ON
OFF
U1
U2
OUTA
VM
OUTB
L1
OFF
L2
ON
(Reverse)
ON
(Brake)
x Forward/Reverse Output Operation Timing Chart (D3 = 0)
D2 data
“L”
“H”
PW M5
U1
OFF
L1
OFF
ON
OFF
ON
U2
L2
OFF
ON
ON
Forward
High
im pedance
Forward
High
im pedance
Reverse
High
im pedance
Reverse
No.7944-19/24
LV8041FN
x Brake Mode Output Operation Timing Chart (D3 = 1)
D2 data
“L”
“H”
PWM5
U1
ON
OFF
L1
OFF
ON
U2
L2
OFF
ON
ON
OFF
Forward
Forward
Brake
Reverse
Brake
Brake
Reverse
Brake
Microstep Drive Mode (Channels 5 and 6 drive mode setting register bit D7 = 1)
Clock Function (STP3)
Input
ST
CLK56
Low
Operating mode
Charge pump circuit
Standby mode
Stopped
High
Drive step mode
High
Drive step hold
Operating
STP State Setting Serial Data Truth Table: 4 bits (Channels 5 and 6 driver settings register)
D5 (OE3)
D4 (RES3)
D3 (HOLD3)
D2 (F/R3)
0
Clockwise (forward)
Operating mode
1
Counterclockwise (reverse)
0
Step/hold clear
1
Step/hold
0
Counter reset (Drive goes to the initial position)
1
Counter reset release
0
Outputs: high impedance
1
Output operating state
Note : Don’t Care
Initial Drive Position
Drive mode
2W1-2 phase drive
Initial mode
5ch
6ch
100%
0%
Reference Voltage Setting Serial Data: 2 bits (Channels 5 and 6 driver settings register)
D7 (VSEN2)
D6 (VSEN1)
0
0
Current control reference voltage (when 100%)
0.2 V
0
1
0.134 V
1
0
0.1 V
1
1
0.066 V
Set Current Calculation
IOUT (reference voltage u set current ratio)/(sense resistor (SEN) value)
Since the reference voltage can be set to either 0.2, 0.134, 0.1, or 0.066 V with the serial data, the output current
can be set with either the reference voltage or the value of the sense resistor SEN.
No.7944-20/24
LV8041FN
Constant Current Forward/Reverse Motor Driver (Channel 7)
Truth Table
Inputs
ST
Outputs
IN71
IN72
OUT7A
OUT7B
Mode
Charge pump circuit
Stopped
Low
OFF
OFF
Standby mode
High
Low
Low
OFF
OFF
Outputs off
High
Low
High
High
Low
Forward
High
High
Low
Low
High
Reverse
High
High
High
Low
Low
Brake
Operating
Note : Don’t care
VM7
OUT7AA
Logic circuits
IN71
OUT7BA
IN72
VREF7
Reference
voltage
LIM7
Fast
charge
circuit
SEN7
Fast
discharge
circuit
FC7
IN71
IN72
U1
OFF
L1
OFF
ON
OFF
ON
U2
L2
OFF
High
impedance
ON
ON
ON
Forward
High
impedance
Reverse
Brake
Set Current Calculation
IOUT = LIM7 voltage/SEN7 resistor
Since the LIM7 voltage is an external input, the reference voltage can be set arbitrarily.
The reference voltage can be set to 0.2 V by using the VREF7 pin and shorting it to the LIM7 pin. If a voltage
created by resistor dividing the VREF7 voltage is input to LIM7, the reference voltage can be made variable (to
voltages under 0.2 V).
No.7944-21/24
LV8041FN
Recommended Application Circuit
The values shown near the various pins are recommended values. See the Allowable Operating Ranges table earlier in
this document for numerical values for the input conditions.
Channels 1 and 2: Microstep drive
Channels 3 and 4: Microstep drive
Channels 5 and 6: Described separately
Channel 7: Constant current drive
M
0.1 PF
0.1 PF
51
50
49
48
47
46
45
44
43
42
41
40
VREF7
LIM7
FC7
VGH
CPH2
CPH1
VGL
CPL2
0.1 PF
IN71
0.1 PF
IN72
10 k:
5V
0V
MO12
1 OUT1A
1:
5V
0V
CLK12
52
PGND12
5V
0V
0.01 PF
10 k:
(3)
CPL1 39
5V
2 SEN1
VM7 38
3 OUT1B
OUT7B 37
5V
1:
4 VM12
10 PF
1:
5 OUT2A
OUT7A 35
6 SEN2
PGND7 34
LV8041FN
7 OUT2B
OUT6B 33
SEN6 32
8 OUT3A
1:
M
10 PF
SEN7 36
9 SEN3
OUT6A 31
5V
10 OUT3B
VM56 30
5V
11 VM34
OUT5B 29
12 OUT4A
MO34
ST
GND
DATA
STB
SCLK
VCC
R
PWM5/
CLK56
PWM6/
MO56
14
15
16
17
18
19
20
21
22
23
24
25
26
5V
0V
Serial data input
(1)
5V
5V
0V
0.1 PF
13 SEN4
20 k:
CLK34
(2)
SEN5 28
OUT5A
OUT4B
1:
PGND34
10 PF
10 PF
27
The circuit diagram for
the section enclosed in
the dotted line is
provided separately.
Note 1: Use a single point ground for the ground lines if at all possible.
2: Here, a 1 : resistor is attached for each of the SEN pin resistors. This sets an output of 200 mA when the current ratio is 100%.
3: The LIM7 reference voltage can be provided either as an external voltage or by using VREF7: either voltage dividing VREF7 (0.2 V) or simply
shorting LIM7 to VREF7.
No.7944-22/24
LV8041FN
Channels 5 and 6 Recommended Circuit
The channels 5 and 6 systems can be switched between microstep drive and PWM drive.
Set the mode using the serial data as described earlier in this document.
Application 1 ... Microstep Drive Mode (Fixed 2W1-2 phase drive)
OUT6B 33
SEN6 32
1:
OUT6A 31
VM56 30
OUT5B 29
25
OUT5A
PWM6/
MO56
PWM5/
CLK56
SEN5 28
1:
M
27
26
(4)
5V
0V
Note 4: In microstep drive mode, pin 26 functions as a position detection monitor pin.
Application 2 ... PWM Drive Mode (1)
OUT6B 33
SEN6 32
(5)
OUT6A 31
VM56 30
OUT5B 29
SEN5 28
PWM5/
CLK56
PWM6/
MO56
OUT5A
25
26
5V
0V
27
5V
0V
Note 5: Since the current limiter does not operate in PWM drive mode, the sense resistor is not needed.
No.7944-23/24
LV8041FN
Application (3) PWM Drive Mode (2) (Doubled output capacity)
OUT6B 33
SEN6 32
OUT6A 31
VM56 30
OUT5B 29
SEN5 28
PWM5/
CLK56
PWM6/
MO56
OUT5A
25
26
27
(6)
5V
0V
Note 6: Short the inputs together.
(Also short the outputs together. Do not short the outputs incorrectly: short OUT5A to OUT6A and short OUT5B to OUT6B.)
„ Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
„ SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could give
rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that
could cause damage to other property. When designing equipment, adopt safety measures so that these
kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits
and error prevention circuits for safe design, redundant design, and structural design.
„ In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products
must not be exported without obtaining the export license from the authorities concerned in accordance
with the above law.
„ No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, of
otherwise, without the prior written permission of SANYO Electric Co., Ltd.
„ Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for
the SANYO product that you intend to use.
„ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual property rights or
This catalog provides information as of August, 2004. Specifications and information herein are subject to
change without notice.
No.7944-24/24