Order this document by MC34151/D The MC34151/MC33151 are dual inverting high speed drivers specifically designed for applications that require low current digital circuitry to drive large capacitive loads with high slew rates. These devices feature low input current making them CMOS and LSTTL logic compatible, input hysteresis for fast output switching that is independent of input transition time, and two high current totem pole outputs ideally suited for driving power MOSFETs. Also included is an undervoltage lockout with hysteresis to prevent erratic system operation at low supply voltages. Typical applications include switching power supplies, dc to dc converters, capacitor charge pump voltage doublers/inverters, and motor controllers. These devices are available in dual–in–line and surface mount packages. • Two Independent Channels with 1.5 A Totem Pole Output P SUFFIX PLASTIC PACKAGE CASE 626 8 1 CMOS/LSTTL Compatible Inputs with Hysteresis Undervoltage Lockout with Hysteresis Low Standby Current Efficient High Frequency Operation D SUFFIX PLASTIC PACKAGE CASE 751 (SO–8) 8 Enhanced System Performance with Common Switching Regulator Control ICs Pin Out Equivalent to DS0026 and MMH0026 1 PIN CONNECTIONS Representative Block Diagram VCC + + + N.C. 1 8 N.C. Logic Input A 2 7 Drive Output A Gnd 3 6 VCC Logic Input B 4 5 Drive Output B 6 – + 5.7V (Top View) + Drive Output A Logic Input A 2 100k • SEMICONDUCTOR TECHNICAL DATA Output Rise and Fall Times of 15 ns with 1000 pF Load 7 + ORDERING INFORMATION + Drive Output B Logic Input B 100k • • • • • • HIGH SPEED DUAL MOSFET DRIVERS 4 5 Device MC34151D MC34151P MC33151D Gnd 3 MC33151P Operating Temperature Range TA = 0° to +70°C TA = – 40° to +85°C Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Package SO–8 Plastic DIP SO–8 Plastic DIP Rev 0 1 MC34151 MC33151 MAXIMUM RATINGS Symbol Value Unit Power Supply Voltage Rating VCC 20 V Logic Inputs (Note 1) Vin –0.3 to VCC V IO IO(clamp) 1.5 1.0 PD RθJA 0.56 180 W °C/W PD RθJA 1.0 100 W °C/W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature MC34151 MC33151 TA Drive Outputs (Note 2) Totem Pole Sink or Source Current Diode Clamp Current (Drive Output to VCC) Power Dissipation and Thermal Characteristics D Suffix SO–8 Package Case 751 Maximum Power Dissipation @ TA = 50°C Thermal Resistance, Junction–to–Air P Suffix 8–Pin Package Case 626 Maximum Power Dissipation @ TA = 50°C Thermal Resistance, Junction–to–Air A °C 0 to +70 –40 to +85 Storage Temperature Range Tstg –65 to +150 °C ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA is the only operating ambient temperature range that applies [Note 3], unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Threshold Voltage – High State Logic 1 Input Threshold Voltage – Low State Logic 0 VIH VIL 2.6 – 1.75 1.58 – 0.8 V Input Current – High State (VIH = 2.6 V) Input Current – Low State (VIL = 0.8 V) IIH IIL – – 200 20 500 100 µA VOL – – – 10.5 10.4 9.5 0.8 1.1 1.7 11.2 11.1 10.9 1.2 1.5 2.5 – – – V RPD – 100 – kΩ tPLH(in/out) tPHL(in/out) – – 35 36 100 100 Drive Output Rise Time (10% to 90%) CL = 1.0 nF Drive Output Rise Time (10% to 90%) CL = 2.5 nF tr – – 14 31 30 – ns Drive Output Fall Time (90% to 10%) CL = 1.0 nF Drive Output Fall Time (90% to 10%) CL = 2.5 nF tf – – 16 32 30 – ns – – 6.0 10.5 10 15 6.5 – 18 LOGIC INPUTS DRIVE OUTPUT Output Voltage – Low State (ISink = 10 mA) Output Voltage – Low State (ISink = 50 mA) Output Voltage – Low State (ISink = 400 mA) Output Voltage – High State (ISource = 10 mA) Output Voltage – High State (ISource = 50 mA) Output Voltage – High State (ISource = 400 mA) Output Pull–Down Resistor VOH SWITCHING CHARACTERISTICS (TA = 25°C) Propagation Delay (10% Input to 10% Output, CL = 1.0 nF) Logic Input to Drive Output Rise Logic Input to Drive Output Fall ns TOTAL DEVICE Power Supply Current Standby (Logic Inputs Grounded) Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz) ICC Operating Voltage VCC mA V NOTES: 1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less. 2. Maximum package power dissipation limits must be observed. 3. Tlow = 0°C for MC34151 Thigh = +70°C for MC34151 –40°C for MC33151 +85°C for MC33151 2 MOTOROLA ANALOG IC DEVICE DATA MC34151 MC33151 Figure 1. Switching Characteristics Test Circuit Figure 2. Switching Waveform Definitions 12V 4.7 0.1 + 6 5.0 V Logic Input tr, tf ≤ 10 ns 0V + + + + – + 5.7V Drive Output 10% tPLH tPHL 7 100k 2 Logic Input 90% 50 90% 10% Drive Output CL tr tf + + 5 100k 4 3 Figure 3. Logic Input Current versus Input Voltage Figure 4. Logic Input Threshold Voltage versus Temperature V th , INPUT THRESHOLD VOLTAGE (V) 2.2 VCC = 12 V TA = 25°C 2.0 1.6 1.2 0.8 0.4 t PLH(IN/OUT) , DRIVE OUTPUT PROPAGATION DELAY (ns) 0 0 2.0 4.0 6.0 8.0 Vin, INPUT VOLTAGE (V) 10 Figure 5. Drive Output Low–to–High Propagation Delay versus Logic Overdrive Voltage 200 160 VCC = 12 V CL = 1.0 nF TA = 25°C Overdrive Voltage is with Respect to the Logic Input Lower Threshold 120 80 40 Vth(lower) 0 –1.6 –1.2 –0.8 –0.4 0 Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V) MOTOROLA ANALOG IC DEVICE DATA VCC = 12 V 2.0 1.8 Upper Threshold Low State Output 1.6 1.4 Lower Threshold High State Output 1.2 1.0 –55 12 t PHL(IN/OUT) , DRIVE OUTPUT PROPAGATION DELAY (ns) I in , INPUT CURRENT (mA) 2.4 –25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 6. Drive Output High–to–Low Propagation Delay versus Logic Input Overdrive Voltage 200 Overdrive Voltage is with Respect to the Logic Input Lower Threshold 160 VCC = 12 V CL = 1.0 nF TA = 25°C 120 80 40 0 Vth(upper) 0 1.0 2.0 3.0 4.0 Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V) 3 MC34151 MC33151 Figure 8. Drive Output Clamp Voltage versus Clamp Current 90% Logic Input V clamp , OUTPUT CLAMP VOLTAGE (V) Figure 7. Propagation Delay VCC = 12 V Vin = 5 V to 0 V CL = 1.0 nF TA = 25°C Drive Output 10% 3.0 1.0 VCC 0 Gnd Figure 9. Drive Output Saturation Voltage versus Load Current Figure 10. Drive Output Saturation Voltage versus Temperature VCC –2.0 Source Saturation VCC = 12 V (Load to Ground) 80 µs Pulsed Load 120 Hz Rate TA = 25°C –3.0 3.0 2.0 1.0 Sink Saturation (Load to VCC) 0.2 Gnd 0.4 0.6 0.8 1.0 IO, OUTPUT LOAD CURRENT (A) 1.2 1.4 V sat , OUTPUT SATURATION VOLTAGE(V) V sat , OUTPUT SATURATION VOLTAGE(V) 0.4 0.6 0.8 1.0 IO, OUTPUT LOAD CURRENT (A) –1.0 0 –0.5 –0.7 –0.9 –1.1 1.9 1.7 90% 0 0.2 Source Saturation (Load to Ground) VCC Isource = 10 mA 10% 10 ns/DIV 1.4 VCC = 12 V Isource = 400 mA Isink = 400 mA 100 125 Figure 12. Drive Output Fall Time VCC = 12 V Vin = 5 V to 0 V CL = 1.0 nF TA = 25°C 90% VCC = 12 V Vin = 5 V to 0 V CL = 1.0 nF TA = 25°C 1.2 1.5 1.0 Isink = 10 mA 0.8 Gnd Sink Saturation 0.6 (Load to VCC) 0 –55 –25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Figure 11. Drive Output Rise Time 4 Low State Clamp (Drive Output Driven Below Ground) 0 50 ns/DIV 0 0 VCC = 12 V 80 µs Pulsed Load 120 Hz Rate TA = 25°C 2.0 –1.0 0 High State Clamp (Drive Output Driven Above VCC) 10% 10 ns/DIV MOTOROLA ANALOG IC DEVICE DATA MC34151 MC33151 Figure 13. Drive Output Rise and Fall Time versus Load Capacitance Figure 14. Supply Current versus Drive Output Load Capacitance 80 VCC = 12 V VIN = 0 V to 5.0 V TA = 25°C 60 ICC, SUPPLY CURRENT (mA) t r –t f , OUTPUT RISE-FALL TIME(ns) 80 40 tf 20 tr 0 0.1 1.0 CL, OUTPUT LOAD CAPACITANCE (nF) 60 f = 500 kHz 20 Figure 15. Supply Current versus Input Frequency 1.0 CL, OUTPUT LOAD CAPACITANCE (nF) 10 Figure 16. Supply Current versus Supply Voltage TA = 25°C Both Logic Inputs Driven 0 V to 5.0 V, 50% Duty Cycle Both Drive Outputs Loaded TA = 25°C 1 – VCC = 18 V, CL = 2.5 nF 2 – VCC = 12 V, CL = 2.5 nF 3 – VCC = 18 V, CL = 1.0 nF 4 – VCC = 12 V, CL = 1.0 nF 1 2 3 4 20 0 f = 50 kHz 8.0 ICC , SUPPLY CURRENT (mA) ICC , SUPPLY CURRENT (mA) 40 f = 200 kHz 40 0 0.1 10 80 60 VCC = 12 V Both Logic Inputs Driven 0 V to 5.0 V 50% Duty Cycle Both Drive Outputs Loaded TA = 25°C 10 k 100 1.0 M Logic Inputs at VCC Low State Drive Outputs 6.0 4.0 Logic Inputs Grounded High State Drive Outputs 2.0 0 0 4.0 8.0 12 16 VCC, SUPPLY VOLTAGE (V) f, INPUT FREQUENCY (Hz) APPLICATIONS INFORMATION Description The MC34151 is a dual inverting high speed driver specifically designed to interface low current digital circuitry with power MOSFETs. This device is constructed with Schottky clamped Bipolar Analog technology which offers a high degree of performance and ruggedness in hostile industrial environments. Input Stage The Logic Inputs have 170 mV of hysteresis with the input threshold centered at 1.67 V. The input thresholds are insensitive to VCC making this device directly compatible with CMOS and LSTTL logic families over its entire operating voltage range. Input hysteresis provides fast output switching that is independent of the input signal transition time, preventing output oscillations as the input thresholds are crossed. The inputs are designed to accept a signal amplitude ranging from ground to VCC. This allows the output of one channel to directly drive the input of a second channel for master–slave operation. Each input has a 30 kΩ pull–down resistor so that an unconnected open input will cause the associated Drive Output to be in a known high state. Output Stage Each totem pole Drive Output is capable of sourcing and sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at MOTOROLA ANALOG IC DEVICE DATA 1.0 A. The low ‘on’ resistance allows high output currents to be attained at a lower VCC than with comparative CMOS drivers. Each output has a 100 kΩ pull–down resistor to keep the MOSFET gate low when VCC is less than 1.4 V. No over current or thermal protection has been designed into the device, so output shorting to VCC or ground must be avoided. Parasitic inductance in series with the load will cause the driver outputs to ring above VCC during the turn–on transition, and below ground during the turn–off transition. With CMOS drivers, this mode of operation can cause a destructive output latch–up condition. The MC34151 is immune to output latch–up. The Drive Outputs contain an internal diode to VCC for clamping positive voltage transients. When operating with VCC at 18 V, proper power supply bypassing must be observed to prevent the output ringing from exceeding the maximum 20 V device rating. Negative output transients are clamped by the internal NPN pull–up transistor. Since full supply voltage is applied across the NPN pull–up during the negative output transient, power dissipation at high frequencies can become excessive. Figures 19, 20, and 21 show a method of using external Schottky diode clamps to reduce driver power dissipation. Undervoltage Lockout An undervoltage lockout with hysteresis prevents erratic system operation at low supply voltages. The UVLO forces the Drive Outputs into a low state as VCC rises from 1.4 V to 5 MC34151 MC33151 Power Dissipation Circuit performance and long term reliability are enhanced with reduced die temperature. Die temperature increase is directly related to the power that the integrated circuit must dissipate and the total thermal resistance from the junction to ambient. The formula for calculating the junction temperature with the package in free air is: TJ = TA + PD (RθJA) where: TJ = Junction Temperature TA = Ambient Temperature PD = Power Dissipation RθJA = Thermal Resistance Junction to Ambient There are three basic components that make up total power to be dissipated when driving a capacitive load with respect to ground. They are: where: PD = PQ = PC = PT = PQ + PC + PT Quiescent Power Dissipation Capacitive Load Power Dissipation Transition Power Dissipation The quiescent power supply current depends on the supply voltage and duty cycle as shown in Figure 16. The device’s quiescent power dissipation is: PQ = VCC where: ICCL (1–D) + ICCH (D) ICCL = Supply Current with Low State Drive Outputs ICCH = Supply Current with High State Drive Outputs D = Output Duty Cycle The capacitive load power dissipation is directly related to the load capacitance value, frequency, and Drive Output voltage swing. The capacitive load power dissipation per driver is: where: PC = VOH = VOL = CL = f= VCC (VOH – VOL) CL f High State Drive Output Voltage Low State Drive Output Voltage Load Capacitance frequency When driving a MOSFET, the calculation of capacitive load power PC is somewhat complicated by the changing gate to source capacitance CGS as the device switches. To aid in this calculation, power MOSFET manufacturers provide gate charge information on their data sheets. Figure 17 shows a curve of gate voltage versus gate charge for the Motorola MTM15N50. Note that there are three distinct slopes to the curve representing different input capacitance values. To 6 completely switch the MOSFET ‘on’, the gate must be brought to 10 V with respect to the source. The graph shows that a gate charge Qg of 110 nC is required when operating the MOSFET with a drain to source voltage VDS of 400 V. Figure 17. Gate–To–Source Voltage versus Gate Charge V GS , GATE–TO–SOURCE VOLTAGE (V) the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V, yielding about 500 mV of hysteresis. 16 MTM15N50 ID = 15 A TA = 25°C 12 VDS = 400 V VDS = 100 V 8.0 8.9 nF 4.0 2.0 nF 0 0 CGS = 40 80 Qg, GATE CHARGE (nC) 120 ∆ Qg ∆ VGS 160 The capacitive load power dissipation is directly related to the required gate charge, and operating frequency. The capacitive load power dissipation per driver is: PC(MOSFET) = VC Qg f The flat region from 10 nC to 55 nC is caused by the drain–to–gate Miller capacitance, occuring while the MOSFET is in the linear region dissipating substantial amounts of power. The high output current capability of the MC34151 is able to quickly deliver the required gate charge for fast power efficient MOSFET switching. By operating the MC34151 at a higher VCC, additional charge can be provided to bring the gate above 10 V. This will reduce the ‘on’ resistance of the MOSFET at the expense of higher driver dissipation at a given operating frequency. The transition power dissipation is due to extremely short simultaneous conduction of internal circuit nodes when the Drive Outputs change state. The transition power dissipation per driver is approximately: PT ≈ VCC (1.08 VCC CL f – 8 × 10–4) PT must be greater than zero. Switching time characterization of the MC34151 is performed with fixed capacitive loads. Figure 13 shows that for small capacitance loads, the switching speed is limited by transistor turn–on/off time and the slew rate of the internal nodes. For large capacitance loads, the switching speed is limited by the maximum output current capability of the integrated circuit. MOTOROLA ANALOG IC DEVICE DATA MC34151 MC33151 LAYOUT CONSIDERATIONS High frequency printed circuit layout techniques are imperative to prevent excessive output ringing and overshoot. Do not attempt to construct the driver circuit on wire–wrap or plug–in prototype boards. When driving large capacitive loads, the printed circuit board must contain a low inductance ground plane to minimize the voltage spikes induced by the high ground ripple currents. All high current loops should be kept as short as possible using heavy copper runs to provide a low impedance high frequency path. For Figure 18. Enhanced System Performance with Common Switching Regulators optimum drive performance, it is recommended that the initial circuit design contains dual power supply bypass capacitors connected with short leads as close to the VCC pin and ground as the layout will permit. Suggested capacitors are a low inductance 0.1 µF ceramic in parallel with a 4.7 µF tantalum. Additional bypass capacitors may be required depending upon Drive Output loading and circuit layout. Proper printed circuit board layout is extremely critical and cannot be over emphasized. Figure 19. MOSFET Parasitic Oscillations VCC 47 Vin 0.1 6 + + ++ – 5.7V Vin + + Rg 7 + D1 1N5819 + 5 4 100k TL494 or TL594 100k 100k 2 3 The MC34151 greatly enhances the drive capabilities of common switching regulators and CMOS/TTL logic devices. Series gate resistor Rg may be needed to damp high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate–source circuit. Rg will decrease the MOSFET switching speed. Schottky diode D1 can reduce the driver’s power dissipation due to excessive ringing, by preventing the output pin from being driven below ground. Figure 20. Direct Transformer Drive Figure 21. Isolated MOSFET Drive + + 7 Isolation Boundary 100k + 100k 4X 1N5819 + + 1N 5819 100k 5 3 3 Output Schottky diodes are recommended when driving inductive loads at high frequencies. The diodes reduce the driver’s power dissipation by preventing the output pins from being driven above VCC and below ground. MOTOROLA ANALOG IC DEVICE DATA 7 MC34151 MC33151 Figure 22. Controlled MOSFET Drive Figure 23. Bipolar Transistor Drive IB Vin Vin + 0 + Base Charge Removal – Rg(on) C1 Rg(off) 100k 100k + The totem–pole outputs can furnish negative base current for enhanced transistor turn–off, with the addition of capacitor C1. In noise sensitive applications, both conducted and radiated EMI can be reduced significantly by controlling the MOSFET’s turn–on and turn–off times. Figure 24. Dual Charge Pump Converter VCC = 15 V 4.7 0.1 + 6 + + + – + 5.7V + 6.8 10 7 + 1N5819 100k 2 47 + + VO ≈ 2.0 VCC + + 5 6.8 10 + 1N5819 100k 4 330pF 47 – VO ≈ – VCC + 3 10k The capacitor’s equivalent series resistance limits the Drive Output Current to 1.5 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. 8 Output Load Regulation IO (mA) +VO (V) –VO (V) 0 1.0 10 20 30 50 27.7 27.4 26.4 25.5 24.6 22.6 –13.3 –12.9 –11.9 –11.2 –10.5 –9.4 MOTOROLA ANALOG IC DEVICE DATA MC34151 MC33151 OUTLINE DIMENSIONS 8 P SUFFIX PLASTIC PACKAGE CASE 626–05 ISSUE K 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. –B– 1 4 F –A– NOTE 2 DIM A B C D F G H J K L M N L C J –T– N SEATING PLANE D M K MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC ––– 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC ––– 10_ 0.030 0.040 G H 0.13 (0.005) M T A M M D SUFFIX PLASTIC PACKAGE CASE 751–05 (SO–8) ISSUE N –A– 8 B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 5 –B– 1 4X P 0.25 (0.010) 4 M B M G R C –T– 8X K D 0.25 (0.010) M T B SEATING PLANE S A M_ S MOTOROLA ANALOG IC DEVICE DATA X 45 _ F J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.18 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.189 0.196 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.007 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 9 MC34151 MC33151 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 10 ◊ *MC34151/D* MOTOROLA ANALOG IC DEVICE DATA MC34151/D