SEMICONDUCTOR TECHNICAL DATA The MC10E1651 is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using Motorola’s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. DUAL ECL OUTPUT COMPARATOR WITH LATCH The latch enable (LENa and LENb) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met. • • • • • • • Typ. 3.0 dB Bandwidth > 1.0 GHz FN SUFFIX PLASTIC PACKAGE CASE 775-02 Typ. V to Q Propagation Delay of 775 ps Typ. Output Rise/Fall of 350 ps Common Mode Range –2.0 V to +3.0 V Individual Latch Enables Differential Outputs 28mV Input Hysteresis L SUFFIX CERAMIC PACKAGE CASE 620-10 LOGIC DIAGRAM V1a FUNCTION TABLE Qa V2a LENa Qa LEN V1, V2 Function H H L V1 > V2 V1 < V2 X H L Latched V1b Qb V2b LENb Qb VEE = –5.2 V VCC = +5.0 V 12/93 Motorola, Inc. 1996 2–1 REV 1 MC10E1651 Pinout: 20-Lead PLCC (Top View) Qb LENb NC 18 17 16 V1b V2b 15 14 Pinout: 16-Pin Ceramic DIP (Top View) Qb 19 13 VCC GND 20 12 NC NC 1 11 NC GND 2 10 VEE Qa 3 9 VCC 4 5 6 Qa LENa NC 7 8 V2a V1a GND Qb Qb LENb V1b V2b VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Qa LENa V2a GND Qa V1a VCC NC VEE ABSOLUTE MAXIMUM RATINGS (Beyond which device life may be impaired) Symbol VSUP VPP Characteristic Min Typ Max Total Supply Voltage |VEE| + |VCC| 12.0 Differential Input Voltage |V1 – V2| 3.7 Unit V V DC CHARACTERISTICS (VEE = –5.2 V ±5%; VCC = +5.0 V ±5%) 0°C Symbol Characteristic Min Typ 25°C Max Min Max Min Max Unit VOH Output HIGH Voltage –1020 –840 –980 –810 –920 –735 mV VOL Output Low Voltage –1950 –1630 –1950 –1630 –1950 –1600 mV II IIH Input Current (V1, V2) Input HIGH Current (LEN) 65 150 65 150 65 150 µA ICC IEE Positive Supply Current Negative Supply Current 50 –55 50 –55 50 –55 mA VCMR Common Mode Range 3.0 V Hys Hysteresis Vskew Hysteresis Skew Cin Input Capacitance DIP PLCC –2.0 3.0 Typ 85°C –2.0 3.0 Typ –2.0 27 27 30 mV –1.0 –1.0 0 mV Condition 1 pF 3 2 3 2 3 2 1. Hysteresis skew (Vskew) is provided to indicate the offset of the hysteresis window. For example, at 25°C the nominal hysteresis value is 27mV and the Vskew value indicates that the hysteresis was skewed from the reference level by 1mV in the negative direction. Hence the hysteresis window ranged from 14mV below the reference level to 13mV above the reference level. All hysteresis measurements were determined using a reference voltage of 0mV. MOTOROLA 2–2 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E1651 AC CHARACTERISTICS (VEE = –5.2 V ±5%; VCC = +5.0 V ±5%) 0°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max 900 750 625 400 775 575 925 750 700 500 850 650 1050 850 tPLH tPHL Propagation Delay to Output V to Q LEN to Q 600 400 750 575 ts Setup Time V 450 300 450 300 550 350 Enable Hold Time V –50 –250 –50 –250 –100 –250 Minimum Pulse Width LEN 400 th tpw tskew Within Device Skew TDE Delay Dispersion (ECL Levels) TDL tr tf Condition ps 1 ps ps ps 400 15 400 15 15 ps 2 ps 100 60 Delay Dispersion (TTL Levels) Rise/Fall Times 20-80% Unit 3, 4 3, 5 ps 350 100 6, 7 5, 6 ps 225 325 475 225 325 475 250 375 500 1. The propagation delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. For propagation delay measurements the threshold level (VTHR) is centered about an 850mV input logic swing with a slew rate of 0.75 V/NS. There is an insignificant change in the propagation delay over the input common mode range. 2. tskew is the propagation delay skew between comparator A and comparator B for a particular part under identical input conditions. 3. Refer to figure 4 and note that the input is at 850mV ECL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 4. The slew rate is 0.25 V/NS for input rising edges. 5. The slew rate is 0.75 V/NS for input rising edges. 6. Refer to Figure 5 and note that the input is at 2.5 V TTL levels with the input threshold range between the 20% and 80% points. The delay is measured from the crosspoint of the input signal and the threshold value to the crosspoint of the Q and Q output signals. 7. The slew rate is 0.3 V/NS for input rising edges. APPLICATIONS INFORMATION internally generated reference level, hence is nominally at the ECL VBB level. Finally, VOD is the input voltage overdrive and represents the voltage level beyond the threshold level (VTHR) to which the input is driven. As an example, if the threshold level is set on one of the comparator inputs as 80mV and the input signal swing on the complementary input is from zero to 100mV, the positive going overdrive would be 20mV and the negative going overdrive would be 80mV. The result of differing overdrive levels is that the devices have shorter propagation delays with greater overdrive because the threshold level is crossed sooner than the case of lower overdrive levels. Typically, semiconductor manufactures refer to the threshold voltage as the input offset voltage (VOS) since the threshold voltage is the sum of the externally supplied reference voltage and inherent device offset voltage. The timing diagram (Figure 3) is presented to illustrate the MC10E1651’s compare and latch features. When the signal on the LEN pin is at a logic high level, the device is operating in the “compare mode,” and the signal on the input arrives at the output after a nominal propagation delay (tPHL, tPLH). The input signal must be asserted for a time, ts, prior to the negative going transition on LEN and held for a time, th, after the LEN transition. After time th, the latch is operating in the “latch mode,” thus transitions on the input do not appear at the output. The device continues to operate in the “latch mode” until the latch is asserted once again. Moreover, the LEN pulse must meet the minimum pulse width (tpw) requirement to effect the correct input-output relationship. Note that the LEN waveform in Figure 3 shows the LEN signal swinging around a reference labeled VBBINT; this waveform emphasizes the requirement that LEN follow typical ECL 10KH logic levels because VBBINT is the ECLinPS and ECLinPS Lite DL140 — Rev 4 2–3 MOTOROLA MC10E1651 VBBINT LEN tpw ts V VIN th VOD VTHR tPLH(LEN) tPHL Q Q Figure 3. Input/Output Timing Diagram DELAY DISPERSION where TNOM is the nominal propagation delay. TNOM accounts for nonuniformity introduced by temperature and voltage variability, whereas the delay dispersion parameter takes into consideration input slew rate and input voltage overdrive variability. Thus a modified propagation delay can be approximated to account for the effects of input conditions that differ from those under which the parts where tested. For example, an application may specify an ECL input with a slew rate of 0.25 V/NS, an overdrive of 17mV and a temperature of 25°C, the delay dispersion parameter would be 100 ps. The modified propagation delay would be Under a constant set of input conditions comparators have a specified nominal propagation delay. However, since propagation delay is a function of input slew rate and input voltage overdrive the delay dispersion parameters, TDE and TDT, are provided to allow the user to adjust for these variables (where TDE and TDT apply to inputs with standard ECL and TTL levels, respectively). Figure 4 and Figure 5 define a range of input conditions which incorporate varying input slew rates and input voltage overdrive. For input parameters that adhere to these constraints the propagation delay can be described as: TNOM ± TDE (or TDT) 775ps ± 100ps –0.9 V – 1.07 V 2.5 V 2.0 V INPUT THRESHOLD RANGE SLEW RATE = 0.25 V/NS INPUT THRESHOLD RANGE SLEW RATE = 0.75 V/NS – 1.58 V – 1.75 V SLEW RATE = 0.30 V/NS SLEW RATE = 0.75 V/NS 0.5 V 0V Figure 4. ECL Dispersion Test Input Conditions MOTOROLA Figure 5. TTL Dispersion Test Input Conditions 2–4 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E1651 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C B Y BRK -N- 0.007 (0.180) M T L –M D -L- U N S 0.007 (0.180) M T L –M S S N S -MZ W D 1 20 V G1 X 0.010 (0.250) S T L –M N S S VIEW D-D A 0.007 (0.180) M T L –M S N S R 0.007 (0.180) M T L –M S N S Z C -T- SEATING PLANE F VIEW S G1 0.010 (0.250) S T L –M S 0.007 (0.180) M T L –M S N S VIEW S S N S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). ECLinPS and ECLinPS Lite DL140 — Rev 4 N K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L –M H 2–5 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.310 0.330 0.040 — MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 7.88 8.38 1.02 — MOTOROLA MC10E1651 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V -A16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -BL C -TN SEATING PLANE K E M F G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) MOTOROLA J M T A S 2–6 M T B S DIM A B C D E F G J K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 — 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15° 0° 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 — 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15° 0° 1.01 0.51 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E1651 Motorola reserves the right to make changes without further notice to any products herein. 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