APL3216 Li+ Charger Protection IC Features General Description • Provide Input Over-voltage Protection • Provide Input Over-current Protection The APL3216 provides complete Li+ charger protection against Input over-voltage, input over-current and over- • Provide Over Temperature Protection • Provide Reverse Current Blocking • High Immunity of False Triggering • High Accuracy Protection Threshold • Low On Resistance 0.75Ω Typ. • Compliance to IEC61000-4-2 (Level 4) temperature. When any of the monitored parameters is over the threshold, the IC turns off the charging current. All protections also have deglitch time against false triggering due to voltage spikes or current transients. When ACIN voltage exceeds OVP threshold, the device will turn off charging current. The charging current is controlled by the GATDRV pin. When sourcing a current from the GATDRV pin, the OUT pin delivers the charging current which is 200-fold magnified in amplitude based on GATDRV’s current. +8kV (Contact Discharge) Other features include accurate VVCDT/VACIN Voltage divider, reverse current blocking from OUT to ACIN and OTP +15kV (Air Discharge) • Available in TDFN2x2-8, SOT-23-6 Packages • Lead Free and Green Devices Available protection. The L3216 provides complete Li+ charger protections, that can save the external components for the charger of cell phone’s PMIC. The above features and small package make the APL3216 an ideal part for (RoHS Compliant) cell phones applications. Applications Pin Configuration • Cell Phones ACIN 1 ACIN 2 GND 3 VCDT 4 Simplified Application Circuit 5V Adapter ACIN CHR_LDO CHR_LDO APL3216 TDFN2x2-8 (Top View) PMIC GATDRV VCDT OUT GATDRV VCDT ISENS OUT 1 6 ACIN 5 GND 4 VCDT CHR_LDO 2 GATDRV 3 GND Li+ Battery 8 OUT 7 OUT 6 CHR_LDO 5 GATDRV VBAT SOT-23-6 (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 1 www.anpec.com.tw APL3216 Ordering and Marking Information Package Code QB : TDFN2x2-8 C : SOT-23-6 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL3216 Assembly Material Handling Code Temperature Range Package Code APL3216 QB: L16 X X - Date Code APL3216 C: L16A X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VACIN VCHR_LDO Parameter Rating Unit ACIN Input Voltage (ACIN to GND) -0.3 ~ 30 V CHR_LDO to GND Voltage -0.3 ~ 7 V -0.3 ~ VCHR_LDO V -0.3 ~ 7 V V VGATDRV GATDRV to GND Voltage VVCDT VCDT to GND Voltage VOUT OUT to GND Voltage -0.3 ~ 7 IOUT OUT Output Current Internally Limited TJ Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds A 150 o -65 ~ 150 o 260 o C C C Note 1:Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions”is not implied. Exposure to absolute maximum rating conditions for extended periods may affect vice reliability. Thermal Characteristic Symbol Parameter Typical Value Unit θJA TDFN2x2-8 Junction-to-Ambient Resistance in free air (Note 2) 80 o θJA SOT-23-6 Junction-to-Ambient Resistance in free air (Note 2) 250 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 2 www.anpec.com.tw APL3216 Recommended Operating Conditions (Note 3) Symbol Parameter VACIN ACIN Input Voltage IOUT Output Current Range Unit 4.5 ~ 9 V 0.7 A TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o COUT Output Capacitor C C µF 0.1~1 Note 3: Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VACIN=5V, TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter Test Conditions APL3216 Min Typ Max Unit ACIN INPUT CURRENT and POWER-ON-RESET (POR) IACIN ACIN Supply Current IOUT=0A, ICHR=0A - 250 500 µA VPOR ACIN POR Threshold VACIN rising - 2.6 - V ACIN POR Hysteresis - 250 - mV ACIN Power-On Blanking Time - 8 - ms TB(ACIN) INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance IOUT=0.6A 750 CHR_LDO Discharge Resistance mΩ - 500 - 0.9 1.25 1.6 - 0.75 - Ω PROTECTIONS ICL Over-current Trip Threshold A - Short-circuit Current Limit - Input OVP Threshold 9.5 10 10.5 V - CHR_LDO Output Series Resistance 2.4 3 - kΩ 0.1035 0.1056 0.1078 V/V 100 200 300 A/A - 160 - °C - 40 - °C VCDT INTERNAL DIVIDER Divider Ratio VVCDT /VACIN CHARGE CURRENT CONTROL Current Mirror Gain IOUT=0.6A, IOUT/IGATDRV THERMAL SHUTDOW PROTECTION TOTP Thermal Shutdown Threshold TJ rising Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 3 www.anpec.com.tw APL3216 Pin Description PIN TDFN2x2-8 SOT-23-6 Function NO. NAME 6 ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum) ceramic capacitor. 3 5 GND Ground terminal. 4 4 VCDT Provide an internal voltage divider. This pin divides ACIN voltage into 0.1056 ratio. 5 3 GATDRV Charging current control pin. When sinking a current from this pin, the OUT pin will source out a current whose magnitude is 200x IGATDRV . 6 2 CHR_LDO Output Pin. The pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum) ceramic capacitor. 1 OUT Output Pins. The pin provides supply source current in series with a resistor to battery. - GND Exposed Thermal Pad. Must be electrically connected to the GND pin. NO. 1 2 7 8 Exposed Pad Block Diagram ACIN VCDT CHR_LDO GATDRV GND OUT Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 4 www.anpec.com.tw APL3216 Typical Application Circuit 5V Adapter ACIN CACIN 1µF/25V CHR_LDO CHR_LDO CCHR_LDO 2.2µF/6.3V APL3216 PMIC GATDRV VCDT GATDRV VCDT OUT ISENS 0.2Ω GND Li+ Battery Description Designation CACIN VBAT 1µF, 25V, X5R, 0603 Murata GRM188R61E105K 1µF, 16V, X5R, 0603 Murata GRM188R61C105K CCHR_LDO Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 1µF, 6.3V, X5R, 0603 Murata GRM185R60J225KE26 5 www.anpec.com.tw APL3216 Function Description ACIN Power-On-Reset (POR) Temperature Protection The APL3216 is built-in a power-on-reset circuit to keep the output shut off until internal circuitry is operating When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and allows the device to cool down. When the device’s junc- properly. The POR circuit has hysteresis and a de-glitch feature so that it will typically ignore undershoot transients tion temperature cools by 40 oC, the internal thermal sense circuit will enable the device, resulting in a pulsed on the input. When input voltage exceeds the POR threshold and after 8ms blanking time, the output voltage starts output during continuous thermal protection. Thermal protection is designed to protect the IC in the event of a soft-start to reduce the inrush current. over temperature conditions. For normal operation, the junction temperature cannot exceed TJ=+125oC. ACIN Over-Voltage Protection (OVP) The CHR_LDO output of the IC operates similar to a linear regulator. If the input voltage rises above VOVP, the ESD Tests internal transistor will be turned off within 5µs to protect connected system on OUT pin. When the input voltage The APL3216 VIN input pin fully supports the IEC610004-2. That means the VIN pin has immunity of ±15kV ESD discharge in Air condition, and immunity of ±8kV ESD dis- returns below the input OVP threshold minus the hysteresis, the transistor is turned on again after 1ms charge in Contact condition. recovery time. The input OVP circuit has a 200mV hysteresis and a recovery time of TON(OVP) to provide noise immunity against transient conditions. Charging Current Control The charging current is controlled by the GATDRV pin. When sourcing a current from the GATDRV pin, the OUT pin delivers the charging current which is 200-fold magnified in amplitude based on GATDRV?¦s current. The IOUT current can be calculated by this following equation: IOUT=200*IGATDRV where The IOUT is the current flowing out from OUT pin. The IGATDRV is the current flowing out from GATDRV pin. Current Limit The output current is monitored by the internal Current Limit circuit. When the output current reaches the over current trip threshold, the device limits the output current at current limit threshold. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 6 www.anpec.com.tw APL3216 Package Information TDFN2x2-8 A b E D D2 A1 E2 A3 L Pin 1 Corner e S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 TDFN2x2-8 MILLIMETERS A3 INCHES 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 1.90 2.10 0.075 0.083 0.063 0.083 D2 1.00 1.60 0.039 E 1.90 2.10 0.075 E2 0.60 1.00 0.024 e L 0.50 BSC 0.30 0.039 0.020 BSC 0.012 0.45 0.018 Note : 1. Follow from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 7 www.anpec.com.tw APL3216 Package Information SOT-23-6 -T- D SEATING PLANE < 4 mils e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-6 MILLIMETERS MIN. INCHES MAX. A MAX. MIN. 0.057 1.45 A1 0.00 0.15 0.000 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC e1 1.90 BSC 0.037 BSC 0.075 BSC L 0.30 0.60 0.012 0 0° 8° 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AB. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 8 www.anpec.com.tw APL3216 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 178.0 ±2 . 0 0 50 MIN. P0 P1 T D F N 2 x 2 -8 4.0 ±0 . 1 0 T1 C 8.4+2.00 13.0+0.50 -0 . 0 0 -0 . 2 0 4.0 ±0 . 1 0 P2 D0 2.0 ±0 . 0 5 1.5+0.10 -0 . 0 0 d D W E1 F 1.5 MIN. 20.2 MIN. 8.0 ±0 . 2 0 1 . 7 5 ±0 . 1 0 3 . 5 0 ±0 . 0 5 A0 B0 K0 3.35 MIN 3.35 MIN 1 . 3 0 ±0 . 2 0 D1 1.5 MIN. T 0 .6 + 0 . 0 0 -0.4 A H T1 C d D W E1 F 178.0 ±2 . 0 0 50 MIN. 8.4+2.00 -0 . 0 0 13.0+0.50 -0 . 2 0 1.5 MIN. 20.2 MIN. 8.0 ±0 . 3 0 1 . 7 5 ±0 . 1 0 3.5 ±0 .0 5 S O T-2 3 -6 P0 P1 P2 D0 D1 T A0 B0 K0 4.0 ±0 . 1 0 4.0 ±0 . 1 0 2.0 ±0 . 0 5 1.5+0.10 -0 . 0 0 1.0 MIN. 0.6+0.00 -0 . 4 0 3 . 2 0±0 . 2 0 3 . 1 0 ±0 . 2 0 1 . 5 0 ±0 . 2 0 (m m ) Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 SOT-23-6 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 9 www.anpec.com.tw APL3216 Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 10 www.anpec.com.tw APL3216 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 JESD-22, A114; A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 11 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV, VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3216 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2011 12 www.anpec.com.tw