ANPEC APL3526

APL3526/B
Ultra-Low On-Resistance, 6A Load Switch with Soft Start
Features
General Description
•
15mΩ(Typical) On-resistance
•
6A Continuous Current
The APL3526/B is an ultra-low on-resistance, power-distribution switch with external soft start control. It integrates
•
Soft Start Time Programmable by External
a N-channel MOSFET that can deliver 6A continuous load
current each.
Capacitor
•
Wide Input Voltage Range (VIN): 0.8V to 5.5V
•
Supply Voltage Range (VBIAS): 3V to 5.5V
•
Output Discharge when Switch Disabled
•
Reverse Current Blocking when Switch Disabled
•
•
Over-Temperature Protection
Enable Input
•
Lead Free and Green Devices Available (RoHS
The device integrates over-temperature protection. The
over temperature protection function shuts down the Nchannel MOSFET power switch when the junction temperature rises beyond 160oC and will automatically turns
on the power switch when the temperature drops by 40oC.
The device is available in lead free TDFN2x2-8 packages.
Compliant)
Pin Configurations
Applications
•
Notebook
•
AIO PC
APL3526
VIN 1
VIN 2
EN 3
BIAS 4
8
7
6
5
VOUT
VOUT
SS
GND
8
7
6
5
VOUT
VOUT
SS
GND
TDFN2x2-8
(Top View)
APL3526B
VIN 1
VIN 2
ENB 3
BIAS 4
TDFN2x2-8
(Top View)
= Exposed Pad (connected to ground plane
for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
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APL3526/B
Ordering and Marking Information
Enable Function
Blank : Active High B : Active Low
Package Code
QB : TDFN2x2-8
Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code
TR : Tape & Reel
APL3526/B
Assembly Material
Handling Code
TemperatureRange
Package Code
Enable Function
L26
APL3526 QB:
X
26B
APL3526B QB:
X
Assembly Material
G : Halogen and Lead Free Device
X-Date Code
X-Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
VBIAS
VIN
VOUT
VEN, VENB
TJ
TSTG
TSDR
Parameter
BAIS to GND Voltage
Rating
Unit
-0.3 ~ 6
V
VIN to GND Voltage
-0.3 ~ 6
V
VOUT to GND Voltage
-0.3 ~ 6
V
EN or ENB to GND Voltage
-0.3 ~ 6
V
Maximum Junction Temperature
-40 ~ 150
o
Storage Temperature
-65 ~ 150
o
260
o
Maximum Lead Soldering Temperature (10 Seconds)
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Typical Value
Junction-to-Ambient Resistance in Free Air (Note 2)
75
Unit
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN2x2-8 is soldered directly on the PCB.
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APL3526/B
Recommended Operating Conditions
Parameter
Symbol
VBIAS
(Note 3)
Range
Unit
BIAS Input Voltage
3.0 ~ 5.5
V
VIN
VIN Input Voltage
0.8 ~ 5.5
V
IOUT
VOUT Output Current
0~6
A
Input Logic High
1.2 ~ 5.5
V
Input Logic Low
0 ~ 0.4
VEN, VENB
TA
TJ
Ambient Temperature
Junction Temperature
V
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 3 : Refer to the typical application circuit
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN= 0.8V~5V, VBIAS =5V, VEN=High or VENB=Low, and TA= -40~85oC.
Typical values are at TA=25oC.
Symbol
Parameter
APL3526/B
Test Conditions
Unit
Min.
Typ.
Max.
SUPPLY CURRENT
BIAS Supply Current
No load
-
50
90
µA
BIAS Supply Current at
Shutdown
No load, VEN=0V or VENB=5V
-
-
2
µA
No load, VBIAS=5V, VEN=0V or VENB=5V,
VIN=5V
-
0.1
8
µA
No load, VBIAS=5V, VEN=0V or VENB=5V,
VIN=3.3V
-
0.1
3
µA
No load, VBIAS=5V, VEN=0V or VENB=5V,
VIN=1.8V
-
0.1
2
µA
No load, VBIAS=5V, VEN=0V or VENB=5V,
VIN=0.8V
-
0.1
1
µA
VEN=0V or VENB=5V, VIN=0V
-
0.1
16
µA
1.9
2.4
2.9
V
-
0.1
-
V
VBIAS=5V, VIN=0.8~5V, IOUT=200mA,
TJ= 25oC
-
15
20
mΩ
VBIAS=5V, VIN=0.8~5V, IOUT=200mA,
TJ= -40~125oC
-
-
27
mΩ
VBIAS=3.3V, VIN=0.8~3.3V, IOUT=200mA,
TJ= 25oC
-
17
23
mΩ
VBIAS=3.3V, VIN=0.8~3.3V, IOUT=200mA,
TJ= -40~125oC
-
-
31
mΩ
VEN=0V or VENB=5V, VOUT force 1V
-
100
150
Ω
VSS=6V, VEN=0V or VENB=5V, measured at
SS
-
560
-
µA
VIN Off-State Supply Current
Reverse Leakage Current
UNDER-VOLTAGE LOCKOUT (UVLO)
Rising BIAS UVLO Threshold
VBIAS rising
BIAS UVLO Hysteresis
POWER SWITCH
RDS(ON)
Power Switch On Resistance
VOUT Discharge Resistance
SOFT-START CONTROL PIN
SS Discharge Current
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APL3526/B
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN= 0.8V~5V, VBIAS =5V, VEN=High or VENB=Low, and TA= -40~85oC.
Typical values are at TA=25oC.
Symbol
Parameter
APL3526/B
Test Conditions
Min.
Typ.
Unit
Max.
EN OR ENB INPUT PIN
VEN, VENB
Input Logic High
1.2
-
-
V
Input Logic Low
-
-
0.4
V
Input Current
-
-
1
µA
OVERT-TEMPERATURE PROTECTION (OTP)
Over-Temperature Threshold
TJ rising
-
160
-
°C
Over-Temperature Threshold
Hysteresis
TJ falling
-
40
-
°C
Pin Description
PIN
FUNCTION
NO.
NAME
1
VIN
2
VIN
3
Power supply Input of switch. Connect this pin to an external DC supply.
EN
Enable input of switch. Logic high turns on switch. The EN pin cannot be left floating.
ENB
Enable input of switch. Logic low turns on switch. The ENB pin cannot be left floating.
4
BIAS
Bias voltage input pin for internal control circuitry.
5
GND
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
6
SS
7
VOUT
8
VOUT
Exposed Pad
-
Soft start control of switch. A capacitor from this pin to ground sets the VOUT’s rise slew
rate.
Switch output.
Connect this pad to system ground plane for good thermal conductivity.
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APL3526/B
Block Diagram
Bulk
Select
VOUT
VIN
BIAS
UVLO
Charge
Pump
SS
Control
Logic
EN/ENB
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OTP
GND
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APL3526/B
Typical Application Circuit
VBIAS
4
BIAS
C BIAS
0.1µF
VIN
1, 2
VIN
VOUT
CIN
1µF
7, 8
C OUT
0.1µF
CL
150µF
R LOAD
APL3526/B
3
EN/ENB
SS
GND
5
6
CSS
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APL3526/B
Function Description
VIN Under-voltage Lockout (UVLO)
A under-voltage lockout (UVLO) circuit monitors the VBIAS
pins voltage to prevent wrong logic controls. The UVLO
function initiates a soft-start process after the BIAS supply voltages exceed rising UVLO voltage threshold during powering on.
Power Switch
The power switch is an N-channel MOSFET with a ultralow RDS(ON). When IC is in shutdown state (V EN=Low or
VENB=High), the MOSFET prevents a reverse current flowing from the VOUT back to VIN. When IC is in UVLO state,
the internal parasitic diodes connected from VOUT to VIN
will be forward biased.
Soft-start
The APL3526/B Provides an adjustable soft-start circuitry
to control rise rate of the output voltage and limit the current surge during start-up. The soft-start time is set with a
capacitor from the SS pin to the ground.
Enable Control
Pulling the ENB above 1.2V or EN below 0.4V will disable
the device, and pulling ENB pin below 0.4V or EN above
1.2V will enable the device. The EN/ENB pins cannot be
left floating.
Over-Temperature Protection (OTP)
When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junction temperature cools by 40 oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal
protection is designed to protect the IC in the event of
over temperature conditions. For normal operation, the
junction temperature cannot exceed TJ=+125oC.
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APL3526/B
Application Information
Power Sequencing
Soft-Start Capacitor
The soft-start capacitor on SS pin can reduce the inrush
current and overshoot of output voltage. The capacitor is
VBIAS
VIN
charge to VSS with a constant 2.5µA(typ.) current source.
This results in a linear charge of the soft-start capacitor
VEN
and thus the output voltage.
VENB
Thermal Consideration
VOUT
The APL3526/B maximum power dissipation depends
on the differences of the thermal resistance and temVEN
perature between junction and ambient air. The power
dissipation PD across the device is:
VENB
PD = (TJ - TA) / θJA
VOUT
where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
VIN
between junction and ambient air. Assuming the TA=25°C
and maximum TJ=160°C (typical thermal limit threshold),
VBIAS
Figure 1. APL3526/B Power Sequencing Diagram
the maximum power dissipation is calculated as:
The APL3526/B has a built-in reverse current blocking
circuit to prevent a reverse current flowing through the
PD(max)=(160-25)/75
= 1.8(W)
body diode of power switch from the VOUT back VIN pin
For normal operation, do not exceed the maximum operating junction temperature of TJ = 125°C. The calculated
when power switch disabled. The reverse current blocking circuit is not active before VBIAS is ready. When IC is in
power dissipation should be less than:
UVLO state, the internal parasitic diodes of power switch
connected from VOUT to VIN will be forward biased.
PD =(125-25)/75
= 1.33(W)
Otherwise, VOUT should not be higher than VBIAS, and
VBIAS must be higher than the voltage of any other input
PD =(125-85)/75
pin, the reason is that the internal parasitic diodes connected from VOUT to VBIAS will be forward biased.
= 0.53(W)
The power dissipation depends on operating ambient
temperature for fixed TJ=125oC and thermal resistance
Capacitor Selection
The APL3526/B requires proper input capacitors to sup-
θJA. For APL3526/B packages, the Figure 2 of derating
curves allows the designer to see the effect of rising
ply current surge during stepping load transients to prevent the input voltage rail from dropping. Because the
ambient temperature on the maximum power allowed.
parasitic inductor from the voltage sources or other bulk
capacitors to the VIN pin limit the slew rate of the surge
1.4
1.3
Power Dissipation (W)
currents, more parasitic inductance needs more input
capacitance.
For normal applications (except OTP or output short circuit has occurred), the recommended input capacitance
of VIN is 1µF and output capacitance of VOUT is 0.1µF at
least. Please place the capacitors near the APL3526/B
1.1
1.0
0.9
0.8
0.7
0.6
as close as possible.
A bulk output capacitor, placed close to the load, is rec-
0.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (oC)
ommended to support load transient current.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Aug., 2013
1.2
Figure 2. Derating Curves for APL3526/B Package
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APL3526/B
Application Information
Layout Consideration
The PCB layout should be carefully performed to maximize thermal dissipation and to minimize voltage drop,
droop and EMI. The following guidelines must be
considered:
1. Please place the input capacitors near the VIN pin as
close as possible.
2. Output decoupling capacitors for load must be placed
near the load as close as possible for decoupling high
frequency ripples.
3. Locate APL3526/B and output capacitors near the load
to reduce parasitic resistance and inductance for excellent load transient performance.
4. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground plane
of the load.
5. Keep VIN and VOUT traces as wide and short as
possible.
Recommended Minimum Footprint
The via diameter = 0.305
Hole size = 0.203
Ground plane for Thermal PAD
0.3
0.54
1.3
0.3
0.5
0.8
Unit: mm
TDFN2x2-8
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APL3526/B
Package Information
TDFN2x2-8
A
b
E
D
Pin 1 dot
D2
A1
A3
NX
aaa C
E2
SEATING PLANE
L
K
Pin 1 Corner
e
S
Y
M
B
O
L
TDFN2x2-8
MILLIMETERS
INCHES
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.03
0.05
0.000
0.001
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.24
0.30
0.007
0.010
0.012
D
1.90
2.00
2.10
0.075
0.079
0.083
D2
1.00
1.30
1.60
0.039
0.051
0.063
E
1.90
2.00
2.10
0.075
0.079
0.083
E2
0.60
0.80
1.00
0.024
0.032
0.039
e
0.50 BSC
L
0.30
K
0.20
aaa
0.38
0.020 BSC
0.012
0.45
0.015
0.018
0.008
0.08
0.003
Note : 1. Follow from JEDEC MO-229 WCCD-3.
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APL3526/B
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN2x2-8
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.4
2.35±0.20
2.35±0.20
1.00±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TDFN2x2-8
Tape & Reel
3000
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APL3526/B
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
Classification Profile
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APL3526/B
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APL3526/B
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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