APL3538 Preliminary Ultra-Low On-Resistance, 6A Dual Load Switch with Soft Start Features Gereral Description • The APL3538 is an ultra-low On-resistance, dual powerdistribution switch with external soft start control. It inte- Ultra-Low On-Resistance -APL3538A/B: 20mΩ (Max.) grates two N-channel MOSFETs that can deliver 6A continuous load current each. The APL3538 can be enabled -APL3538C/D: 35mΩ (Max.) • • Low Quiescent Current: 30µA(max) by other power systems. Pulling and holding the voltage of EN pin (APL3538A) below 0.4V shuts off the output. Soft Start Time Programmable by External Capacitor • • • • • • • • • Pulling and holding the voltage of ENB pin (APL3538B) below 0.4V enable the output. The device integrates some protection features, including Over-Current Protection (OCP) and Over-Temperature Protection (OTP). The OCP can protect the device against current over-loads or shortcircuit events. The OTP function shuts down the N-channel MOSFET power switch when the junction temperature rises beyond 150°C and will automatically turns on the power switch when the temperature drops by 30°C. Wide Input Voltage Range (VIN): 0.8V to 5.5V Supply Voltage Range (VDD): 3V to 5.5V Over-Current Protection (OCP) Enable Control Function Output Discharge when Switch Disabled Reverse Current Blocking when Switch Disabled Over-Temperature Protection with Hysteresis The device is available in lead free TQFN2x2-14 package. Tiny small TQFN2x2-14 Package Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit Applications • • • Notebooks VDD VDD Tablet PC AIO PC VIN1 VIN1 VIN2 VOUT 1 VOUT1 APL3538A/BC/D VIN2 VOUT 2 VOUT2 EN1/ENB1 EN2/ENB2 SS1 GND SS2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 1 www.anpec.com.tw APL3538 Preliminary 8 VOUT2 9 SS2 10 SS1 7 VOUT2 VOUT1 12 VIN1 14 Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 6 ENB2 5 VIN2 VIN2 4 5 VIN2 VDD 3 ENB1 13 VIN2 4 VDD 3 GND 2 VIN1 1 VIN1 14 6 EN2 7 VOUT2 APL3538B/D TQFN 2x2-14 (Top View) GND 2 APL3538A/C TQFN 2x2-14 (Top View) VIN1 1 VOUT1 12 EN1 13 11 VOUT1 8 VOUT2 9 SS2 10 SS1 11 VOUT1 Pin Configurations 2 www.anpec.com.tw APL3538 Preliminary Ordering and Marking Information Product Code (Enable Function / RDS(ON )) A : Active High / 16mΩ (Typ.) B : Active Low / 16mΩ (Typ.) C : Active High / 25mΩ (Typ.) D : Active Low / 25mΩ (Typ.) Package Code QB : TQFN2x2-14 Operating Ambient Temperature Range I : -40 to 85OC Handling Code APL3538 Assembly Material Handling Code Temperature Range Package Code Product Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL3538A QB: L38A X X - Date Code APL3538B QB: L38B X X - Date Code APL3538C QB: L38C X X - Date Code APL3538D QB: L38D X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines ”Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Sym b o l (Note 1) Rat in g Un it V DD V DD to GN D Vo ltage Param ete r -0.3 ~ 6 V V IN x V IN x to G N D Voltage -0.3 ~ 6 V > 10µ s ec puls e width -0.3 ~ 6 V < 10µ s ec puls e width -1.4 ~ 6 V < 100 n sec p ulse width 8 V E Nx to G N D Voltage -0.3 ~ 6 V V ENB x E NBx to G N D Vo lta ge -0.3 ~ 6 V I OUT x C o nti nuo us O utp ut Cur rent, IO UT x VOU T x V OU T x to G ND Vo ltage V D Sx V IN x to V O UT x Voltage V EN x Inter nally Lim ited A M axim um J unc tion Tem perature -40 ~ 150 o C T ST G Sto rage Temperature -65 ~ 150 o C T SD R M axim um Le ad So ld eri ng Temperature (10 Seco nds) 260 o C TJ Note1: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 3 www.anpec.com.tw APL3538 Preliminary Thermal Characteristics Symbol Parameter Typical Value Junction-to-Ambient Thermal Resistance in free air θJA Unit (Note 2) o TQFN2x2-14 70 C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit V DD VDD Input Voltage (VDD≥V IN) 3.0 ~ 5.5 V V INx VINx Input Voltage 0.8 ~ 5.5 V 0~6 A VOUTx Output Current (Single Channel) I OUTx 8 A V IHx ENx/ENBx Logic High Input Voltage 1 ~ 5.5 V VILx ENx/ENBx Logic Low Input Voltage 0 ~ 0.4 V C SSx SSx Capacitance 0 ~ 10 nF Maximum Pulse Current, Pulse<300µs, 1% Duty Cycle (Single Channel) TA TJ -40 ~ 85 o -40 ~ 125 o Ambient Temperature Junction Temperature C C Note 3 : Refer to the typical application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over VINx= 5V, VDD=5V, VENx=5V (or VENBx=0V) and TA=-40~85oC. Typical values are at TA=25oC. S ymbol Param eter APL35 38A/B/C/D Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT VDD Sup ply Curr ent (b oth cha nnels) No load – 20 30 µA VDD Sup ply Curr ent (sing le cha nnel) No load – 15 25 µA No load, VDD=5V, VENx=0V – – 1 µA VDD Sup ply Curr ent at Shutdown VINx O ff-State Sup ply Curre nt (p er ch anne l) Reverse Lea ka ge Current (per cha nnel) No load, VDD=5V, VENBx=5V – 0.9 2 µA No load, VDD=5V, VINx=5V, V EN =0V or V ENB=5V – 0.1 8 µA No load, VDD=5V, VINx=3.3V, VEN=0V or VENB=5V – 0.1 3 µA No load, VDD=5V, VINx=1.8V, VENx=0V or VENB=5V – 0.1 2 µA No load, VDD=5V, VINx=0.8V, VENx=0V or VENB=5V – 0.1 1 µA VENx=0V or VENBx=5V, VOU Tx=5.5V, V IN x=0V – 0.1 16 µA 2.0 2.3 2.6 V – 0.1 – V UNDER-V OLTAGE LOCKOUT (UVLO) Rising VDD UV LO Th reshold o V DD rising, T J =25 C VDD UVLO Hysteresis Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 4 www.anpec.com.tw APL3538 Preliminary Electrical Characteristics Unless otherwise specified, these specifications apply over VINx= 5V, VDD=5V, V ENx=5V (or VENBx=0V) and TA=-40~85oC. Typical values are at TA=25oC. APL3538A/B/C/D Symbol Parameter Test Conditions Unit Min. Typ. Max. VDD=5V, I OUT x=6A, TJ=25o C – 16 20 VDD=3.3V, IO UTx=6A, TJ=25 C o – 20 24 mΩ VDD=5V, I OUT x=6A, TJ=25o C – 25 35 mΩ VDD=3.3V, IO UTx=6A, TJ=25o C – 31 42 mΩ 9 12 15 A TJ=-40~125 C 8 – – A VOUTx short to ground – – 1 µs – 12 – µs – 14 – kΩ Input Logic HIGH 1 V Input Logic Low – – – – 0.4 V POWER SWITCH 1 AND POWER SWITCH 2 Power Switch On Resistance (APL3538A/B) RDS(ON) Power Switch On Resistance (APL3538C/D) mΩ OVER CURRENT PROTECTION (OCP) I OCPx OCP Threshold (per channel) OCP Response Time TJ=25o C o SOFT-START CONTROL PIN (SS1 AND SS2) tR Internal Soft-Start Time RLx=10Ω, CSSx=0nF, VINx=1.05V VSSx=6V, VENx=Low or VENBx=High, measured at SSx Discharge Resistance SSx ENABLE INPUT PIN (EN1, EN2 OR ENB1, ENB2) tD(ON) tD(OFF) Input Current VENx=5.5V or VENBx=5.5V – – 1 µA Turn On Delay Time CSSx=0nF, RLx=10Ω, From being enabled to VO UT rising – 7 – µs – µs Turn Off Delay Time CSSx=0nF, RLx=10Ω – 5 Output Discharge Resistance VENx=0V or VENBx=5V, VOUTx force 1V – 100 150 Ω – 150 – °C – 30 – °C OVERT-TEMPERATURE PROTECTION (OTP) TO TPX OTP Threshold (per channel) THYS OTP Hysteresis Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 TJ rising 5 www.anpec.com.tw APL3538 Preliminary Timing Chart 50% 50% tR VEN tON tF tOFF 90% 50% 90% 50% VOUT VOUT 10% tD(OFF ) 10% tD( ON) Note4: Rise and fall times of the control signal is 100ns. Figure 1. tD(ON)/tD(OFF), tON/tOFF, tR/tF Waveforms Pin Descriptions PIN Function NO. NAME 1, 14 VIN1 Power supply Input of switch 1. Connect this pin to an external DC supply. 2 GND Power supply Input of switch. Connect this pin to an external DC supply. 3 VDD VDD voltage input pin for internal control circuitry. Connecting this pin to a 5V or 3.3V supply voltage provides the bias for the control circuitry and charge pump. 4, 5 VIN2 Power supply Input of switch 2. Connect this pin to an external DC supply. EN2 Enable input of switch 2. Logic high turns on switch. The EN2 pin cannot be left floating. ENB2 Enable input of switch 2. Logic low turns on switch. The ENB2 pin cannot be left floating. 6 7, 8 VOUT2 Output of switch 2. The output voltage follows the input voltage. When EN2 is low or ENB2 is high, the output voltage is discharged by an internal resistor. 9 SS2 Soft start control of switch 2. A capacitor from this pin to ground sets the VOUT’s rise slew rate. 10 SS1 Soft start control of switch 1. A capacitor from this pin to ground sets the VOUT’s rise slew rate. 11, 12 VOUT1 13 Output of switch 1. The output voltage follows the input voltage. When EN1 is low or ENB1 is high, the output voltage is discharged by an internal resistor. EN1 Enable input of switch 1. Logic high turns on switch. The EN1 pin cannot be left floating. ENB1 Enable input of switch 1. Logic low turns on switch. The ENB1 pin cannot be left floating. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 6 www.anpec.com.tw APL3538 Preliminary Block Diagram Bulk Select VIN1 VOUT1 VDD OCP 1 UVLO Charge Pump 1 Enable EN1 /ENB1 Control Logic EN2 /ENB2 GND Enable SS1 SS 2 OTP1 OTP2 Charge Pump 2 OCP 2 VOUT2 VIN2 Bulk Select Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 7 www.anpec.com.tw APL3538 Preliminary Typical Application Circuit VDD VDD C DD 1µ F VIN1 C IN1 22µF C1 Optional VIN1 VOUT1 APL3538 A/C C OUT1 22µF RL 1 C OUT2 22µF RL 2 C OUT1 22µF RL 1 C OUT2 22µF RL 2 VIN2 VIN2 C IN2 22µF C2 Optional On VOUT2 EN1 Off On GND EN2 Off SS 1 SS 2 C SS1 Optional C SS2 Optional VDD VDD C DD 1µF VIN1 VIN1 C1 Optional VOUT1 C IN1 22µF APL3538 B/D VIN2 VIN2 C2 Optional Off C IN2 22µF VOUT2 ENB1 On Off On GND ENB2 SS 1 SS 2 C SS1 Optional Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 8 C SS2 Optional www.anpec.com.tw APL3538 Preliminary Function Description Under-voltage Lockout (UVLO) Over-Temperature Protection A Under-Voltage Lockout (UVLO) circuit monitors the VDD pins voltage to prevent wrong logic controls. The UVLO When the junction temperature exceeds 150°C, the internal thermal sense circuit turns off the power FET and function initiates a soft-start process after the VDD supply voltages exceed rising UVLO voltage threshold during allows the device to cool down. When the device’s junction temperature cools by 30°C, the internal thermal sense powering on. circuit will enable the device, resulting in a pulsed output during continuous thermal protection. Thermal protec- Power Switch tion is designed to protect the IC in the event of over temperature conditions. For normal operation, the junction The power switch is an N-channel MOSFET with a ultralow RDS(ON). When IC is in shutdown state (VEN1,2=Low or temperature cannot exceed TJ=+125°C. VENB1,2=High), the MOSFET prevents a reverse current flowing from the VOUT back to VIN. When IC is in UVLO state, the internal parasitic diodes connected from VOUT to VIN will be forward biased. Over-Current Protection (OCP) The APL3538 power switch provides the OCP function. When the output current reaches the OCP threshold, the device is turned off and the output is latched to be floating until ENx or ENBx is toggled. Soft-Start The APL3538 provides an adjustable soft-start circuitry to control rise rate of the output voltage and limit the current surge (ISURGE,Max<7.5A) during start-up. The soft-start time is set with a capacitor from the SSx pin to the ground. Enable Control The APL3538 has a dedicated enable pin (ENx or ENBx). A logic low/high signal applied to this pin shuts down the output. Following a shutdown, a logic high/low signal reenables the output through initiation of a new soft-start cycle. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 9 www.anpec.com.tw APL3538 Preliminary Application Information A 22µF or higher ceramic bypass capacitor from VIN to Power Sequencing VDD GND, located near the APL3538, is strongly. Additional input capacitance may be needed on the input to reduce VINx voltage overshoot from exceeding the absolute maximum voltage of the device during heavy load transient or shortcircuit conditions. When the load current trips the OCP threshold in an over load condition such as a short circuit, VENx the IC immediately turns off the internal power switch that will cause VIN ringing due to the parasitical inductance VENBx between power source and VIN. VOUTx Output Capacitor Selection VENx The APL3538 requires proper output capacitors to sup- VENBx ply current surge during stepping load transients to prevent the output voltage rail from dropping. A 22µF ceramic VOUTx bypass capacitor from VOUT to GND, located near the APL3538, is strongly. Additional output capacitance may VINx be needed on the output to reduce voltage undershoot from exceeding the absolute maximum ratings (VOUTx and VDSx) of the device during OCP condition. VDD Thermal Consideration Figure 2. APL3538 Power Sequencing Diagram The APL3538 maximum power dissipation depends on the differences of the thermal resistance and tempera- The APL3538 has a built-in reverse current blocking circuit to prevent a reverse current flowing through the body ture between junction and ambient air. The power dissipation PD across the device is: diode of power switch from the VOUTx back VINx pin when power switch disabled. The reverse current blocking cir- PD = (TJ - TA) / θJA cuit is not active before VDD is ready. When IC is in UVLO state, the internal parasitic diodes of power switch connected from VOUTx to VINx will be forward biased. Otherwise, VOUTx should not be higher than VDD, and VDD where (TJ-TA) is the temperature difference between the junction and ambient air. θJA is the thermal resistance between junction and ambient air. must be higher than the voltage of any other input pin, the reason is that the internal parasitic diodes connected from VOUTx to VDD will be forward biased. For normal operation, do not exceed the maximum operating junction temperature of TJ = 125°C. The calculated Input Capacitor Selection power dissipation should be less than: The APL3538 requires proper input capacitors to supply current surge during stepping load transients to prevent PD(MAX) = (125 - 25) / 70 = 1.42 (W) …………………………… TA =25°C the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk ca- PD(MAX) = (125 - 85) / 70 pacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input = 0.57(W) ………………………….... TA =85°C capacitance. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 10 www.anpec.com.tw APL3538 Preliminary Application Information Thermal Consideration To ensure proper operation, the maximum junction temperature of the APL3538 should not exceed 125°C. Several factors attribute to the junction temperate rise: load current, MOSFET on resistance, junction-to-ambient thermal resistance, and ambient temperature. The maximum load current can be determined by: I OUT 1( MAX ) + I OUT 2 ( MAX ) ≤ 2 2 I OUT 1( MAX ) + I OUT 2 ( MAX ) ≤ PD ( MAX ) RDS ( ON ) + 2 × I OUT 1( MAX ) × I OUT 2 ( MAX ) PD ( MAX ) RDS ( ON ) 2 2 ……VDD=5V, T =25°C I OUT 1( MAX ) + I OUT 2 ( MAX ) ≤ 71 A 2 2 ……VDD=3.3V, T =25°C I OUT 1( MAX ) + I OUT 2 ( MAX ) ≤ 59 A It is noted that the maximum continuous output current (IOUT1 or IOUT2) is 6A. Exceeding the maximum continuous output current may cause permanent damage to the device. Layout Consideration The PCB layout should be carefully performed to maximize thermal dissipation and to minimize voltage drop, droop and EMI. The following guidelines must be considered: 1. Please place the input capacitors near the VINx pin as close as possible. 2. Output decoupling capacitors for load must be placed near the load as close as possible for decoupling high frequency ripples. 3. Locate APL3538 and output capacitors near the load to reduce parasitic resistance and inductance for excellent load transient performance. 4. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 5. Keep VINx and VOUTx traces as wide and short as possible. Copyright ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 11 www.anpec.com.tw APL3538 Preliminary Package Information TQFN2x2-14 D b E A PIN 1 dot A1 A3 NX aaa Pin1 Corner C L SEATING PLANE e S Y M B O L e/2 TQFN2*2-14 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.15 0.25 0.006 0.010 D 1.90 2.10 0.075 0.083 E 1.90 2.10 0.075 0.083 e L 0.40 BSC 0.27 aaa Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 0.016 BSC 0.011 0.43 0.08 0.017 0.003 12 www.anpec.com.tw APL3538 Preliminary Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 2.35±0.20 2.35±0.20 1.00±0.20 TQFN2x2 (mm) Devices Per Unit Package Type Unit Quantity TQFN2x2 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 13 www.anpec.com.tw APL3538 Preliminary Taping Direction Information TQFN2x2 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 14 www.anpec.com.tw APL3538 Preliminary Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 15 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL3538 Preliminary Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. P.1 - Sep, 2015 16 www.anpec.com.tw