AOZ7111 Critical Conduction Mode PFC Controller General Description Features The AOZ7111 is an active power factor correction (PFC) controller for boost PFC applications that operate in critical conduction mode (CRM). The device uses a voltage mode PWM which does not need rectified AC line voltage information, it saves the power loss of an input sensing network necessary for traditional currentmode CRM PFC controller. The AOZ7111 minimizes the number of external components by integrating safety features that make it an excellent choice for designing robust PFC stages. No AC input voltage sensing requirement The AOZ7111 is available in a SO-8 package and it is rated over a -40°C to +125°C ambient temperature range. AC Fault Detect™ makes system more robust Maximum switching frequency limitation Additional OVP detection pin Output over-voltage / open-feedback protection and disable function Internal closed loop soft-start Dynamic OVP function Non-linear gain error amplifier enable fast line and load transient response No need for the auxiliary winding with minus current detection (ZCD) 150µs internal start-up timer MOSFET over-current protection and inductor saturation protection Under-voltage lockout with hysteresis Lower startup and operating current +300mA / -800mA peak gate drive current Thermal shutdown SO-8 package Applications Adapter / ballast LCD TV / LED TV SMPS Typical Application VOUT AOZ7111 VCC Line AC VCC OUT + Filter CT + INV COMP OVP CS GND Figure 1. Typical Boost PFC Application Rev. 1.0 January 2013 www.aosmd.com Page 1 of 15 AOZ7111 Ordering Information Part Number Ambient Temperature Range Package Environmental AOZ7111AI -40°C to +125°C SO-8 Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information. Pin Configuration INV 1 8 VCC CT 2 7 OUT COMP 3 6 GND OVP 4 5 CS SO-8 (Top View) Pin Description Pin Number Pin Name 1 INV Inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5V. 2 CT The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by comparing the Ct voltage to an internal voltage derived from VCOMP. The Ct pin discharge the external timing capacitor at the end of the on time. 3 COMP 4 OVP 5 CS 6 GND The GND pin is analog ground. 7 OUT This pin is the gate drive output. 8 VCC This is the IC supply pin. Rev. 1.0 January 2013 Pin Function This pin is the output of the transconductance error amplifier. Components for the compensation should be connected between this pin and GND. The OVP pin is used to detect PFC output over-voltage when the INV pin information is not correct. This pin is the input of the zero current detection and over-current protection comparator. www.aosmd.com Page 2 of 15 AOZ7111 Absolute Maximum Ratings Exceeding the Absolute Maximum Ratings may damage the device. Symbol Min Max Units Supply Voltage -0.3 20 V IOH, IOL Peak Drive Output Current -800 +300 mA ICLAMP Driver Output Clamping Diode VO>VCC or VO<-0.3V -10 +10 mA INV, OVP Pin Input Voltage -0.3 5 V CT, COMP Pin Input Voltage -0.3 9.5 V CS Pin Input Voltage -5 0.3 V Driver Output Voltage -0.3 VCC V +150 °C °C VCC VIN Parameter TJ Operating Junction Temperature TA Operating Temperature Range -40 +125 TS Storage Temperature Range -65 ESD TL JA +150 °C Electrostatic Discharge Capability (Human Body Model, JES22-A114) 2.5 kV Lead Temperature (Soldering, 10s) 300 °C Package Thermal Resistance (Junction-to-Ambient) 150 °C/W Electrical Characteristics TA = 25°C, VCC = 14V, unless otherwise specified(1) Symbol Parameter Conditions Min Typ Max Units SUPPLY Operating Range After Turn On 18 V VSTART Start Threshold Voltage VCC Increasing 11 12 13 V VSTOP Stop Threshold Voltage VCC Decreasing 8.5 9.5 10.5 V VCC VUVLO_HY VZ IIN_NS ISTB 10.5 Input Under-Voltage Lockout Hysteresis 2.5 V Zener Voltage ICC = 20mA 18 20 22 V Non-Switching Supply Current VCOMP < 0.9V, VIN = 14V 0.5 1.0 1.5 mA Standby Current VINV < 0.2V 30 60 µA 2.5 2.535 V 10 mV 125 µS ERROR AMPLIFIER Voltage Reference TJ = 25°C Line Regulation VCC = 14V ~ 18V Gm Transconductance VINV = 2.4V to 2.6V IO Error Amplifier Current Capability Source: VINV = VREF -0.1V Sink: VINV = VREF +0.1V VREF VREF_LINE Ct_OFFSET 2.465 75 Minimum Control Voltage to Generate Drive Pluses 100 -10 +10 µA 1.0 V 350 KHz RAMP OSCILLATOR FMAX TSTART Maximum Oscillating Frequency Restart Timer Delay VCT(MAX) CT Peak Voltage ICHARGE On Time Capacitor Charge Current Rev. 1.0 January 2013 50 VCOMP = Open 300 8 150 www.aosmd.com 150 200 µs V 250 µA Page 3 of 15 AOZ7111 Electrical Characteristics (Continued) TA = 25°C, VCC = 14V, unless otherwise specified(1) Symbol Parameter Conditions Min Typ Max Units Zero Current Detection Comparator Threshold -24 -15 -9 mV VOCP1 OCP1 Threshold Voltage (Shutdown Mode) -0.8 -0.7 -0.6 V VOCP2 OCP2 Threshold Voltage (Latch Mode) -1.2 V TZCD, D Output Delay from ZCD to Output Turn-On 650 ns ZERO CURRENT DETECTION VZCD-TH GATE DRIVE ROH Drive Pull-Up Resistance ISOURCE = 50mA ROL 24 30 6 Ω Drive Pull-Down Resistance ISINK = 50mA 5 TRISE Output Rise Time CL = 1nF, 10% to 90% 70 ns Ω TFALL Output Fall Time CL = 1nF, 90% to 10% 25 ns PROTECTION VDOVP Dynamic OVP Threshold Voltage HVOVP_INV Dynamic OVP Hysteresis VOVP_INV OVP Threshold Voltage @ INV Pin HVOVP_INV OVP Hysteresis @ INV Pin VOVP TA = 25°C 2.54 TA = 25°C TA = 25°C OVP Threshold Voltage @ OVP Pin TA = 25°C INV Enable Threshold TA = 25°C HYEN INV Enable Hysteresis TA = 25°C OTP Over-Temperature Shutdown Limit TJ Rising TJ Falling THYS Hysteresis Temperature of OTP 2.61 0.05 2.62 TA = 25°C VEN_INV 2.575 2.685 V 2.75 0.175 2.65 2.75 0.055 V V 2.85 0.5 0.01 V V V 0.120 V 150 100 °C 50 °C Note: 1. Specifications in BOLD indicate an ambient temperature range -40°C to +125°C. These specifications are guaranteed by design. Rev. 1.0 January 2013 www.aosmd.com Page 4 of 15 AOZ7111 Functional Block Diagram CS LEB -15mV + -0.7V – + – ZCD Internal +5V S OCP 2.75V Q R Restart Timer + DRV EAmp INV Vz Delay POR 2.5V VCC + – UVLO & POR Reference & Bias OVP Fmax Limit – S 100µS Gate Driver OUT Q R – COMP + + – Dynamic OVP 2.575V CT AC Input Fault Detect Ramp Control 1st OVP – + 2.685V GND Rev. 1.0 January 2013 www.aosmd.com Page 5 of 15 AOZ7111 Typical Characteristics Start Threshold vs. Temperature 13.0 240 12.8 230 12.6 Start Threshold (V) Charge Current (µA) Charge Current vs. Temperature 250 220 210 200 190 180 12.4 12.2 12.0 11.8 11.6 170 11.4 160 11.2 150 -150 -25 0 25 50 75 100 11.0 -150 125 -25 0 Temperature (°C) 10.3 -0.62 10.1 -0.64 9.9 -0.66 9.7 9.5 9.3 -0.76 8.7 -0.78 50 125 100 125 100 125 -0.72 -0.74 25 100 -0.70 8.9 0 75 -0.68 9.1 -25 50 OPC1 vs. Temperature -0.60 OPC1 (V) Stop Threshold (V) Stop Threshold vs. Temperature 10.5 8.5 -150 25 Temperature (°C) 75 100 -0.80 -150 125 -25 0 Temperature (°C) 25 50 75 Temperature (°C) OVP vs. Temperature OVP_INV vs. Temperature 2.85 2.72 2.70 OVP_INV (V) OVP (V) 2.80 2.75 2.70 2.65 -150 2.68 2.66 2.64 -25 0 25 50 75 100 125 Temperature (°C) Rev. 1.0 January 2013 2.62 -150 -25 0 25 50 75 Temperature (°C) www.aosmd.com Page 6 of 15 AOZ7111 Typical Characteristics (Continued) EN_INV vs. Temperature Reference vs. Temperature 0.80 2.535 0.75 2.525 Reference (V) EN_INV (V) 0.70 0.65 0.60 0.55 0.50 2.505 2.495 2.485 2.475 0.45 0.40 -150 2.515 -25 0 25 50 75 100 125 2.465 -150 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) Restart Timer Delay vs. Temperature Max Frequency vs. Temperature 300 400 Restart Timer Delay (µs) Max Frequency (KHz) 390 380 370 360 350 340 330 320 250 200 150 100 310 300 -150 -25 0 25 50 75 100 50 125 -150 -25 0 ZCD Comparator Threshold (mV) Output Delay (ns) 850 800 750 700 650 -25 0 25 50 75 100 125 75 100 125 -8 -10 -12 -14 -16 -18 -20 -22 -24 -150 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Rev. 1.0 January 2013 50 ZCD Comparator Threshold vs. Temperature Output Delay vs. Temperature 900 600 -150 25 Temperature (°C) Temperature (°C) www.aosmd.com Page 7 of 15 AOZ7111 Detailed Description The AOZ7111 is a voltage mode active power factor correction (PFC) controller designed for cost-effective boost PFC applications that operate in critical conduction mode (CRM). Its voltage mode scheme does not require an AC input line-sensing network, usually necessary for a current mode CRM PFC controller. It gets the ZCD signal pulse from the current sense resistor; therefore, ZCD auxiliary winding is not needed. AOZ7111 features output over-voltage protection, overcurrent protection, open-feedback protection, and undervoltage lockout protection. A unique AC input fault detection circuit makes the system more robust during the AC absent test. The additional OVP pin can be used to double check the output voltage if the feedback resistor gets damaged. The controller also implements comprehensive safety features for robust designs. The AOZ7111 is available in SO-8 package. Error Amplifier Regulation AOZ7111 regulates the boost output voltage using an internal transconductance error amplifier (EA) with a typical transconductance value of 100µS. The advantage in using a transconductance error amplifier is that the INV pin voltage is only determined by the resistor divider network connected to the output voltage, not the operation of the amplifier. This enables the INV pin to be used for sensing over-voltage or under-voltage conditions independently of the error amplifier. The negative terminal of the EA is pinned out to INV, the positive terminal is connected to a 2.5V (±1.8%) reference (VREF), and the EA output is pinned out COMP. The output of the error amplifier (COMP) is connected to the PWM comparator and controls the on-time of the OUT output. The sink and source current capability of the error amplifier is approximate 10µA during normal operation. When the INV pin voltage is over the normal operating conditions (VINV>2.6V, or VINV<2.4V if the error is large), additional circuitry is activated to enhance the slew-rate of the error amplifier, it enables fast line and load transient response. Rev. 1.0 January 2013 ICOMP Source 200µS 2.4V 2.5V 2.6V INV 100µS Sink Figure 2. Non-linear Gain Characteristics The output voltage of PFC contains a high ripple frequency, 2 times the AC power line (50Hz or 60Hz). The VOUT ripple is attenuated by the regulation loop to ensure VCOMP is constant during the AC line cycle. In order to obtain a stable operation and ensure VCOMP is constant during the AC line cycle, the bandwidth should typically be set below 20Hz so that the regulation block output may be relatively constant over a given AC line cycle. Soft-Start AOZ7111 employs an internal soft-start function to suppress inrush current and overshoot of output voltage during the startup. The soft-start circuit works after UVLO and standby are released and before the soft-start cancellation voltage is exceeded. During the soft-start, the OTA supplies a constant 10µA into the compensation network at the COMP pin. The voltage at this pin rises linearly as well as the amplitude of the input current. As soon as the output voltage VOUT reaches 95% of its rated level, the startup procedure is finished and the normal voltage control takes over. www.aosmd.com Page 8 of 15 AOZ7111 VOUT VCOMP varies with the RMS input voltage and output load, the on time is constant during the AC line cycle if the values of the compensation components are sufficient to filter out the VOUT ripple. The maximum on time of the controller occurs when VCOMP is at the maximum. The Ct capacitor is sized to ensure that the required on time is reached at maximum output power and the minimum input voltage condition. Rated output 95% rated t The minimum Ct value is calculated as below: IDS 2 P OUT L I ch arg e Ct min = -------------------------------------------------------------2 EFF V AC V Ct max VCOMP Current Detection Block t The current detection circuit is composed of zero current detection and over-current detection. Figure 3. Soft-Start Sequence On Time Control (Ramp Control Oscillator) The switching pattern consists of constant on times and variable off times for a given RMS input voltage and output load. The AOZ7111 controls the on-time with the capacitor connected to the Ct pin. A current source charges the Ct capacitor to a voltage derived from the COMP pin voltage (VCt(off)). VCt(off) is calculated as below: 2 P OUT L I ch arg e V Ct off = V COMP – C t offset = ----------------------------------------------------------------2 EFF V AC C t V CS = – R CS I L where, L is the inductor current; RCS is the current sense resistor; VCS is the measured voltage. Zero Current Detection The zero current detection function guarantees that the MOSFET can not turn on as long as the inductor current has not reached zero. When VCt(off) is reached, the drive turns off. The ramp oscillator consists of three phases: Charge Phase: The oscillator capacitor voltage grows linearly from its bottom value (ground) until it exceeds VCOMP - Ct(offset). At that moment, the PWM latch output gets low and the oscillator discharge sequence is set. Discharge Phase: The oscillator capacitor is discharged down to its valley value of 0V. Standby Phase: At the end of the discharge sequence, the oscillator voltage is maintained in a low state until the PWM latch is set again. Rev. 1.0 January 2013 The inductor current is converted into a voltage by inserting a ground reference resistor (RCS) series with the input diode bridge and the input filtering capacitor. Therefore, a negative voltage proportional to the inductor current is built: The negative signal VCS is applied to the current sense at pin 5. The pin 5 voltage is compared to the -15mV threshold so that as long as VCS is lower than this threshold, the current sense comparator resets the PWM latch to force the gate drive signal low state. Consequently, it is not possible to turn on the power MOSFET until the inductor current is measured smaller than (15mV/RCS), nearly at zero. www.aosmd.com Page 9 of 15 AOZ7111 Maximum Switching Frequency Limit VCOMP Ramp+ Offset t IL t t CS -15mV ZCD Because the MOSFET turn-on depends on the CS input, switching frequency may increase to higher than several MHz due to the mis-triggering or noise on the nearby CS pin. If the switching frequency is higher than needed for critical conduction mode, it will enter CCM. In CCM, inductor current can be raised very high, which may exceed the current rating of the power switch or diode. This can seriously damage the power switch and burn it down. To avoid this, the maximum switching frequency limitation is embedded. If the ZCD signal is applied again within 2.9µs after the previous edge of gate signal, this signal is ignored and AOZ7111 waits for another ZCD signal. Overvoltage Protection (OVP) OUT t Figure 4. Switching and Current Sense Operation Over-Current Protection The over-current detection protective circuit detects the inductor current and protects the power MOSFET by turning off the output driver when it becomes higher than the set current level. With the over-current detection, the voltage across the current detection resistance RCS connected to the GND is fed to the CS pin. If the CS pin voltage compared by the over-current detection comparator becomes lower than -0.7V, it is then regarded as over-current state; therefore, the feed-forward of the output driver is reset to turn off the power MOSFET. Restart Timer AOZ7111 utilizes self-oscillation instead of the oscillator with fixed frequency. In steady operation, it turns on the MOSFET with a signal from the zero current detector. In startup or light load conditions, a trigger signal is required for starting up or stable operation. When the output of the IC continues turn-off (150µs or more), the restart trigger signal is automatically generated. Rev. 1.0 January 2013 It is critical that over voltage protection (OVP) prevents the output voltage exceeding the ratings of PFC stage components. Over-voltage protection (OVP) is embedded by the information at the INV pin. That information comes from the output through the voltage dividing resistors. AOZ7111 has dynamic OVP function to narrow the on time when the INV voltage is higher than 2.575V. When the voltage further rises and exceeds the comparator reference voltage of static OVP (2.685V), the OVP comparator shuts down the output drive pulse. The OVP logic includes hysteresis to ensure that output voltage has sufficient time to discharge before the AOZ7111 driver recovery and also to ensure noise immunity. Additional OVP detection Over-voltage protection (OVP) is embedded by the information at the INV pin. That information comes from the output through the voltage dividing resistors. When the upper divider resistor gets damaged and resistance becomes too high the output electrolytic capacitor may explode. To prevent such a catastrophe the additional OVP pin is assigned to double check output voltage. When the second OVP triggers, switching can be recovered only when the VCC supply voltage falls below VSTOP and builds up higher than UVLO again. www.aosmd.com Page 10 of 15 AOZ7111 VOUT VOUT RFB1 INV pin ROVP1 RFB2 VAC t + 1.07*VREF VCOMP t OVP pin + S ROVP2 Q IDS t 1.1*VREF POR R Figure 6. Operation with AC Input Fault Detection Under Voltage Lock Out (UVLO) Figure 5. OVP Circuitry Around INV and OVP Pin AC Input Fault Detection AOZ7111 does not require an AC input voltage sensing, nor does it need the auxiliary winding with minus current detection. In general, the VCC of PFC controller is supplied by a system standby power supply, a mismatch may occur in a worst case scenario. A worst case scenario could be AC input chattering: the electric AC power source is suddenly absent for two or three additional AC line cycles, VCC is still higher than UVLO (VSTOP) during this time, so the voltage control loop tries to compensate for the VOUT drop and VCOMP will increase until it reaches its maximum clamp level. During the AC input recovery, high comp leads to very high switching current and severe stress is put on both the MOSFET and boost diode. To ensure that the system is more robust and reliable, AOZ7111 has a unique AC input fault detection circuit to protect against this type of scenario. If the AC input voltage is absent two or three additional cycles, internal soft-start is reset and waits for the AC input recovery again. During the AC input recovery, soft-start manages turn-on time allowing the switching current to increase smoothly. Rev. 1.0 January 2013 UVLO function is used to prevent controller malfunction when VCC supply voltage drops. When VCC supply voltage reaches 12V (typ), the internal block of the IC is enabled and starts operation. When VCC supply voltage drops below 9.5V (typ), most of the internal circuit is disabled to reduce the IC current consumption. Under Voltage Protection (UVP) AOZ7111 detects the under voltage fault if VINV is less than VEN_INV. The UVP comparator disables the operation when VINV is less than 0.5V and there is 55mV hysteresis. An external small-signal MOSFET can be used to disables the IC. During disable mode, the current consumption of the IC decreases to 60µA or less. www.aosmd.com Page 11 of 15 AOZ7111 Application Information Alpha and Omega Semiconductor provides an EXCEL based design tool, an application note and a demonstration board to help the design of AOZ7111 and reduce the R&D cycle time. All the tools can be download from: www.aosmd.com. PCB Layout Guide The following are good PCB layout guideline for a PFC stage: 1. To keep the IC GND pin as clean as possible, the power stage ground and the signal ground must be separated. 2. The PFC MOSFET gate drive loop path should be minimized. 3. Minimize the trace length to INV pin. Since the feedback node is high impedance the trace from the output resistor divider to INV pin should be as short as possible. 4. Switching current sense (CS pin) is very important for the stable operation of PFC stage. Normally, a RC filter is recommended to reduce the noise applied to the CS pin. Figure 7. Recommended PCB Layout 5. The VCC decoupling capacitor CVCC need to be placed close to IC VCC and GND pin as much as possible. Rev. 1.0 January 2013 www.aosmd.com Page 12 of 15 AOZ7111 Package Dimensions, SO-8L D Gauge plane Seating plane 0.25mm e 8 E h x 45° E1 L c 1 θ 7° (4x) A2 A 0.10mm A1 b 2.20 RECOMMENDED LAND PATTERN 2.87 5.74 1.27 0.80 0.635 Dimensions in millimeters Dimensions in inches Symbols A Min. 1.35 Nom. 1.65 Max. 1.75 Symbols A Min. 0.053 Nom. 0.065 Max. 0.069 A1 A2 b 0.10 1.25 0.31 — 1.50 — 0.25 1.65 0.51 A1 A2 b 0.004 0.049 0.012 — 0.059 — 0.010 0.065 0.020 c D E e E1 h L θ 0.17 4.80 3.80 0.25 5.00 4.00 c D E e E1 h L θ 0.007 0.189 0.150 — 4.90 3.90 1.27 BSC 5.80 6.00 0.25 — 0.40 — — 0° 6.20 0.50 1.27 8° — 0.010 0.193 0.197 0.154 0.157 0.050 BSC 0.228 0.236 0.244 0.010 — 0.020 0.016 — 0.050 — 0° 8° UNIT: mm Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating. 3. Package body size exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils each. 4. Dimension L is measured in gauge plane. 5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact. Rev. 1.0 January 2013 www.aosmd.com Page 13 of 15 AOZ7111 Tape and Reel Dimensions, SO-8L Carrier Tape P1 D1 P2 T E1 E2 E B0 K0 A0 D0 P0 Feeding Direction UNIT: mm Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T SO-8 (12mm) 6.40 ±0.10 5.20 ±0.10 2.10 ±0.10 1.60 ±0.10 1.50 ±0.10 12.00 ±0.10 1.75 ±0.10 5.50 ±0.10 8.00 ±0.10 4.00 ±0.10 2.00 ±0.10 0.25 ±0.10 Reel W1 S G N M K V R H W UNIT: mm W N Tape Size Reel Size M 12mm ø330 ø330.00 ø97.00 13.00 ±0.10 ±0.30 ±0.50 W1 17.40 ±1.00 H K ø13.00 10.60 +0.50/-0.20 S 2.00 ±0.50 G — R — V — Leader/Trailer and Orientation Trailer Tape 300mm min. or 75 empty pockets Rev. 1.0 January 2013 Components Tape Orientation in Pocket www.aosmd.com Leader Tape 500mm min. or 125 empty pockets Page 14 of 15 AOZ7111 Part Marking AOZ7111AI (SO-8) Z7111AI FAYWLT Part Number Code Assembly Lot Code Fab & Assembly Location Year & Week Code LEGAL DISCLAIMER Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or completeness of the information provided herein and takes no liabilities for the consequences of use of such information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes to such information at any time without further notice. This document does not constitute the grant of any intellectual property rights or representation of non-infringement of any third party’s intellectual property rights. LIFE SUPPORT POLICY ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. Rev. 1.0 January 2013 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.aosmd.com Page 15 of 15