NSC CLC5612IN

N
CLC5612
Dual, High Output, Programmable Gain Buffer
General Description
Features
The CLC5612 is a dual, low-cost, high-speed (90MHz) buffer
which features user-programmable gains of +2, +1, and
-1V/V. The CLC5612 also has a new output stage that delivers
high output drive current (130mA), but consumes minimal
quiescent supply current (1.5mA/ch) from a single 5V supply. Its
current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over
a wide range of gains and signal levels, and has a linear-phase
response up to one half of the -3dB frequency.
■
The CLC5612 offers 0.1dB gain flatness to 18MHz and differential gain and phase errors of 0.15% and 0.02°. These features are
ideal for professional and consumer video applications.
Applications
130mA output current
0.15%, 0.02° differential gain, phase
1.5mA/ch supply current
90MHz bandwidth (Av = +2)
-87/-93dBc HD2/HD3 (1MHz)
17ns settling to 0.05%
290V/µs slew rate
Stable for capacitive loads up to 1000pf
Single 5V to ±5V supplies
■
■
■
■
■
■
■
■
Video line driver
Coaxial cable driver
Twisted pair driver
Transformer/coil driver
High capacitive load driver
Portable/battery-powered applications
A/D driver
■
■
■
The CLC5612 offers superior dynamic performance with a
90MHz small-signal bandwidth, 290V/µs slew rate and 6.2ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive, and high-speed performance make
the CLC5612 well suited for many battery-powered personal
communication/computing systems.
■
■
■
■
CLC5612
Dual, High Output, Programmable Gain Buffer
June 1999
Maximum Output Voltage vs. RL
10
The ability to drive low-impedance, highly capacitive loads,
makes the CLC5612 ideal for single ended cable applications.
It also drives low impedance loads with minimum distortion.
The CLC5612 will drive a 100Ω load with only -74/-86dBc
second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz).
With a 25Ω load, and the same conditions, it produces only -70/
-67dBc second/third harmonic distortion. It is also optimized for
driving high currents into single-ended transformers and coils.
Output Voltage (Vpp)
9
8
VCC = ±5V
7
6
5
4
3
Vs = +5V
2
When driving the input of high-resolution A/D converters, the
CLC5612 provides excellent -87/-93dBc second/third harmonic
distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast
settling time.
1
10
100
1000
RL (Ω)
Typical Application
Differential Line Driver with Load Impedance Conversion
Rm/2
Req
8
1
1kΩ
2
1kΩ
-
7
+
Vin
3
1kΩ
1kΩ
Io
Zo
RL
UTP
Rm/2
OUT1
-IN1
-Vd/2
1kΩ
-
OUT2
+
6
+IN1
5
CLC5612
+VCC
1kΩ
+
4
Pinout
DIP & SOIC
1kΩ
1kΩ
-IN2
-
Rt
+
Vo
-
-VCC
Rt2
+
Vd/2
1:n
+IN2
Note: Supplies and bypassing not shown.
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
+5V Electrical Characteristics (A
PARAMETERS
Ambient Temperature
v
= +2, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
CONDITIONS
CLC5612IN/IM
TYP
+25°C
MIN/MAX RATINGS
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 0.5Vpp
Vo = 2.0Vpp
-0.1dB bandwidth
Vo = 0.5Vpp
gain peaking
<200MHz, Vo = 0.5Vpp
gain rolloff
<30MHz, Vo = 0.5Vpp
linear phase deviation
<30MHz, Vo = 0.5Vpp
differential gain
NTSC, RL = 150Ω to -1V
differential phase
NTSC, RL = 150Ω to -1V
75
62
18
0
0.2
0.1
0.09
0.14
50
57
13
0.5
0.9
0.4
–
–
50
54
11
0.9
1.0
0.5
–
–
50
52
11
1.2
1.0
0.5
–
–
MHz
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
5.5
20
3
185
9.0
28
6.5
150
9.7
45
14
130
10.5
70
14
120
ns
ns
%
V/µs
-74
-79
-65
-86
-81
-60
-70
-77
-58
-82
-79
-55
-67
-72
-58
-79
-76
-53
-67
-72
-58
-79
-76
-53
dBc
dBc
dBc
dBc
dBc
dBc
3.4
6.3
8.7
-80
4.4
8.2
11.3
–
4.9
9.0
12.4
–
4.9
9.0
12.4
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
8
80
3
25
±0.3
1000
48
47
1.5
30
–
14
–
±1.5
±20%
45
45
1.7
35
–
18
–
±2.0
±26%
43
43
1.8
35
–
18
–
±2.0
±30%
43
43
1.8
mV
µV/˚C
µA
nA/˚C
%
Ω
dB
dB
mA
0.41
2.2
4.2
0.8
4.0
1.0
4.1
0.9
100
400
0.29
3.3
4.1
0.9
3.9
1.1
4.0
1.0
80
600
0.26
3.3
4.0
1.0
3.8
1.2
4.0
1.0
65
600
0.26
3.3
4.0
1.0
3.8
1.2
3.9
1.1
40
600
MΩ
pF
V
V
V
V
V
V
mA
mΩ
2V step
1V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
crosstalk (input referred)
10MHz, 1Vpp
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current (non-inverting)
average drift
gain accuracy
internal resistors (Rf, Rg)
power supply rejection ratio
common-mode rejection ratio
supply current (per amplifier)
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
input voltage range, High
input voltage range, Low
output voltage range, High
RL = 100Ω
output voltage range, Low
RL = 100Ω
output voltage range, High
RL = ∞
output voltage range, Low
RL = ∞
output current
output resistance, closed loop
DC
NOTES
A
A
A
A
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Notes
A) J-level: spec is 100% tested at +25°C.
B) The short circuit current can exceed the maximum safe
output current.
1) Vs = VCC - VEE
supply voltage (VCC - VEE)
output current (see note C)
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
Reliability Information
Transistor Count
MTBF (based on limited test data)
http://www.national.com
98
285Mhr
2
+14V
140mA
VEE to VCC
+150°C
-65°C to +150°C
+300°C
±5V Electrical Characteristics (A
v
PARAMETERS
Ambient Temperature
= +2, RL = 100Ω, VCC = ±5V, unless specified)
CONDITIONS
CLC5612IN/IM
TYP
+25°C
GUARANTEED MIN/MAX
+25°C
0 to 70°C -40 to 85°C
UNITS
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vo = 1.0Vpp
Vo = 4.0Vpp
-0.1dB bandwidth
Vo = 1.0Vpp
gain peaking
<200MHz, Vo = 1.0Vpp
gain rolloff
<30MHz, Vo = 1.0Vpp
linear phase deviation
<30MHz, Vo = 1.0Vpp
differential gain
NTSC, RL=150Ω
differential phase
NTSC, RL=150Ω
90
49
17
0
0.2
0.2
0.15
0.02
75
43
12
0.5
0.5
0.4
0.4
0.06
65
40
10
0.9
0.7
0.5
–
–
65
38
10
1.0
0.7
0.5
–
–
MHz
MHz
MHz
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
6.2
17
10
290
6.9
19
16
250
7.3
35
18
220
7.7
55
18
200
ns
ns
%
V/µs
-74
-87
-67
-86
-93
-63
-70
-80
-61
-82
-88
-59
-67
-77
-59
-79
-85
-56
-67
-77
-59
-79
-85
-56
dBc
dBc
dBc
dBc
dBc
dBc
3.4
6.3
8.7
-80
4.4
8.2
11.3
–
4.9
9.0
12.4
–
4.9
9.0
12.4
–
nV/√Hz
pA/√Hz
pA/√Hz
dB
3
80
5
40
±0.3
1000
48
48
1.6
30
–
12
–
±1.5
±20%
45
46
1.9
35
–
16
–
±2.0
±26%
43
44
2.0
35
–
17
–
±2.0
±30%
43
44
2.0
mV
µV/˚C
µA
nA/˚C
%
Ω
dB
dB
mA
0.52
1.9
±4.2
±3.8
±4.0
130
400
0.38
2.85
±4.1
±3.6
±3.8
100
600
0.34
2.85
±4.1
±3.6
±3.8
80
600
0.34
2.85
±4.0
±3.5
±3.7
50
600
MΩ
pF
V
V
V
mA
mΩ
2V step
2V step
2V step
2V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
3rd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz; RL = 1kΩ
2Vpp, 5MHz
equivalent input noise
voltage (eni)
>1MHz
non-inverting current (ibn)
>1MHz
inverting current (ibi)
>1MHz
crosstalk (input referred)
10MHz, 1Vpp
STATIC DC PERFORMANCE
output offset voltage
average drift
input bias current (non-inverting)
average drift
gain accuracy
internal resistors (Rf, Rg)
power supply rejection ratio
common-mode rejection ratio
supply current (per amplifier)
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance (non-inverting)
input capacitance (non-inverting)
common-mode input range
output voltage range
RL = 100Ω
output voltage range
RL = ∞
output current
output resistance, closed loop
DC
Notes
Model
CLC5612IN
CLC5612IM
CLC5612IMX
Package Thermal Resistance
Package
B
Ordering Information
B) The short circuit current can exceed the maximum safe
output current.
Plastic (IN)
Surface Mount (IM)
NOTES
θJC
θJA
65°C/W
50°C/W
130°C/W
145°C/W
3
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Description
8-pin PDIP
8-pin SOIC
8-pin SOIC tape and reel
http://www.national.com
+5V Typical Performance (A
= +2, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified)
v
Frequency Response vs. RL
Non-Inverting Frequency Response
Gain Flatness & Linear Phase
-90
Av = +2
-180
-270
Phase
0
-90
RL = 25Ω
-180
RL = 100Ω
-270
0.1
Phase
0
-0.1
-0.2
-450
-450
10M
0.2
Gain
-360
-360
1M
0.3
Magnitude (0.1dB/div)
0
RL = 1kΩ
Gain
1M
100M
10M
-0.3
100M
10
0
Frequency (Hz)
Frequency (Hz)
Frequency Response vs. Vo (Av = 2)
20
30
Frequency (MHz)
Frequency Response vs. Vo (Av = -1)
Frequency Response vs. Vo (Av = 1)
Vo = 1Vpp
Vo = 0.1Vpp
Vo = 1Vpp
Magnitude (1dB/div)
Magnitude (1dB/div)
Vo = 1Vpp
Vo = 2Vpp
Vo = 2.5Vpp
1M
10M
Vo = 2Vpp
Vo = 2.5Vpp
1M
100M
10M
Frequency (Hz)
1M
100M
10M
100M
Frequency (Hz)
Equivalent Input Noise
PSRR & CMRR
2nd & 3rd Harmonic Distortion
3.6
15
-50
Vo = 2Vpp
PSRR
40
30
20
10
Inverting Current 10.8pA/√Hz
3.4
11
3.3
Non-Inverting Current 7.6pA/√Hz
7
3.2
Voltage 3.1nV/√Hz
3.1
3.0
0
1k
10k
100k
1M
10M
3
10k
100M
100k
1M
-70
2nd
RL = 1kΩ
-80
2nd
RL = 100Ω
-90
3rd
RL = 100Ω
-100
10M
1M
10M
Frequency (Hz)
Frequency (Hz)
2nd & 3rd Harmonic Distortion, RL = 25Ω
Frequency (Hz)
2nd & 3rd Harmonic Distortion, RL = 1kΩ
2nd & 3rd Harmonic Distortion, RL = 100Ω
-30
-50
-40
3rd, 10MHz
-50
Distortion (dBc)
3rd, 10MHz
-50
2nd, 10MHz
-60
3rd, 1MHz
-70
Distortion (dBc)
-40
3rd
RL = 1kΩ
-60
Distortion (dBc)
3.5
Noise Voltage (nV/√Hz)
CMRR
50
Noise Current (pA/√Hz)
PSRR & CMRR (dB)
Vo = 2Vpp
Vo = 2.5Vpp
Frequency (Hz)
60
Distortion (dBc)
Magnitude (1dB/div)
Vo = 0.1Vpp
Vo = 0.1Vpp
Phase (deg)
Av = -1
Phase
Vo = 0.5Vpp
Magnitude (1dB/div)
Gain
Phase (deg)
Vo = 0.5Vpp
Phase (deg)
Normalized Magnitude (1dB/div)
0.4
Av = +1
-60
2nd, 10MHz
-70
2nd, 1MHz
-80
-60
3rd, 10MHz
-70
2nd, 10MHz
-80
2nd, 1MHz
-90
3rd, 1MHz
2nd, 1MHz
3rd, 1MHz
-80
-90
0
0.5
1
1.5
2
2.5
-100
0
Output Amplitude (Vpp)
0.5
1
1.5
2
0
2.5
0
Offset Voltage VIO (mV)
Output Resistance (Ω)
10
1
0.1
-0.1
1
0.5
-0.2
VIO
0
-0.3
IBN
-0.5
-0.4
-1
-0.5
-1.5
10k
100k
1M
10M
4
100M
-0.6
-60
-40
-20
0
20
40
Temperature (°C)
60
80
100
IBN (µA)
Output Voltage (0.02V/div)
2.5
VCC = ±5V
Frequency (Hz)
http://www.national.com
2
IBN & VIO vs. Temperature
0.01
Time (10ns/div)
1.5
1.5
100
Small Signal
1
Output Amplitude (Vpp)
Closed Loop Output Resistance
Large & Small Signal Pulse Response
Large Signal
0.5
Output Amplitude (Vpp)
±5V Typical Performance (A
= +2, RL = 100Ω, VCC = ± 5V, unless specified)
v
Frequency Response vs. RL
Frequency Response
Gain Flatness & Linear Phase
0
-45
-90
-135
Av = +2
Phase
0
-90
RL = 25Ω
-225
100M
1M
-0.2
-0.4
Phase
-0.6
-0.8
-1.0
-450
100M
10M
-1.2
0
10
5
Frequency (Hz)
Frequency Response vs. Vo (Av = 2)
Vo = 2Vpp
10M
Vo = 2Vpp
1M
100M
Vo = 0.1Vpp
10M
Vo = 5Vpp
Vo = 2Vpp
1M
100M
10M
Frequency (Hz)
Large & Small Signal Pulse Response
Differential Gain & Phase
2nd & 3rd Harmonic Distortion vs. Frequency
0.2
0
0.1
Gain (%)
0.05
-0.3
0
-0.4
-0.05
Phase Pos Sync
-0.5
-0.6
-0.1
Vo = 2Vpp
-0.7
-0.2
2
3
-70
2nd
RL = 100Ω
-80
2nd
RL = 1kΩ
-90
3rd
RL = 1kΩ
-100
4
1
10
Number of 150 Ω Loads
2nd & 3rd Harmonic Distortion, RL = 25Ω
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-40
-50
-50
Distortion (dBc)
3rd, 10MHz
-50
2nd, 10MHz
-60
3rd, 1MHz
-70
3rd, 10MHz
-60
3rd, 10MHz
Distortion (dBc)
-40
Distortion (dBc)
Frequency (MHz)
2nd & 3rd Harmonic Distortion, RL = 100Ω
-30
3rd
RL = 100Ω
-60
-0.15
Gain Neg Sync
1
Phase (deg)
Phase Neg Sync
-0.2
Time (20ns/div)
-50
0.15
Gain Pos Sync
-0.1
Small Signal
100M
Frequency (Hz)
0.1
Large Signal
30
Vo = 1Vpp
Vo = 5Vpp
Frequency (Hz)
25
Frequency Response vs. Vo (Av = -1)
Magnitude (1dB/div)
Magnitude (1dB/div)
Vo = 5Vpp
20
Vo = 0.1Vpp
Vo = 1Vpp
Vo = 1Vpp
15
Frequency (MHz)
Frequency Response vs. Vo (Av = 1)
Vo = 0.1Vpp
Output Voltage (0.5V/div)
Gain
-360
Frequency (Hz)
Magnitude (1dB/div)
-270
-180
10M
1M
-180
Distortion Level (dBc)
1M
RL = 1kΩ
RL = 100Ω
0
Phase (deg)
Phase
Gain
Magnitude (0.1dB/div)
Gain
Vo = 1.0Vpp
Magnitude (1dB/div)
Av = +1
Av = -1
Phase (deg)
Phase (deg)
Normalized Magnitude (1dB/div)
0.2
Vo = 1.0Vpp
-60
2nd, 10MHz
-70
-70
2nd, 10MHz
-80
2nd, 1MHz
-90
3rd, 1MHz
3rd, 1MHz
-80
-100
2nd, 1MHz
2nd, 1MHz
-80
-90
0
1
2
3
4
5
-110
0
Output Amplitude (Vpp)
1
1.5
2
2.5
0.15
0.1
0
-0.05
-0.1
0.1
0.05
0
-0.05
-0.1
-0.15
-0.15
10
100
Time (ns)
1000
10000
4
5
9
1
8
0
7
-1
IBN
6
-2
VOS
5
-3
4
-0.2
-0.2
3
1µ
10µ
100µ
1m
Time (s)
5
10m
100m
IBN (µA)
0.05
2
IBN & VOS vs. Temperature
Offset Voltage VOS(mV)
0.15
Vo (% Output Step)
0.2
1
Output Amplitude (Vpp)
Long Term Settling Time
0.2
1
0
Output Amplitude (Vpp)
Short Term Settling Time
Vo (% Output Step)
0.5
-4
-60
-20
20
60
100
140
Temperature (°C)
http://www.national.com
±5V Typical Channel Matching Performance (A
v
= +2, RL = 100Ω, VCC = ± 5V, unless specified)
Input Referred Crosstalk
Channel Matching
Pulse Crosstalk
-20
Active Output
Channel
Channel 1
Active Channel
Amplitude (0.2V/div)
Channel 2
Magnitude (dB)
-40
-60
-80
-100
Inactive Output
Channel
Inactive Channel
Amplitude (20mV/div)
Magnitude (0.5dB/div)
Vo = 1Vpp
-120
1M
10M
Frequency (Hz)
100M
10M
1M
Time (10ns/div)
100M
Frequency (Hz)
CLC5612 Operation
The CLC5612 is a current feedback buffer built in an
advanced complementary bipolar process.
The
CLC5612 operates from a single 5V supply or dual ±5V
supplies. Operating from a single 5V supply, the
CLC5612 has the following features:
■
■
■
■
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
Vo
=
Vin
Gains of +1, -1, and 2V/V are achievable without
external resistors
Provides 100mA of output current while
consuming only 7.5mW of power
Offers low -79/-81dBc 2nd and 3rd harmonic
distortion
Provides BW > 50MHz and 1MHz distortion
< -75dBc at Vo = 2Vpp
■
■
■
■
Current Feedback Amplifiers
Some of the key features of current feedback technology are:
■
■
■
Av is the closed loop DC voltage gain
Rf is the feedback resistor
Z(jω) is the CLC5612’s open loop
transimpedance gain
Z( jω )
is the loop gain
Rf
The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rf and Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing Rf
has the following affects:
If gains other than +1, -1, or +2V/V are required, then the
CLC5602 can be used. The CLC5602 is a current feedback amplifier with near identical performance and allows
for external feedback and gain setting resistors.
■
Equation 1
where:
The CLC5612 performance is further enhanced in ±5V
supply applications as indicated in the ±5V Electrical
Characteristics table and ±5V Typical Performance plots.
■
Av
Rf
1+
Z(jω )
■
Independence of AC bandwidth and voltage gain
Inherently stable at unity gain
Adjustable frequency response with feedback resistor
High slew rate
Fast settling
■
■
■
■
Decreases loop gain
Decreases bandwidth
Reduces gain peaking
Lowers pulse response overshoot
Affects frequency response phase linearity
CLC5612 Design Information
Closed Loop Gain Selection
The CLC5612 is a current feedback op amp with
Rf = Rg = 1kΩ on chip (in the package). Select from
three closed loop gains without using any external gain
or feedback resistors. Implement gains of +2, +1,
and -1V/V by connecting pins 2 and 3 (or 5 and 6) as
described in the chart below.
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Gain
Av
-1V/V
+1V/V
+2V/V
6
Input Connections
Non-Inverting (pins 3,5) Inverting (pins 2,6)
ground
input signal
input signal
input signal
NC (open)
ground
The gain accuracy of the CLC5612 is excellent and
stable over temperature change. The internal gain
setting resistors, Rf and Rg are diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (Rf/Rg) remains constant. If an external resistor is
used in series with Rg, gain accuracy over temperature
will suffer.
VCC
6.8µF
+
Note: Rt, RL and Rg are tied to Vcm for minimum power
consumption and maximum output swing.
Channel 2 not shown.
Vo
0.1µF
8
1
1kΩ
RL
Vcm
1kΩ
2
-
7
+
Vcm Vin
3
1kΩ
1kΩ
6
-
Rt
4
5
+
Single Supply Operation (VCC = +5V, VEE = GND)
The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with
a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the
output voltages are specified.
CLC5612
Vcm
Figure 3: DC Coupled, Av = +2V/V Configuration
AC Coupled Single Supply Operation
Figures 4, 5, and 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5612 is typically +0.8V to
+4.2V. The typical output range with RL=100Ω is +1.0V
to +4.0V.
VCC
6.8µF
+
Note: Channel 2 not shown.
For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.
Vo
VCC
Vin
3
1kΩ
6
-
4
5
Vo = − Vin + 2.5
Low frequency cutoff =
where Rg = 1kΩ.
1
,
2πR gCC
Figure 4: AC Coupled, Av = -1V/V Configuration
+
The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to VCC ÷ 2
= 2.5V (For VCC = +5V).
0.1µF
8
1kΩ
1kΩ
+
2
7
CLC5612
1kΩ
Vin
+
R
6.8µF
1
RL
1kΩ
R
VCC
Vo
1kΩ
2
DC Coupled Single Supply Operation
Figures 1, 2, and 3 on the following page, show the
recommended configurations for input signals that
remain above 0.8V DC.
Note: Rb provides DC bias for the non-inverting input.
Rb, RL and Rt are tied to Vcm for minimum power
consumption and maximum output swing.
Channel 2 not shown.
0.1µF
8
1
CC
-
7
+
Rt
3
1kΩ
VCC
6
1kΩ
6.8µF
-
Vcm
Vcm
5
CLC5612
Vo
VCC
Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ.
Vin
VCC
+
0.1µF
2
1kΩ
-
-
7
+
3
1kΩ
1kΩ
6
4
5
Vo = Vin + 2.5
Low frequency cutoff =
R
where Rin =
2
1kΩ
RL
1kΩ
CLC5612
8
1
1kΩ
R
R
6.8µF
Vo
CC
0.1µF
8
1
2
Figure 1: DC Coupled, Av = -1V/V Configuration
Note: Rt and RL are tied to Vcm for minimum power
consumption and maximum output swing.
Channel 2 not shown.
+
Note: Channel 2 not shown.
-
4
+
Rb
+
Vcm
1
,
2πRinCC
R >> R source
7
+
Vcm Vin
3
1kΩ
1kΩ
Figure 5: AC Coupled, Av = +1V/V Configuration
6
-
Vcm
4
+
Rt
5
CLC5612
Figure 2: DC Coupled, Av = +1V/V Configuration
7
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VCC
VCC
6.8µF
Vo
VCC
Vo
2
1kΩ
1kΩ
-
7
1kΩ
2
-
+
3
1kΩ
Vin
6
1kΩ
3
1kΩ
-
4
7
+
1kΩ
6
-
R
0.1µF
8
1
1kΩ
Rt
5
+
CLC5612
4
Vo = 2Vin + 2.5
Low frequency cutoff =
where Rin =
R
2
0.1µF
1
,
2πRinCC
R >> R source
5
+
Vin
+
0.1µF
8
1
R C
CC
6.8µF
+
Note: Channel 2 not shown.
CLC5612
Note: Channel 2 not shown.
+
6.8µF
VEE
Figure 6: AC Coupled, Av = +2V/V Configuration
Figure 9: Dual Supply, Av = +2V/V Configuration
Dual Supply Operation
The CLC5612 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 7, 8 and 9.
Load Termination
The CLC5612 can source and sink near equal amounts
of current. For optimum performance, the load should be
tied to Vcm.
VCC
6.8µF
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC5612 will
improve stability and settling performance. The
Frequency Response vs. CL plot, shown below in
Figure 10, gives the recommended series resistance
value for optimum flatness at various capacitive loads.
+
Vo
0.1µF
8
1
1kΩ
Vin
1kΩ
2
-
7
+
Rt
3
1kΩ
1kΩ
6
-
4
5
+
0.1µF
CLC5612
y
Note: Rb provides DC bias for the
non-inverting input. Select Rt to
yield desired Rin = Rt||1kΩ.
Channel 2 not shown.
+
6.8µF
Vo = 1Vpp
Magnitude (1dB/div)
Rb
VEE
Figure 7: Dual Supply, Av = -1V/V Configuration
VCC
CL = 10pF
Rs = 49.9Ω
CL = 100pF
Rs = 17.4Ω
CL = 1000pF
Rs = 6.7Ω
+
Rs
-
1k
6.8µF
CL
1k
1k
+
1M
Vo
8
1
1kΩ
-
7
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 11 shows typical inverting and non-inverting
circuit configurations for matching transmission lines.
+
Vin
3
1kΩ
1kΩ
6
-
Rt
4
+
0.1µF
5
CLC5612
Note: Channel 2 not shown.
+
6.8µF
VEE
Figure 8: Dual Supply, Av = +1V/V Configuration
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100M
Figure 10: Frequency Response vs. CL
1kΩ
2
10M
Frequency (Hz)
0.1µF
8
Non-inverting gain applications:
■
■
Connect pin 2 as indicated in the table in the
Closed Loop Gain Selection section.
Make R1, R2, R6, and R7 equal to Zo.
Use R3 to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.
IM
0.8
Power (W)
■
1.0
IN
0.6
0.4
0.2
Inverting gain applications:
■
■
■
0
Connect R3 directly to ground.
Make the resistors R4, R6, and R7 equal to Zo.
Make R5 II Rg = Zo.
-40 -20
R4
Z0
8
1
Z0
C6
1kΩ
R5
Figure 12: Power Derating Curve
Z0
3
R3
R2
-
Vo
R7
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
7
+
4
V2 +-
1kΩ
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides
evaluation boards for the CLC5612 (CLC730038-DIP,
CLC730036-SOIC) and suggests their use as a guide for
high frequency layout and as an aid for device testing and
characterization.
1kΩ
1kΩ
6
-
R1
2
+
V1
+
-
5
■
CLC5612
Note: Channel 2 not shown.
■
Figure 11: Transmission Line Matching
■
Power Dissipation
Follow these steps to determine the power consumption
of the CLC5612:
■
1. Calculate the quiescent (no-load) power:
Pamp = ICC (VCC - VEE)
2. Calculate the RMS power at the output stage:
Po = (VCC - Vload) (Iload), where Vload and Iload
are the RMS voltage and current across the
external load.
3. Calculate the total RMS power:
Pt = Pamp + Po
■
■
Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
Place the 6.8µF capacitors within 0.75 inches
of the power pins.
Place the 0.1µF capacitors less than 0.1 inches
from the power pins.
Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.
Minimize all trace lengths to reduce series
inductances.
Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.
Evaluation Board Information
A data sheet is available for the CLC730038/ CLC730036
evaluation boards. The evaluation board data sheets provide:
The maximum power that the DIP and SOIC,
packages can dissipate at a given temperature is
illustrated in Figure 12. The power derating curve for
any CLC5612 package can be derived by utilizing the
following equation:
where
20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6 to match the output transmission line over a
greater frequency range. C6 compensates for the increase
of the amplifier’s output impedance with frequency.
R6
0
■
■
■
Evaluation board schematics
Evaluation board layouts
General information about the boards
The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.
(175° − Tamb )
θ JA
Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient,
for a given package (°C/W)
9
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The readme file that accompanies the diskette lists
released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE
Models for Comlinear’s Op Amps, contains schematics
and a reproduction of the readme file.
Special Evaluation Board
Considerations for the CLC5612
To optimize off-isolation of the CLC5612, cut the Rf trace
on both the CLC730038 and the CLC730036 evaluation
boards. This cut minimizes capacitive feedthrough
between the input and the output. Figure 13 shows where
to cut both evaluation boards for improved off-isolation.
Application Circuits
730036 Bottom
Single Supply Cable Driver
Figure 14 below shows the CLC5612 driving 10m of 75Ω
coaxial cable. The CLC5612 is set for a gain of +2V/V
to compensate for the divide-by-two voltage drop at
Vo. The response after 10m of cable is illustrated in
Figure 15.
Vo
10m of 75Ω
Coaxial Cable
+5V
75Ω
6.8µF
+
CLC730038
REV C
0.1µF
75Ω
+5V
8
1
5kΩ
Vin
0.1µF
0.1µF
0.1µF
1kΩ
2
1kΩ
-
7
+
3
1kΩ
1kΩ
6
-
5kΩ
4
+
Cut traces here
5
CLC5612
NOTE: Channel 2 not shown
730036 Top
+Vcc
+
C3
C4
+
-Vcc
Figure 14: Single Supply Cable Driver
OUT2
ROUT2
GND
RG2 IN2
Vin = 10MHz, 0.5Vpp
RF2
OUT1
C2
ROUT1
RF1
(970) 226-0500
100mV/div
C1
RIN2
RG1 RIN1
IN1
20ns/div
Figure 15: Response After 10m of Cable
Cut traces here
Differential Line Driver With Load
Impedance Conversion
The circuit shown in the Typical Application schematic
on the front page and in Figure 16, operates as a
differential line driver. The transformer converts the load
impedance to a value that best matches the CLC5612’s
output capabilities. The single-ended input signal is
converted to a differential signal by the CLC5612. The
line’s characteristic impedance is matched at both the
input and the output. The schematic shows Unshielded
Twisted Pair for the transmission line; other types of lines
can also be driven.
Figure 13: Evaluation Board Changes
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for
Comlinear’s monolithic amplifiers that:
■
■
■
Support Berkeley SPICE 2G and its many derivatives
Reproduce typical DC, AC, Transient, and Noise
performance
Support room temperature simulations
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10
Rm/2
Zo
Req
Vd/2
8
1
1kΩ
2
1kΩ
-
7
+
Vin
3
1kΩ
1kΩ
Select the transformer so that it loads the line with a
value very near Zo over frequency range. The output
impedance of the CLC5612 also affects the match. With
an ideal transformer we obtain:
Io
1:n
RL
UTP
Rm/2
-Vd/2
Return Loss = −20 ⋅ log10
-
4
5
+
Rt
CLC5612
n2 ⋅ Z o(5612) ( jω )
,dB
Zo
6
Rt2
Note: Supplies and bypassing not shown.
where Zo(5612)(jω) is the output impedance of the
CLC5612 and |Zo(5612)(jω)| << Rm.
Figure 16: Differential Line Driver with
Load Impedance Conversion
The load voltage and current will fall in the ranges:
Set up the CLC5612 as a difference amplifier:
■
■
Set the Channel 1 amplifier to a gain of +1V/V
Set the Channel 2 amplifier to a gain of -1V/V
Make the best use of the CLC5612’s output drive
capability as follows:
Rm + Req =
Vo
≤ n ⋅ Vmax
Io ≤
Imax
n
The CLC5612’s high output drive current and low
distortion make it a good choice for this application.
2 ⋅ Vmax
Imax
Differential Input/Differential Output Amplifier
Figure 17 below illustrates a differential input/differential
output configuration. The bypass capacitors are the only
external components required.
where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the
maximum Output Current.
-5V
Vin2
Match the line’s characteristic impedance:
0.1µF
RL = Z o
CLC5612
1kΩ
1kΩ
6.8µF
Vout2
Rm = Req
Vin1
RL
n=
Req
6.8µF
+5V
1kΩ
0.1µF
1kΩ
Vout1
Vout1 – Vout2 = (Vin1 – Vin2) x 2
Figure 17: Differential Input/Differential
Output Amplifier
11
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CLC5612
Dual, High Output, Programmable Gain Buffer
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National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
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sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
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