N CLC405 Low-Cost, Low-Power, 110MHz Op Amp with Disable General Description Features The CLC405 is a low-cost, wideband (110MHz) op amp featuring a TTL-compatible disable which quickly switches off in 18ns and back on in 40ns. While disabled, the CLC405 has a very high input/output impedance and its total power consumption drops to a mere 8mW. When enabled, the CLC405 consumes only 35mW and can source or sink an output current of 60mA. These features make the CLC405 a versatile, high-speed solution for demanding applications that are sensitive to both power and cost. ■ Utilizing National’s proven architectures, this current feedback amplifier surpasses the performance of alternative solutions and sets new standards for low power at a low price. This powerconserving op amp achieves low distortion with -72dBc and -70dBc for second and third harmonics respectively. Many high source impedance applications will benefit from the CLC405’s 6MΩ input impedance. And finally, designers will have a bipolar part with an exceptionally low 100nA non-inverting bias current. ■ ■ ■ ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ ■ ■ ■ With 0.1dB flatness to 50MHz and low differential gain and phase errors, the CLC405 is an ideal part for professional video processing and distribution. However, the 110MHz -3dB bandwidth (Av = +2) coupled with a 350V/µs slew rate also make the CLC405 a perfect choice in cost-sensitive applications such as video monitors, fax machines, copiers, and CATV systems. Low-cost Very low input bias current: 100nA High input impedance: 6MΩ 110MHz -3dB bandwidth (Av = +2) Low power: Icc = 3.5mA Ultra-fast enable/disable times High output current: 60mA Desktop video systems Multiplexers Video distribution Flash A/D driver High-speed switch/driver High-source impedance applications Peak detector circuits Professional video processing High resolution monitors Frequency Response (Av = +2V/V) CLC405 Low-Cost, Low-Power, 110MHz Op Amp with Disable June 1999 Typical Application Wideband Digitally Controlled Programmable Gain Amplifier Pinout DIP & SOIC © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC405 Electrical Characteristics (AV = +2, Rf = 348Ω: Vcc = + 5V, RL = 100Ω unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC405AJ TYP +25˚C MIN/MAX RATINGS +25˚C 0 to 70˚C -40 to 85˚C UNITS FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 1.0Vpp Vout < 5.0Vpp -3dB bandwidth AV = +1 Vout < 0.5Vpp (Rf = 2K) ±0.1dB bandwidth Vout < 1.0Vpp gain flatness Vout < 1.0Vpp peaking DC to 200MHz rolloff <30MHz linear phase deviation <20MHz differential gain NTSC, RL=150Ω NTSC, RL=150Ω (Note 2) differential phase NTSC, RL=150Ω NTSC, RL=150Ω (Note 2) 110 42 135 50 75 31 0 0.05 0.3 0.01 0.01 0.25 0.08 TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% overshoot slew rate AV = +2 AV = -1 5 18 3 350 650 7.5 27 12 260 8.2 36 12 225 8.4 39 12 215 ns ns % V/µs V/µs -72/-52 -70/-57 -46 -50 -45 -47 -44 -46 dBc dBc 5 12 3 6.3 15 3.8 6.6 16 4 6.7 17 4.2 nV/√Hz pA/√Hz pA/√Hz 1 30 100 3 1 17 52 50 3.5 0.8 5 50 900 7 47 45 4.0 0.9 1600 8 7 40 46 44 4.1 0.95 8 50 2800 11 10 45 45 43 4.4 1 mV µV/˚C nA nA/˚C µA nA/˚C dB dB mA mA 40 18 59 55 26 55 2 0.8 58 30 55 2 0.8 58 32 55 2 0.8 ns ns dB V V 6 182 1 ±2.2 + 3.5,-2.8 +4.0,-3.3 40 0.06 3 2.4 1 2 1.8 +3.1,-2.7 +3.9,-3.2 40 0.2 2 1.7 +2.9,-2.6 +3.8,-3.1 38 0.25 2 1.5 +2.4,-1.6 +3.7,-2.8 20 0.4 MΩ Ω pF V V V mA Ω 2V step 2V step 2V step 2V step 1V step DISTORTION AND NOISE RESPONSE 2Vpp, 1MHz/10MHz 2nd harmonic distortion 3rd harmonic distortion 2Vpp, 1MHz/10MHz equivalent input noise non-inverting voltage >1MHz inverting current >1MHz non-inverting current >1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input bias current average drift power supply rejection ratio common-mode rejection ratio supply current disabled DC DC RL= ∞ RL= ∞ SWITCHING PERFORMANCE turn on time turn off time off isolation high input voltage low input voltage to >50dB attn. @ 10MHz 10MHz VIH VIL non-inverting inverting MISCELLANEOUS PERFORMANCE input resistance non-inverting input resistance inverting input capacitance non-inverting common mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop 50 27 45 26 MHz MHz MHz MHz 0.6 0.3 0.6 0.03 0.8 0.4 0.7 0.04 1.0 0.5 0.7 0.05 0.4 0.5 0.55 dB dB deg % % deg deg 15 5 NOTES 1 2 2 B B A A A A A Recommended gain range +1 to +40V/V Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Transitor count Absolute Maximum Ratings supply voltage Iout is short circuit protected to ground common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) http://www.national.com 68 Notes ±7V 1) At temps < 0˚C, spec is guaranteed for RL = 500Ω. 2) An 825Ω pull-down resistor is connected between Vo and -Vcc. A) J-level: spec is 100% tested at +25˚C B) Guaranteed at 10MHz. ±Vcc +150˚C -65˚C to +150˚C +300˚C 2 CLC405 Typical Performance Characteristics (AV = +2, Rf = 348Ω: Vcc = + 5V, RL = 100Ω unless specified) Non-Inverting Frequency Response -45 AV+4 -90 AV+10 -135 Magnitude (1dB/div) 0 AV+1 AV-1 Rf =348 AV-10 Rf =500 AV-2 Phase -180 AV-1 -225 AV-4 -270 AV-10 -315 -180 1 10 RL=1k Gain AV-2 Rf =200 RL=100 RL=50 Phase 0 RL=1k -45 RL=100 -90 RL=50 -135 -360 1 100 10 Frequency (MHz) Frequency Response vs. Vout Phase (deg) AV+2 Phase Frequency Response For Various RLs Phase (deg) AV+4 Rf =200 AV+10 Rf =100 AV-4 Rf =200 Gain Phase (deg) Magnitude (1dB/div) Gain Inverting Frequency Response AV+1 Rf =2k Magnitude (1dB/div) AV+2 Rf =348 -180 100 1 10 100 Frequency (MHz) Frequency (MHz) Frequency Response vs. Capacitive Load Gain Flatness & Linear Phase Deviation Vo=1Vpp -45 Vo=0.2Vpp -90 Vo=2Vpp -135 Vo=1Vpp Magnitude (1dB/div) 0 Vo=5Vpp CL=100pF Rs =30 CL= .001µfd Rs =10 + 10 Rs - CL 348Ω -180 100 1 0 100 15 Open Loop Transimpedance Gain, Z(s) 6.0 110 20 log [|Vo/|i/1Ω] 130 5.0 4.0 100 160 Gain 90 120 Phase 70 80 - CLC405 Ii 50 3.0 Equivalent Input Noise 200 Vo 40 + 100Ω 100 Inverting Current = 12pA/√Hz 10 10 Voltage = 5nV/√Hz Non-Inverting Current = 3pA/√Hz Noise Current (pA/√Hz) 7.0 30 Frequency (MHz) Phase (deg) 1 30 2.0 0 100 200 300 400 0 1k 500 10k 10M 1M 100k 1 100M 100 2nd Rl = 100 3rd Rl = 100 -80 2nd Rl = 1k + 10MHz 5MHz -55 + 50Ω - -65 Pout 50Ω 1MHz -75 -90 1 -55 5MHz -65 1MHz -75 10dBm = 2Vpp 0dBm = .63Vpp 0 10 -10 0 Output Power (dBm) Frequency (MHz) Output Resistance vs. Frequency Differential Gain and Phase 0.20 0 1.00 Vin Gain (dB) Forward 10 -10 -40 Reverse -60 -30 -80 -50 -100 + 75Ω 0.15 75Ω CLC405 - 825Ω 348Ω Vout 75Ω 0.75 -Vcc 348Ω Phase 0.10 0.50 Gain 0.05 0.25 Differential Phase (deg) -20 30 10 Output Power (dBm) Forward and Reverse Gain During Disable 50 500KHz -85 -10 10 10MHz 50Ω 500KHz 3rd Rl = 1k -85 0.1 Pout 50Ω - Distortion (dBc) Distortion (dBc) -60 10M -45 10dBm = 2Vpp 0dBm = .63Vpp -50 1M 100k 3rd Harmonic Distortion vs. Pout -45 Vo = 2Vpp -70 10k Frequency (Hz) 2nd Harmonic Distortion vs. Pout 2nd & 3rd Harmonic Distortion -40 1k Frequency (Hz) Load (Ω) Differential Gain (%) Maximum Output Voltage (Vpp) Phase Frequency (MHz) Maximum Output Voltage vs. RL Distortion (dBc) 1k 10 Frequency (MHz) Output Resistance (20log Zout) Gain 348Ω Noise Voltage (nV/√Hz) 1 CL=10pF Rs =100 LPD (0.5o/div) Phase Phase (deg) Magnitude (1dB/div) Vo=0.2Vpp Vo=5Vpp Magnitude (0.1dB/div) Vo=2Vpp Gain f = 3.58MHz 1 10 Frequency (MHz) 100 0 1 10 100 Frequency (MHz) 3 0 1 2 3 4 Number of 150Ω Loads http://www.national.com CLC405 Typical Performance Characteristics (AV = +2, Rf = 348Ω: Vcc = + 5V, RL = 100Ω unless specified) Large Signal Pulse Response 2.0 AV+2 1.0 Output Voltage Output Voltage AV+1 0.10 0.00 -0.10 0.0 -1.0 AV-1 -0.20 AV-2 -2.0 Time (5ns/div) Settling Time vs. Capacitive Load 50 100 + Rs CLC405 - 40 CL 348Ω 1k 80 Ts 348Ω Vo = 2V step 30 60 20 40 Rs (Ω) Settling Time, Ts(ns) to 0.05% Error Small Signal Pulse Response 0.20 Rs 10 20 0 Time (5ns/div) 10 0 1000 100 CL (pF) Short Term Settling Time 4.0 60 Vout = 2Vstep 0.1 0.0 -0.1 50 Offet Voltage, VIO (mV) PSRR/CMRR (dB) PSRR CMRR 40 30 20 0 20 40 60 Time (ns) 80 100 IBN 3.0 0 IBI 2.0 -1.0 1.0 -2.0 VIO 0 -3.0 -1.0 10 -0.2 1.0 10k 100k 10M 1M 100M IBI, IBN (µA) Vout (% Final Value) IBI, IBN, VIO vs. Temperature PSRR and CMRR 0.2 -4.0 -60 -20 20 60 100 140 Temperature (oC) Frequency (Hz) CLC405 OPERATION Feedback Resistor The feedback resistor, Rf, determines the loop gain and frequency response for a current feedback amplifier. Unless otherwise stated, the performance plots and data sheet specify CLC405 operation with Rf of 348Ω at a gain of +2V/V. Optimize frequency response for different gains by changing Rf. Decrease Rf to peak frequency response and extend bandwidth. Increase Rf to roll off of the frequency response and decrease bandwidth. Use a 2kΩ Rf for unity gain, voltage follower circuits. Operate the CLC405 without connecting pin 8. An internal 20kΩ pull-up resistor guarantees the CLC405 is enabled when pin 8 is floating. Enable/Disable Operation for Single or Unbalanced Supply Operation Supply Mid-Point Use application note OA-13 to optimize your Rf selection. The equations in this note are a good starting point for selecting Rf. The value for the inverting input impedance for OA-13 is approximately 182Ω. Vcc -Vee 2 20kΩ Bias Circuitry Q2 20kΩ Pull-up Resistor Q1 Pin 8 Disable 20kΩ I Tail Enable/Disable Operation Using ± 5V Supplies The CLC405 has a TTL & CMOS logic compatible disable function. Apply a logic low (i.e. < 0.8V) to pin 8, and the CLC405 is guaranteed disabled across its temperature range. Apply a logic high to pin 8, (i.e. > 2.0V) and the CLC405 is guaranteed enabled. Voltage, not current, at pin 8 determines the enable/disable state of the CLC405. Disable the CLC405 and its inputs and output become high impedances. While disabled, the CLC405’s quiescent power drops to 8mW. Use the CLC405’s disable to create analog switches or multiplexers. Implement a single analog switch with one CLC405 positioned between an input and output. Create an analog multiplexer with several CLC405s. Tie the outputs together and put a different signal on each CLC405 input. http://www.national.com Pin 7 +Vcc Pin 4 -Vee CLC405 NOTE: Pins 4, 7, 8 are external Figure 1 Figure 1 illustrates the internal enable/disable operation of the CLC405. When pin 8 is left floating or is tied to +Vcc, Q1 is on and pulls tail current through the CLC405 bias circuitry. When pin 8 is less than 0.8V above the supply midpoint, Q1 stops tail current from flowing in the CLC405 circuitry. The CLC405 is now disabled. Disable Limitations The feedback resistor, Rf, limits off isolation in inverting gain configurations. Do not apply voltages greater than +Vcc or less than -Vee to pin 8 or any other pin. 4 Use power-supply bypassing capacitors when operating this amplifier. Choose quality 0.1µF ceramics for C1 and C2. Choose quality 6.8µF tantalum capacitors for C3 and C4. Place the 0.1µF capacitors within 0.1 inches from the power pins. Place the 6.8µF capacitors within 3/4 inches from the power pins. Input - Bias Current, Impedances, and Source Termination Considerations The CLC405 has: • a 6MΩ non-inverting input impedance. • a 100nA non-inverting input bias current. If a large source impedance application is considered, remove all parasitic capacitance around the non-inverting input and source traces. Parasitic capacitances near the input and source act as a low-pass filter and reduce bandwidth. Video Performance vs. IEX Improve the video performance of the CLC405 by drawing extra current from the amplifier output stage. Using a single external resistor as shown in Figure 3, you can adjust the differential phase. Video performance vs. IEX is illustrated below in Graph 1. This graph represents positive video performance with negative synchronization pulses. Current feedback op amps have uncorrelated input bias currents. These uncorrelated bias currents prevent source impedance matching on each input from canceling offsets. Refer to application note OA-07 of the data book to find specific circuits to correct DC offsets. Differential Gain & Phase vs. IEX Differential Gain (%) Use the CLC730013 and CLC730027 evaluation boards for the DIP and SOIC respectively. These board layouts were optimized to produce the typical performance of the CLC405 shown in the data sheet. To reduce parasitic capacitances, the ground plane was removed near pins 2, 3, and 6. To reduce series inductance, trace lengths of components and nodes were minimized. Rin 50Ω 7 6 CLC405 2 50Ω - Rg 348Ω Rout 4 0.05 0.05 0 2 Vin Rt 4 6 8 10 12 14 16 18 +5V + Rout Vout CLC405 - Rpull Rf Rg down -5V Extra I -Vcc Figure 3 The value for Rpd in Figure 3 is determined by : Rpd = at +5V supplies. 5 IEX Wideband Digital PGA As shown on the front page, the CLC405 is easily configured as a digitally controlled programmable gain amplifier. Make a PGA by configuring several amplifiers at required gains. Keep Rf near 348Ω and change Rg for each different gain. Use a TTL decoder that has enough outputs to control the selection of different gains and the buffer stage. Connect the buffer stage like the buffer of the front page. The buffer isolates each gain stage from the load and can produce a gain of zero for a gain selection of zero. Use of an inverter (7404) on the buffer disable pin to keep the buffer operational at all gains except zero. Or float the buffer disable pin for a continuous enable state. SMA Output -5V C4 6.8µfd 0.10 Graph1 Rf C2 0.1µfd 0.10 IEX in mA +5V + 348Ω 0.15 0 Insert the back matching resistor (Rout) shown in Figure 2 when driving coaxial cable or a capacitive load. Use the plot in the typical performance section labeled “Settling Time vs. Capacitive Load” to determine the optimum resistor value for Rout for different capacitive loads. This optimal resistance improves settling tim for pulse-type applications and increases stability. 3 + 0.15 0 Do not use dip sockets for the CLC405 DIP amplifiers. These sockets can peak the frequency domain response or create overshoot in the time domain response. Use flush-mount socket pins when socketing is necessary. The 730013 circuit board device holes are sized for Cambion P/N 450-2598 socket pins or their functional equivalent. SMA Input 0.20 Phase Gain Parasitics on traces degrade performance. Minimize coupling from traces to both power and ground planes. Use low inductive resistors for leaded components. C3 6.8µfd 0.20 Differential Phase (deg) Layout Considerations Whenever questions about layout arise, USE THE EVALUATION BOARD AS A TEMPLATE. C1 0.1µfd 0.25 0.25 + Figure 2 5 http://www.national.com Coaxial Cable Amplitude Equalizer Place the first zero (fz1) at some low frequency (540 khz for Graph 2). R1 & C1 produce a pole (fp1 @ 750khz) that cancels fz1. Place a second zero at a higher frequency (fz2 @ 12Mhz). R2 & C2 provide a canceling pole (of fp2 = 25Mhz). Graph 3 shows the closed loop response of the op amp equalizer with equations for the poles, zeros, and gains. Closed Loop Equalizer Frequency Response G1 = 20log (1+ Input + G2 = 20log (1+ Output CLC405 Log Magnitude Rt - Rf = 348Ω Rg C1 R1 C2 R2 RC Networks Rg 2R1 Req ) fp1 2R2 ) G2 fz2 fp1 G1 fz1 fz1 = 1 π 2R1C1 + RgC1 fp1 = 1 2π R1C1 ( fz2 = ) Req = R1llRg 1 π 2R2C2 + ReqC2 1 fp2 = 2π R2C2 ( ) Frequency (Hz) Figure 4 Graph 3 Digital Word Amplitude Equalization Note: For very-high frequency equalization, use a higher bandwidth part (i.e. CLC44X) Unequalized Amplitude (0.5V/div) CLC405 Low-Cost, Low-Power, 110MHz Op Amp with Disable Amplitude Equalization Sending signals over coaxial cable greater than 50 meters in length will attenuate high frequency signal components. Equalizers restore the attenuated components of this signal. The circuit in Figure 4, is an op amp equalizer. The RC networks peak the response of the CLC405 at higher frequencies. This peaking restores cable-attenuated frequencies. Graph 2 shows how the equalizer actually restored a digital word through 150 meters of coaxial cable. Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) CerDip Equalized θjc θjA 75˚/W 130˚/W 65˚/W 125˚/W 150˚/W 155˚/W Ordering Information Model Time (200ns/div) Temperature Range CLC405AJP CLC405AJE CLC405AIB CLC405ALC CLC405AMC CLC405A8B Graph 2 The values used to produce Graph 2 are: Rg = 348Ω C1 = 470pF C2 = 70pF R1 = 450Ω R2 = 90Ω -40˚C -40˚C -40˚C -40˚C -55˚C -55˚C to to to to to to +85˚C +85˚C +85˚C +85˚C +125˚C +125˚C Description 8-pin PDIP 8-pin SOIC 8-pin CerDIP dice dice, MIL-STD-883 8-pin CerDIP, MIL-STD-883 Contact factory for other packages and DESC SMD number. Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. 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