AVAGO ACPL-W454-060E

ACPL-P454 and ACPL-W454
High CMR High Speed Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-W454/P454 is similar to Avago Technologies
other high speed transistor output optocouplers, but with
shorter propagation delays and higher CTR. The ACPLW454/P454 also has a guaranteed propagation delay
difference (tPLH - tPHL). These features make the ACPLW454/P454 an excellent solution to IPM inverter dead time
and other switching problems.
x Package Clearance/Creepage at 8mm (ACPL-W454)
The ACPL-W454/P454 CTR, propagation delays, and CMR
are specified both for TTL load and drive conditions and for
IPM (Intelligent Power Module) load and drive conditions.
Specifications and typical performance plots for both TTL
and IPM conditions are provided for ease of application.
x High CTR: >25% at 25°C
This diode-transistor optocoupler uses an insulating layer
between the light emitting diode and an integrated photo
detector to provide electrical insulation between input
and output. Separate connections for the photodiode bias
and output transistor collector increase the speed up to a
hundred times over that of a conventional phototransistor
coupler by reducing the base-collector capacitance.
Functional Diagram
ANODE
1
6 VCC
NC 2
TRUTH TABLE
LED
VO
ON
LOW
OFF
HIGH
5 VO
CATHODE 3
4 GND
A 0.1 μF bypass capacitor between pins 4 and 6 is recommended.
Schematic
ICC
ANODE
+
V CC
1
VF
CATHODE
6
IF
IO
Ð
5
VO
3
SHIELD
4
GND
x Function Compatible with HCPL-4504
x Surface Mountable in 6-pin stretched SO6
x Short Propagation Delays for TTL and IPM Applications
x Very High Common Mode Transient Immunity: Guaranteed 15 kV/Ps at VCM = 1500 V
x Guaranteed Specifications for Common IPM Applications
x TTL Compatible
x Guaranteed AC and DC Performance Over Temperature:
0°C to 70°C
x Open Collector Output
x Safety approval
UL Recognized 3750 Vrms for 1 minute (5000 Vrms for
1 minute under ACPL-W454 devices) per UL1577
CSA Approved
IEC/EN/DIN EN 60747-5-2 Approved with VIORM = 1140
Vpeak (ACPL-W454) and VIORM = 891 Vpeak (ACPL-P454)
for Option 060.
Applications
x Inverter Circuits and Intelligent Power Module (IPM) Interfacing – Shorter propagation delays and guaranteed
(tPLH - tPHL) specifications.
x High Speed Logic Ground Isolation
- TTL/TTL, TTL/LTTL, TTL/CMOS, TTL/LSTTL
x Line Receivers
- High common mode transient immunity (>15 kV/Ps
for a TTL load/drive) and low input-output capacitance
(0.6 pF).
x Replace Pulse Transformers
- Save board space and weight
x Analog Signal Ground Isolation
- Integrated photo detector provides improved linearity
over phototransistors
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P454 and ACPL-W454 are UL Recognized with 3750 Vrms (5000 Vrms under ACPL-W454) for 1 minute per UL1577
and are approved under CSA Component Acceptance Notice #5, File CA 88324.
Option
RoHS
Compliant
Part number
Package
IEC/EN/DIN EN
60747-5-2
X
-000E
-500E
ACPL-P454
ACPL-W454
Tape
& Reel
Surface Mount
Stretched
SO-6
-060E
-560E
Quantity
100 per tube
X
X
1000 per reel
X
X
X
X
100 per tube
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P454-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN 607475-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-P454-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-W454 (Stretched SO6, 8mm Clearance)
4.580
1.27 [.050] BSG
0.38 ± 0.127
[.015 ± .005]
6.807
.268
1
6
2
5
3
4
.180
+0.254
0
+.010
- .000
Land Pattern Recommendation
12.65 [.498]
0.76
[.030]
+0.127
0
1.590 ± 0.127
[.063 ± .005]
+.005
- .000
0.45
[.018]
7°
3.180 ± 0.127
[.125 ± .005]
45°
1.91 [.075]
7°
0.20 ± 0.10
[.008 ± .004]
0.750 ± 0.250
[0.0295 ± 0.010]
11.50 ± 0.250
[.453 ± .010]
2
Dimensions in Millimeters [Inches]
Coplanarity = 0.1mm [0.004 inches]
ACPL-P454 (Stretched SO6, 7mm Clearance)
4.580
0.38 ± 0.127
[.015 ± .005]
.180
1.27 [.050] BSG
+0.254
0
Land Pattern Recommendation
+.010
10.7 [.421]
- .000
2.16 [.085]
7.62 [.300]
1.590 ± 0.127
[.063 ± .005]
6.81 [.268]
0.45 [.018]
0.20 [.008]
7.00°
7.00°
45.00°
7.00°
A
7.00°
3.180 ± 0.127
[.125 ± .005]
1 ± .0.250
[.040 ± .010]
0.20 ± 0.10
[.008 ± .004]
Dimensions in Millimeters [Inches]
Coplanarity = 0.1mm [0.004 inches]
9.7 ± 0.250
[.382 ± .010]
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-W454/P454 are approved by the following organizations:
IEC/EN/DIN EN 60747-5-2 (Option 060 only)
Approval under:
IEC 60747-5-2 :1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
3
UL - Approval under UL 1577, component recognition program up to VISO = 3750 VRMS (5000VRMS for ACPL-W454).
File E55361.
CSA - Approval under CSA Component Acceptance Notice
#5, File CA 88324.
Insulation Related Specifications
W454
P454
Parameter
Symbol
Value
Value
Units
Conditions
Min External Air Gap
(Clearance)
L(IO1)
8
7
mm
Measured from input terminals to output terminals
Min. External Tracking Path
(Creepage)
L(IO2)
8
8
mm
Measured from input terminals to output terminals
0.08
0.08
mm
Through insulation distance conductor to conductor
175
175
V
DIN IEC 112/VDE 0303 Part 1
Min. Internal Plastic Gap
(Clearance)
Tracking Resistance
CTI
Isolation Group
(per DIN VDE 0109)
IIIa
Material Group DIN VDE 0109
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060 only)
Description
Symbol
ACPL-W454
ACPL-P454
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage d 150 Vrms
for rated mains voltage d 300 Vrms
for rated mains voltage d 450 Vrms
for rated mains voltage d 600 Vrms
for rated mains voltage d 1000 Vrms
I-IV
I-IV
I-III
I-III
I-II
I-IV
I-IV
I-III
I-III
Climatic Classification
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
2
Units
Maximum Working Insulation Voltage
VIORM
1140
891
V peak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec
Partial Discharge < 5 pC,
VPR
2137
1670
V peak
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test, tm = 60 sec,
Partial Discharge < 5 pC
VPR
1710
1336
V peak
VIOTM
8000
8000
V peak
Safety Limiting Values
(Maximum values allowed in the event of a failure)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
230
600
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
d109
d109
:
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
*
4
Refer to the optocoupler section of the Designer’s Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of
Method a and Method b partial discharge test profiles.
Absolute Maximum Ratings
Storage Temperature
-55°C to +125°C
Operating Temperature
-55°C to +100°C
Average Input Current - IF
25 mA[1]
Peak Input Current - IF
50 mA[2] (50% duty cycle, 1 ms pulse width)
Peak Transient Input Current - IF
1.0 A (d1 ms pulse width, 300 pps)
Reverse Input Voltage - VR (Pin3-1)
5V
Input Power Dissipation
45 mW[3]
Average Output Current - IO (Pin 5)
8 mA
Peak Output Current
16 mA
Output Voltage - VO (Pin 5-4)
-0.5 V to 20 V
Supply Voltage - VCC (Pin 6-4)
-0.5 V to 30 V
Output Power Dissipation
100 mW[4]
Solder Reflow Temperature Profile
see Package Outline Drawings section
DC Electrical Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Parameter
Symbol
Min
Typ.*
Max.
Units
Test Conditions
Current
Transfer Ratio
CTR
25
32
60
%
TA = 25°C
21
34
Current
Transfer Ratio
CTR
26
35
Logic Low
Output Voltage
VOL
Logic High
Output Current
IOH
22
VO = 0.4 V
VO = 0.5 V
65
%
TA = 25°C
VO = 0.4 V
0.2
0.4
V
TA = 25°C
IO = 3.0 mA
0.2
0.5
0.003
0.5
0.01
1
VO = 0.5 V
37
PA
IF = 16 mA
VCC = 4.5 V
Fig.
Note
1, 2,
4
5
IF = 12 mA
VCC = 4.5 V
5
1
IO = 2.4 mA
IF = 16 mA
VCC = 4.5 V
TA = 25°C
VO = VCC= 5.5 V
IF = 0 mA
5
TA = 25°C
VO = VCC = 15.0 V
50
Logic Low
Supply Current
ICCL
50
200
PA
IF = 16 mA, VCC = 15 V
VO = open,
11
Logic High
Supply Current
ICCH
0.02
1
PA
TA = 25°C
VCC = 15 V
11
0.02
2
IF = 16 mA, VO =
Open,
Input Forward
Voltage
VF
1.5
1.7
V
TA = 25°C
IF = 16 mA
1.5
1.8
Input Reverse
Breakdown
Voltage
BVR
V
IR = 10 PA
Temperature
Coefficient of Forward Voltage
'VF/'TA
-1.6
mV/°C
IF = 16 mA
Input
Capacitance
CIN
60
pF
f = 1 MHz, VF = 0
*All typicals at TA = 25°C.
5
5
3
Switching Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified
Parameter
Propagation
Delay Time to
Logic Low at
Output
Propagation
Delay Time to
Logic High at
Output
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
0.2
0.3
Ps
TA = 25°C
6,8,9
9
0.2
0.5
Pulse: f = 20 kHz, Duty Cycle = 10%
IF = 16 mA, VCC = 5.0 V
RL = 1.9 k:, CL = 15 pF
V THHL = 1.5 V
0.2
0.5
0.7
TA = 25°C
6,
10-14
10
0.1
0.5
1.0
Pulse: f = 10 kHz, Duty Cycle = 50%
IF = 12 mA, VCC = 15.0 V
RL = 20 k:, CL = 100 pF
V THHL = 1.5 V
TA = 25°C
Pulse: f = 20 kHz, Duty Cycle = 10%
IF = 16 mA, VCC = 5.0 V
RL = 1.9 k:, CL = 15 pF
V THHL = 1.5 V
6,8,9
9
TA = 25°C
Pulse: f = 10 kHz, Duty Cycle = 50%
IF = 12 mA, VCC = 15.0 V
RL = 20 k:, CL = 100 pF
V THHL = 2.0 V
6,
10-14
10
TA = 25°C
Pulse: f = 10 kHz, Duty Cycle = 50%
IF = 12 mA, VCC = 15.0 V
RL = 20 k:, CL = 100 pF
V THHL = 1.5 V V THLH = 2.0V
6,
10-14
13
TA = 25°C
VCC = 5.0 V, RL = 1.9 k:
CL = 15 pF, IF = 0 mA
VCM = 1500 VP-P
7
7,9
TA = 25°C
VCC = 15.0 V, RL = 20 k:
CL = 100 pF, IF = 0 mA
VCM = 1500 VP-P
7
8,10
TA = 25°C
VCC = 5.0 V, RL = 1.9 k:
CL = 15 pF, IF = 16 mA
VCM = 1500 VP-P
7
7,9
tPHL
tPLH
0.3
0.5
0.3
0.7
0.3
0.8
1.1
0.2
0.8
1.4
Ps
Propagation
Delay Difference
Between Any 2
Parts
tPLH
- tPHL
-0.4
0.3
0.9
Ps
-0.7
0.3
1.3
Ps
Common Mode
Transient Immunity at Logic High
Level Output
|CMH|
15
30
15
30
Common Mode
Transient Immunity at Logic Low
Level Output
|CML|
15
30
15
30
TA = 25°C
VCC = 15.0 V, RL = 20 k:
CL = 100 pF, IF = 12 mA
VCM = 1500 VP-P
7
8,10
15
30
TA = 25°C
VCC = 15.0 V, RL = 20 k:
CL = 100 pF, IF = 16 mA
VCM = 1500 VP-P
7
8,10
*All typicals at TA = 25°C.
6
kV/Ps
kV/Ps
Package Characteristics
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. All typicals at TA = 25°C.
Parameter
Symbol
Min.
Input-Output Momentary
Withstand Voltage*
VISO
3750
Input-Output Resistance
RI-O
Input-Output Capacitance
CI-O
*
Typ.
Max.
Units
Test Conditions
Vrms
RH d 50%, t = 1 min, TA = 25°C
Fig.
Note
6,12
1012
:
VI-O = 500 Vdc
6
0.6
pF
f = 1 MHz; VI-O = 0 Vdc
6
5000 (For “ACPL-W454)
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C.
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO), to the forward LED input current (IF), times 100.
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV CM/dt on the
leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient
immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure
that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common mode pulse
signal,VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V).
9. The 1.9 k: load represents 1 TTL unit load of 1.6 mA and the 5.6 k: pull-up resistor.
10. The RL = 20 k:, CL = 100 pF load represents an IPM (Intelligent Power Mode) load.
11. Use of a 0.1 PF bypass capacitor connected between pins 4 and 6 is recommended.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage t4500 VRMS for 1 second (leakage detection
current limit, II-O d 5 PA); each optocoupler under ACPL-W454 is proof tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 μA).
13. The difference between tPLH and tPHL, between any two ACPL-W454/P454 parts under the same test condition. (See Power Inverter Dead Time and
Propagation Delay Specifications section).
25 mA
20 mA
15 mA
10 mA
0
IF = 5 mA
0
10
V O - OUTPUT VOLTAGE - V
20
Figure 1. DC and Pulsed Transfer Characteristics.
7
1.0
0.5
0.0
NORMALIZED
IF = 16 mA
V O = 0.4 V
V CC = 5.0 V
T A = 25 ˚C
0 2 4 6 8 10 12 14 16 18 20 22 24 26
IF - INPUT CURRENT - mA
Figure 2. Current Transfer Ratio vs. Input Current.
IF - FORWARD CURRENT - mA
35 mA
30 mA
5
1000
1.5
40 mA
NORMALIZED CURRENT TRANSFER RATIO
IO - OUTPUT CURRENT - mA
TA = 25 ˚C
10 VCC = 5.0 V
100
IF
10
1.0
TA = 25˚C
+
VF
-
0.1
0.01
0.001
1.1
1.2
1.3
1.4
1.5
VF - FORWARD VOLTAGE - VOLTS
Figure 3. Input Current vs. Forward Voltage.
1.6
10 4
IOH - LOGIC HIGH OUTPUT CURRENT - nA
NORMALIZED CURRENT TRANSFER RATIO
1.1
1.0
0.9
0.8
0.7
NORMALIZED
IF = 16 mA
V O = 0.4 V
V CC = 5.0 V
T A = 25 ˚C
10 3
IF = 0 mA
V O = V CC = 5.0 V
10 2
10 1
10 0
10 -1
0.6
-60 -40 -20
0 20 40 60 80 100 120
TA - TEMPERATURE - ˚C
Figure 4. Current Transfer Ratio vs. Temperature.
10 -2
-60 -40 -20
0 20 40 60 80 100 120
TA - TEMPERATURE - ˚C
Figure 5. Logic High Output Current vs. Temperature.
ACPL-W454/P454
IF
PULSE
GEN.
Z O = 50Ω
t r = 5 ns
0
V CC
VO
V THHL
1
6
2
5
V CC
RL
VO
0.1μF
V THLH
3
IF MONITOR
V OL
t PHL
IF
4
CL
100 Ω
t PLH
Figure 6. Switching Test Circuit.
ACPL-W454/P454
V CM
10 V
10%
0V
90%
IF
90%
tr
VO
10%
tf
B
SWITCH AT B: IF = 12 mA, 16 mA
RL
2
5
3
VO
4
V FF
CL
V OL
+
V CM
-
PULSE GEN.
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
8
V CC
6
0.1μF
V CC
SWITCH AT A: I F = 0 mA
VO
1
A
0.35
0.30
t PLH
t PHL
0.25
0.20
IF = 10 mA
IF = 16 mA
0.15
0.10
-60 -40 -20
0
0.8
t PHL
0.4
0
2
1.0
0.9
0.8
VCC = 15.0 V
R L = 20 k
C L = 100 pF
V THHL = 1.5 V
V THLH = 2.0 V
1.8
IF = 10 mA
IF = 16 mA
50% DUTY CYCLE
0.7
0.6
0.5
0.4
t PHL
0.3
-60 -40 -20
0
20 40
60 80 100 120
TA - TEMPERATURE - ˚C
Figure 11. Propagation Delay Time vs. Temperature.
1.2
1.1
tp - PROPAGATION DELAY - μs
1.0
0.9
0.8
0.7
t PLH
6 8 10 12 14 16 18 20
RL - LOAD RESISTANCE - k
1.4
1.2
1.0
0.8
t PLH
0.4
IF = 10 mA
IF = 16 mA
0.2
0.0
0
5
10 15 20 25 30 35 40 45 50
R L - LOAD RESISTANCE - k
Figure 12. Propagation Delay Time vs. Load Resistance.
TA = 25 ˚C
R L = 20 k
C L = 100 pF
V THHL = 1.5 V
V THLH = 2.0 V
50% DUTY CYCLE
0.6
0.5
0.4
0.3
0.2
t PLH
t PHL
0
t PHL
IF = 10 mA
IF = 16 mA
10 11 12 13 14 15 16 17 18 19 20
VCC - SUPPLY VOLTAGE - V
Figure 14. Propagation Delay Time vs. Supply
Voltage.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0253EN
AV02-1307EN - August 4, 2010
2
4
6
8
IF = 10 mA
IF = 16 mA
10 12 14 16 18 20
RL - LOAD RESISTANCE - k
Figure 10. Propagation Delay Time vs. Load
Resistance.
VCC = 15.0 V
TA = 25 ˚C
R L = 20 k
V THHL = 1.5 V
V THLH = 2.0 V
50% DUTY CYCLE
3.0
t PHL
0.6
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VCC = 5.0 V
TA = 25 ˚C
C L = 100 pF
V THHL = 1.5 V
VTHLH = 2.0 V
50% DUTY CYCLE
3.5
VCC = 15.0 V
TA = 25 ˚C
C L = 100 pF
V THHL = 1.5 V
VTHLH = 2.0 V
50% DUTY CYCLE
1.6
t PLH
4
Figure 9. Propagation Delay Time vs. Load Resistance.
t p - PROPAGATION DELAY - μs
tp - PROPAGATION DELAY - μs
1.1
IF = 10 mA
IF = 16 mA
0.2
TA - TEMPERATURE - ˚C
Figure 8. Propagation Delay Time vs. Temperature.
t PLH
0.6
0.0
20 40 60 80 100 120
2.6
2.4
tp - PROPAGATION DELAY - μs
0.40
VCC = 5.0 V
T = 25 ˚C
1.2 A
C L = 15 pF
1.0 V THHL = V THLH = 1.5 V
10% DUTY CYCLE
t p - PROPAGATION DELAY - μs
tp - PROPAGATION DELAY - μs
0.45
1.4
VCC = 5.0 V
R L = 1.9 k
C L = 15 pF
V THHL = V THLH = 1.5 V
10% DUTY CYCLE
tp - PROPAGATION DELAY - μs
0.50
2.5
2.0
t PLH
t PHL
1.5
1.0
IF = 10 mA
IF = 16 mA
0.5
0.0
0
200
400
600
800
CL - LOAD CAPACITANCE - pF
Figure 13. Propagation Delay Time vs. Load
Capacitance.
1000