NSC 54LVXC4245

54LVXC4245
8-Bit Dual Supply Configurable Voltage Interface
Transceiver with TRI-STATE ® Outputs
General Description
Features
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable
voltage interface transceiver suited for real time configurable
I/O applications. The VCCA pin accepts a 5V supply level.
The “A” port is a dedicated 5V port. The VCCB pin accepts a
3V-to-5V supply level. The “B” port is configured to track the
VCCB supply level respectively. A 5V level on the VCC pin will
configure the I/O pins at a 5V level and a 3V VCC will configure the I/O pins at a 3V level. This device will allow the VCCB
voltage source pin and I/O pins on the “B” port to float when
OE is HIGH. This feature is necessary to buffer data to and
from a socket that permits live insertion and removal during
normal operation.
Bidirectional interface between 5V and 3V-to-5V buses
Control inputs compatible with TTL level
Outputs source/sink up to 24 mA
Available in Cerpack and CDIP packages
Implements patented EMI reduction circuitry
Flexible VCCB operating range
Allows B port and VCCB to float simultaneously when OE
is HIGH
n Functionally compatible with the 54 series 245
n Standard Microcircuit Drawing (SMD) 5962-9862001
n
n
n
n
n
n
n
Ordering Code
Order Number
Package Number
Package Description
54LVXC4245W-QML
W24C
24-Lead Ceramic Flatpack
54LVXC4245J-QML
J24F
24-Lead Ceramic Dual-in-line
Logic Symbol
Connection Diagram
Pin Assignment
for Cerpack and CDIP
DS101033-1
Pin Descriptions
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A0–A7
Side A Inputs or TRI-STATE Outputs
B0–B7
Side B Inputs or TRI-STATE Outputs
DS101033-2
TRI-STATE ® is a registered trademark of National Semiconductor Corporation
© 1999 National Semiconductor Corporation
DS101033
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54LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE
Outputs
March 1999
Truth Table
Inputs
OE
Outputs
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH-Z State
Logic Diagram
DS101033-4
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2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCCA,VCCB)
DC Input Voltage (VI) @ OE, T/R
DC Input/Output Voltage (VI/O)
@ An
@ Bn
DC Input Diode Current (IIK)
@ OE, T/R
DC Output Diode Current (IOK)
DC Output Source or
Sink Current (IO)
DC VCC or Ground Current
Per Output Pin (ICC or IGND)
and Max Current
Storage Temperature Range
(TSTG)
Supply Voltage VCCA
VCCB
Input Voltage (VI) @ OE , T/R
Input/Output Voltage (VI/O)
@ An
@ Bn
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 30% to 70% of VCC
VCC @ 3V, 4.5V, 5.5V
−0.5V to +7.0V
−0.5V to VCCA +0.5V
−0.5V to VCCA +0.5V
−0.5V to VCCB +0.5V
± 20 mA
± 50 mA
± 50 mA
4.5V to 5.5V
2.7V to 5.5V
0V to VCCA
0V to VCCA
0V to VCCB
−55˚C to +125˚C
8 ns/V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
± 50 mA
± 200 mA
Note 2: The A port unused pins (inputs and I/O’s) must be held HIGH or
LOW. They may not float.
−65˚C to +150˚C
DC Electrical Characteristics
Symbol
Parameter
VCCA
(V)
VCCB
(V)
TA = −55˚C to
+125˚C
Units
Conditions
Guaranteed Limits
VIHA
An
4.5
2.7
2.0
Input Voltage
OE
4.5
3.6
2.0
or
T/R
5.5
5.5
2.0
≥ VCC − 0.1V
Bn
4.5
2.7
2.0
4.5
3.6
2.0
4.5
5.5
3.85
VIHB
VILA
VOHB
V
VOUT ≤ 0.1V
Maximum Low Level
An
4.5
2.7
0.8
Input Voltage
OE
4.5
3.6
0.8
or
T/R
5.5
5.5
0.8
≥ VCC − 0.1V
Bn
4.5
2.7
0.8
4.5
3.6
0.8
4.5
5.5
1.65
VILB
VOHA
V
VOUT ≤ 0.1V
Minimum High Level
4.5
2.7
4.4
5.5
5.5
5.4
4.5
3.0
3.7
4.5
4.5
3.7
4.5
2.7
2.6
5.5
5.5
5.4
4.5
2.7
2.2
4.5
3.0
2.4
4.5
3.0
2.2
IOH = −12 mA
IOH = −12 mA
IOH = −24 mA
4.5
4.5
3.7
IOH = −24 mA
3
V
IOH = −100 µA
IOH = −100 µA
IOH = −24 mA
Minimum High Level
Output Voltage
V
IOH = −24 mA
IOH = −100 µA
IOH = −100 µA
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DC Electrical Characteristics
(Continued)
TA = −55˚C to
+125˚C
VCCA
(V)
VCCB
(V)
Maximum Low Level
4.5
2.7
0.1
Output Voltage
5.5
5.5
0.1
4.5
3.0
0.4
4.5
4.5
0.4
4.5
2.7
0.1
5.5
5.5
0.1
4.5
2.7
0.3
4.5
3.0
0.3
4.5
3.0
0.4
4.5
4.5
0.4
± 1.0
± 1.0
± 5.0
± 5.0
µA
Symbol
Parameter
Units
Conditions
Guaranteed Limits
VOLA
VOLB
IIN
IOZA
IOZB
∆ICC
ICCA1
Maximum Input Leakage
5.5
3.6
Current @ OE, T/R
5.5
5.5
IOL = 24 mA
IOL = 24 mA
VI = VCCA, GND
5.5
3.6
5.5
± 5.0
± 5.0
µA
5.5
OE = VCCA
VO = VCCB, GND
VI = VCC − 2.1V
5.5
µA
Maximum
All
Inputs
5.5
5.5
1.5
mA
ICC/Input
Bn
5.5
3.6
0.5
mA
5.5
Open
40
µA
5.5
3.6
40
µA
5.5
5.5
40
Bn = VCCB or GND
OE = GND, T/R =
GND
An = VCCA or GND
5.5
3.6
10
µA
5.5
5.5
40
Bn = VCCB or GND
OE = GND, T/R =
VCCA
V
(Note 3)
V
(Note 3)
V
(Note 3)
V
(Note 3)
Quiescent VCCA
Quiescent VCCA
Quiescent VCCB
Quiet Output Maximum
5.0
3.3
1.5
Dynamic VOL
5.0
5.0
1.5
5.0
3.3
0.8
5.0
5.0
1.5
VOLPB
VOLVA
IOL = 100 µA
IOL = 100 µA
IOL = 12 mA
IOL = 12 mA
Maximum TRI-STATE
3.6
5.5
Supply Current
VOLPA
V
Output Leakage @ Bn
5.5
Output Leakage @ An
Supply Current
ICCB
IOL = 100 µA
IOL = 100 µA
IOL = 24 mA
IOL = 24 mA
VI = VIL, VIH
OE = VCCA
VO = VCCA, GND
VI = VIL, VIH,
Maximum TRI-STATE
Supply Current as B Port Floats
ICCA2
V
Quiet Output Minimum
5.0
3.3
-1.1
Dynamic VOL
5.0
5.0
-1.2
5.0
3.3
-0.7
5.0
5.0
-1.1
VOLVB
Note 3: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.
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4
VI = VCCB − 0.6V
An = VCCA or GND
Bn = Open, OE =
VCCA
T/R = VCCA, VCCB =
Open
An = VCCA or GND
AC Electrical Characteristics
Symbol
CL = 50 pF
VCCA = 4.5V to 5.5V
VCCB = 4.5V to 5.5V
TA = −55˚C to +125˚C
Parameter
CL = 50 pF
VCCA = 4.5V to 5.5V
VCCB = 2.7V to 3.6V
TA = −55˚C to +125˚C
Min
Max
Min
Max
tPHL
Propagation
1.0
8.0
1.0
9.5
tPLH
Delay A to B
1.0
8.0
1.0
9.5
tPHL
Propagation
1.0
8.0
1.0
9.5
tPLH
Delay B to A
1.0
8.0
1.0
9.5
tPZL
Output Enable
1.0
9.5
1.0
12.0
tPZH
Time OE to B
1.0
9.5
1.0
12.0
tPZL
Output Enable
1.0
11.5
1.0
13.0
tPZH
Time OE to A
1.0
11.5
1.0
13.0
tPHZ
Output Disable
1.0
7.0
1.0
7.5
tPLZ
Time OE to B
1.0
7.0
1.0
7.5
tPHZ
Output Disable
0.5
7.0
0.5
7.0
tPLZ
Time OE to A
0.5
7.0
0.5
7.0
tOSHL
Output to Output
tOSLH
Skew (Note 4)
1.5
1.5
Units
ns
ns
ns
ns
ns
ns
ns
Data to Output
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
CPD
Power Dissipation Capacitance
A→B
B→A
Max
Units
10
pF
50
pF
Conditions
VCC = Open
VCCA = 5V, VCCB = 3.3V
VCCA = 5V
12
pF
50
pF
VCCB = 3.3V
Note 5: CPD is measured at 10 MHz.
5
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Configurable I/O Application for mixed or unknown Voltages
“A” port is a dedicated 5V port to interface 5V ICs. The “B”
port is configurable and accepts a 3V-to-5V supply level.
This configurable ″B″ port provides maximum flexibility for interfacing to unknown supply voltages, for interfacing to supply voltages which may change in the future, or for providing
flexibility when supplying systems to multiple customers with
varying power supply requirements. Figure 1 shows how the
LVXC4245 fits into a system with a 3V subsystem and a 5V
subsystem.
LVXC4245 is designed to solve 3V/5V interfacing issues
when CMOS devices cannot tolerate I/O levels above their
applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the
P-Channel transistor in 3V ICs will conduct causing current
flow from I/O bus to the 3V power supply. The resulting high
current flow can cause destruction of 3V ICs through latchup
effects. To prevent this problem, a current limiting resistor is
used typically under direct connection of 3V ICs and 5V ICs,
but it causes speed degradation.
In a better solution, the LVXC4245 configures two different
output levels to handle the dual supply interface issues. The
DS101033-3
FIGURE 1. LVXC4245 Fits into a System with 3V Subsystem and 5V Subsystem
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6
Configurable I/O Application for
mixed or unknown Voltages
In the first case, when interfacing to non-TTL inputs such as
ACMOS or HCMOS where full 5V signal swings are needed,
the LVXC4245 can act as an amplifier to translate 0 volt to 3
volt signals up to 0 volt to 5 volt levels as shown in Figure 2.
(Continued)
Additionally, the LVXC4245 solves two other unique problems: when interfacing to non-TTL compatible signals or
when interfacing to components or busses which are pulled
up to 5V.
DS101033-5
FIGURE 2. LVXC4245 amplifies 3V signals for interfacing to non-TTL inputs.
sumption. The LVXC4245 can be used to translate the 3 volt
signals to 5 volt levels and eliminate the power consumed by
the pull-up resistors.
In the second case, when interfacing to busses which use resistive pull-ups to 5V, it is desirable to avoid connecting 3V
devices directly to the bus to avoid excessive power con-
DS101033-6
FIGURE 3. LVXC4245 for interfacing to 5V busses with pull-ups minimizes power consumption.
7
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Ceramic Flatpack
Package Number W24C
24-Lead Ceramic Dual-in-line
Package Number J24F
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8
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54LVXC4245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE
Outputs
Notes