54ACT573 Octal Latch with TRI-STATE ® Outputs General Description Features The ’ACT573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. n ICC and IOZ reduced by 50% n Inputs and outputs on opposite sides of package allowing easy interface with microprocessors n Useful as input or output port for microprocessors n Functionally identical to ’ACT373 n TRI-STATE outputs for bus interfacing n Outputs source/sink 24 mA n ’ACT573 has TTL-compatible inputs n Standard Military Drawing (SMD) — ’ACT573: 5962-87664 The ’ACT573 is functionally identical to the ’ACT373 but has inputs and outputs on opposite sides. Logic Symbols IEEE/IEC DS100332-1 DS100332-2 Pin Names D0–D7 Description Data Inputs LE Latch Enable Input OE TRI-STATE Output Enable Input O0–O7 TRI-STATE Latch Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100332 www.national.com 54ACT573 Octal Latch with TRI-STATE Outputs August 1998 Connection Diagrams Pin Assignment for LCC Pin Assignment for DIP and Flatpak DS100332-4 DS100332-3 www.national.com 2 Functional Description Truth Table The ’ACT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram DS100332-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 175˚C Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage Minimum High Level Output Voltage VOH VOL IIN Maximum Low Level Output Voltage Maximum Input 4.5 2.0 5.5 2.0 4.5 0.8 V 5.5 0.8 or VCC − 0.1V 4.5 4.4 V 5.5 5.4 V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA (Note 2) VIN = VIL or VIH 4.5 3.70 5.5 4.70 4.5 0.1 5.5 0.1 V IOH −24 mA −24 mA V IOUT = 50 µA (Note 2) VIN = VIL or VIH 4.5 0.50 5.5 0.50 V IOL 24 mA 5.5 ± 1.0 µA 5.5 ± 5.0 µA VI = VIL, VIH VO = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 24 mA VI = VCC, GND Leakage Current IOZ Maximum TRI-STATE Leakage Current ICCT Maximum ICC/Input IOLD IOHD www.national.com (Note 3) Minimum Dynamic Output Current 4 DC Characteristics for ’ACT Family Devices Symbol Parameter (Continued) VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits ICC Maximum Quiescent Supply Current 5.5 80.0 µA VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 5) tPLH Propagation Delay Fig. Units Min Max 5.0 1.5 13.5 ns 5.0 1.5 13.5 ns 5.0 1.5 13.0 ns 5.0 1.5 12.0 ns No. Dm to On tPHL Propagation Delay Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On tPZH Output Enable Time 5.0 1.5 11.5 ns tPZL Output Enable Time 5.0 1.5 11.0 ns tPHZ Output Disable Time 5.0 1.5 13.5 ns tPLZ Output Disable Time 5.0 1.5 10.5 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 6) 54ACT TA = −55˚C to +125˚C CL = 50 pF Fig. Units No. Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 4.5 ns 5.0 1.0 ns 5.0 5.0 ns Dn to LE th Hold Time, HIGH or LOW Dn to LE tw LE Pulse Width, HIGH Note 6: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 5.0 pF Power Dissipation 25.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V 7 Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 20-Lead Ceramic Flatpak (F) NS Package Number W20A 9 www.national.com 54ACT573 Octal Latch with TRI-STATE Outputs LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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