19-3348; Rev 3; 3/11 4A, 20ns, Dual MOSFET Drivers The MAX5054–MAX5057 dual, high-speed MOSFET drivers source and sink up to 4A peak current. These devices feature a fast 20ns propagation delay and 20ns rise and fall times while driving a 5000pF capacitive load. Propagation delay time is minimized and matched between the inverting and noninverting inputs and between channels. High sourcing/sinking peak currents, low propagation delay, and thermally enhanced packages make the MAX5054–MAX5057 ideal for highfrequency and high-power circuits. The MAX5054–MAX5057 operate from a 4V to 15V single power supply and consume 40µA (typ) of supply current when not switching. These devices have internal logic circuitry that prevents shoot-through during output state changes to minimize the operating current at high switching frequency. The logic inputs are protected against voltage spikes up to +18V, regardless of the VDD voltage. The MAX5054A is the only version that has CMOS input logic levels while the MAX5054B/MAX5055/ MAX5056/MAX5057 have TTL input logic levels. The MAX5055–MAX5057 provide the combination of dual inverting, dual noninverting, and inverting/noninverting input drivers. The MAX5054 feature both inverting and noninverting inputs per driver for greater flexibility. They are available in 8-pin TDFN (3mm x 3mm), standard SO, and thermally enhanced SO packages. These devices operate over the automotive temperature range of -40°C to +125°C. Applications Features o 4V to 15V Single Power Supply o 4A Peak Source/Sink Drive Current o 20ns (typ) Propagation Delay o Matching Delay Between Inverting and Noninverting Inputs o Matching Propagation Delay Between Two Channels o VDD / 2 CMOS Logic Inputs (MAX5054AATA) o TTL Logic Inputs (MAX5054B/MAX5055/MAX5056/MAX5057) o 0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input Hysteresis o Up to +18V Logic Inputs (Regardless of VDD Voltage) o Low Input Capacitance: 2.5pF (typ) o 40µA (typ) Quiescent Current o -40°C to +125°C Operating Temperature Range o 8-Pin TDFN and SO Packages Ordering Information PART TEMP RANGE PINPACKAGE TOP MARK Power MOSFET Switching Motor Control MAX5054AATA+ -40°C to +125°C 8 TDFN-EP* Switch-Mode Power Supplies Power-Supply Modules MAX5054AATA/V+ -40°C to +125°C 8 TDFN-EP* BMF MAX5054BATA+ -40°C to +125°C 8 TDFN-EP* AGR MAX5055AASA+ -40°C to +125°C 8 SO-EP* MAX5055BASA+ -40°C to +125°C 8 SO — MAX5056AASA+ -40°C to +125°C 8 SO-EP* — MAX5056BASA+ -40°C to +125°C 8 SO — MAX5057AASA+ -40°C to +125°C 8 SO-EP* — MAX5057BASA+ -40°C to +125°C 8 SO *EP = Exposed pad. /VDenotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. — DC-DC Converters Typical Operating Circuit VOUT VIN MAX5054 VDD AGS — INA+ OUTA INA- INB+ OUTB PWM IN INB- Selector Guide and Pin Configurations appear at end of data sheet. GND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5054–MAX5057 General Description MAX5054–MAX5057 4A, 20ns, Dual MOSFET Drivers ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.) VDD...............................................................................-0.3V to +18V INA+, INA-, INB+, INB- ...............................................-0.3V to +18V OUTA, OUTB...................................................-0.3V to (VDD + 0.3V) OUTA, OUTB Short-Circuit Duration ........................................10ms Continuous Source/Sink Current at OUT_ (PD < PDMAX) .....200mA Continuous Power Dissipation (TA = +70°C) 8-Pin TDFN-EP (derate 18.2mW/°C above +70°C)........1454mW 8-Pin SO-EP (derate 19.2mW/°C above +70°C)… ........1538mW 8-Pin SO (derate 5.9mW/°C above +70°C)… ..................471mW Operating Temperature Range..............................-40°C to +125°C Storage Temperature Range .................................-65°C to +150°C Junction Temperature ...........................................................+150°C Lead Temperature (soldering, 10s)......................................+300°C Soldering Temperature (reflow)............................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) 8 SO-EP Junction-to-Ambient Thermal Resistance (θJA)..................+41°C/W Junction-to-Case Thermal Resistance (θJC)......................+7°C/W 8 TDFN-EP Junction-to-Ambient Thermal Resistance (θJA)...............+41°C/W Junction-to-Case Thermal Resistance (θJC)......................+8°C/W 8 SO Junction-to-Ambient Thermal Resistance (θJA)................+132°C/W Junction-to-Case Thermal Resistance (θJC).......................+40°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDD = 4V to 15V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 15 V 3.50 3.85 V POWER SUPPLY VDD Operating Range VDD Undervoltage Lockout VDD UVLO 4 VDD rising 3.00 VDD Undervoltage Lockout Hysteresis VDD Undervoltage Lockout to Output Delay VDD rising IDD INA- = INB- = VDD, INA+ = INB+ = 0V (not switching) 200 mV 12 µs VDD = 4V 28 55 VDD = 15V 40 75 2.4 4 1.1 1.8 µA VDD Supply Current IDD-SW INA- = 0V, INB+ = VDD = 15V, INA+ = INB- both channels switching at 250kHz, CL = 0F 1 mA DRIVER OUTPUT (SINK) Driver Output Resistance Pulling Down Peak Output Current (Sinking) RON-N IPK-N Output-Voltage Low Latchup Protection 2 VDD = 15V, IOUT_ = -100mA TA = +25°C TA = +125°C 1.5 2.4 VDD = 4.5V, IOUT_ = -100mA TA = +25°C 2.2 3.3 TA = +125°C 3.0 4.5 VDD = 15V, CL = 10,000pF IOUT_ = -100mA ILUP 4 A VDD = 4.5V 0.45 VDD = 15V 0.24 Reverse current IOUT_ (Note 2) 400 _______________________________________________________________________________________ Ω V mA 4A, 20ns, Dual MOSFET Drivers (VDD = 4V to 15V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRIVER OUTPUT (SOURCE) Driver Output Resistance Pulling Up RON-P Peak Output Current (Sourcing) IPK-P Output-Voltage High VDD = 15V, IOUT_ = 100mA TA = +25°C 1.5 2.1 TA = +125°C 1.9 2.75 VDD = 4.5V, IOUT_ = 100mA TA = +25°C 2.75 4 TA = +125°C 3.75 5.5 VDD = 15V, CL = 10,000pF 4 VDD = 4.5V VDD 0.55 VDD = 15V VDD 0.275 IOUT_ = 100mA Ω A V LOGIC INPUT (Note 4) MAX5054A Logic 1 Input Voltage Logic 0 Input Voltage VIH VIL MAX5054B/MAX5055/MAX5056/MAX5057 (Note 5) 0.7 x VDD V 2.1 0.3 x VDD MAX5054A MAX5054B/MAX5055/MAX5056/MAX5057 Logic-Input Hysteresis VHYS 0.1 x VDD MAX5054A MAX5054B/MAX5055/MAX5056/MAX5057 Logic-Input-Current Leakage Input Capacitance INA+, INB+, INA-, INB- = 0V or VDD V 0.8 V 0.3 -1 CIN +0.1 +1 2.5 µA pF SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1) OUT_ Rise Time tR OUT_ Fall Time tF CL = 1000pF 4 CL = 5000pF 18 CL = 10,000pF 32 CL = 1000pF 4 CL = 5000pF 15 CL = 10,000pF 26 ns ns Turn-On Delay Time tD-ON CL = 10,000pF (Note 3) 10 20 34 ns Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 3) 10 20 34 ns SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1) OUT_ Rise Time tR OUT_ Fall Time tF CL = 1000pF 7 CL = 5000pF 37 CL = 10,000pF 85 CL = 1000pF 7 CL = 5000pF 30 CL = 10,000pF 75 ns ns Turn-On Delay Time tD-ON CL = 10,000pF (Note 3) 18 35 70 ns Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 3) 18 35 70 ns _______________________________________________________________________________________ 3 MAX5054–MAX5057 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VDD = 4V to 15V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MATCHING CHARACTERISTICS Mismatch Propagation Delays from Inverting and Noninverting Inputs to Output ∆tON-OFF Mismatch Propagation Delays Between Channel A and Channel B ∆tA-B VDD = 15V, CL = 10,000pF 2 VDD = 4.5V, CL = 10,000pF 4 ns VDD = 15V, CL = 10,000pF 1 VDD = 4.5V, CL = 10,000pF 2 ns All devices are 100% tested at TA = +25°C. Specifications over -40°C to +125°C are guaranteed by design. Limits are guaranteed by design, not production tested. The logic-input thresholds are tested at VDD = 4V and VDD = 15V. TTL compatible with reduced noise immunity. Note 2: Note 3: Note 4: Note 5: Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) TA = +125°C TA = +25°C 20 40 30 TA = +25°C 20 10 10 0 10 12 14 8 10 12 14 PROPAGATION DELAY TIME, HIGH-TO-LOW vs. SUPPLY VOLTAGE (CL = 5000pF) IDD-SW SUPPLY CURRENT vs. SUPPLY VOLTAGE 30 20 4 2 8 10 MAX5054 toc03 12 14 16 DUTY CYCLE = 50% VDD = 15V, CL = 4700pF 1 CHANNEL SWITCHING 90 80 70 1MHz 60 50 500kHz 40 30 50kHz 100kHz 10 0 0 6 10 20 50kHz 100kHz 8 100 MAX5054 toc05 500kHz 1 TA = -40°C 6 SUPPLY CURRENT vs. SUPPLY VOLTAGE 1MHz 3 4 SUPPLY VOLTAGE (V) DUTY CYCLE = 50% VDD = 15V, CL = 0 1 CHANNEL SWITCHING 5 16 SUPPLY CURRENT (mA) TA = +25°C 6 IDD-SW SUPPLY CURRENT (mA) MAX5054 toc04 40 0 12 SUPPLY VOLTAGE (V) 4 6 SUPPLY VOLTAGE (V) TA = +125°C 4 TA = -40°C 0 4 16 SUPPLY VOLTAGE (V) 10 20 MAX5054 toc06 8 60 50 TA = +25°C 30 TA = -40°C 0 6 40 10 TA = -40°C 4 TA = +125°C 50 PROPAGATION DELAY (ns) 50 FALL TIME (ns) RISE TIME (ns) TA = +125°C 40 60 MAX5054 toc02 50 30 60 MAX5054 toc01 60 PROPAGATION DELAY TIME, LOW-TO-HIGH vs. SUPPLY VOLTAGE (CL = 5000pF) FALL TIME vs. SUPPLY VOLTAGE (CL = 5000pF) RISE TIME vs. SUPPLY VOLTAGE (CL = 5000pF) PROPAGATION DELAY (ns) MAX5054–MAX5057 4A, 20ns, Dual MOSFET Drivers 14 16 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 4 6 8 10 12 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 14 16 4A, 20ns, Dual MOSFET Drivers 2.5 2.0 1.5 MAX5054AATA (CMOS INPUT) 9 8 7 VIN RISING 6 5 4 VIN FALLING 3 2 3.0 INPUT THRESHOLD VOLTAGE (V) 3.0 10 MAX5054 toc08 VDD = 15V, f = 250kHz, CL = 0 DUTY CYCLE = 50% BOTH CHANNELS SWITCHING INPUT THRESHOLD VOLTAGE (V) SUPPLY CURRENT (mA) MAX5054 toc07 4.0 3.5 INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE MAX5054 toc09 IDD-SW SUPPLY CURRENT vs. TEMPERATURE TTL INPUT VERSIONS 2.5 VIN RISING 2.0 1.5 1.0 VIN FALLING 0.5 1 1.0 -25 0 25 50 75 100 4 6 8 10 12 4 16 14 10 12 14 SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH) SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW) SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH) 200 MAX5054AATA (CMOS INPUT) VDD = 15V 4 SUPPLY CURRENT (mA) SUPPLY CURRENT (µA) 400 300 200 100 100 2 4 6 8 10 12 14 0 16 3 2 1 0 0 MAX5054 toc12 TTL INPUT VERSIONS VDD = 15V 16 5 MAX5054 toc11 500 MAX5054 toc10 300 2 4 6 8 10 12 14 0 16 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V) LOGIC-INPUT VOLTAGE (V) LOGIC-INPUT VOLTAGE (V) SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW) DELAY MISMATCH BETWEEN IN_+ AND IN_- TO OUT_ vs. TEMPERATURE DELAY MISMATCH BETWEEN IN_+ AND IN_- TO OUT_ vs. TEMPERATURE 3 2 1 2 OUTPUT RISING 0 -2 -4 2 4 6 8 10 12 LOGIC-INPUT VOLTAGE (V) 14 16 4 OUTPUT RISING 2 0 -2 OUTPUT FALLING -4 MAX5054AATA (CMOS INPUT) VDD = 4.5V, CL = 10,000pF MAX5054AATA (CMOS INPUT) VDD = 15V, CL = 10,000pF -6 -6 0 6 MAX5054 toc15 4 DELAY MISMATCH (ns) 4 OUTPUT FALLING DELAY MISMATCH (ns) MAX5054AATA (CMOS INPUT) VDD = +15V MAX5054 toc14 6 MAX5054 toc13 5 0 8 SUPPLY VOLTAGE (V) 400 0 6 SUPPLY VOLTAGE (V) TTL INPUT VERSIONS VDD = 15V SUPPLY CURRENT (µA) 125 TEMPERATURE (°C) 500 SUPPLY CURRENT (mA) 0 0 -50 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX5054–MAX5057 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) DELAY MISMATCH BETWEEN 2 CHANNELS vs. TEMPERATURE DELAY MISMATCH BETWEEN 2 CHANNELS vs. TEMPERATURE 3 1 0 -1 VDD = 15V, CL = 10,000pF 3 DELAY MISMATCH (ns) OUTPUT FALLING OUTPUT RISING MAX5054 toc17 VDD = 4.5V, CL = 10,000pF 2 4 MAX5054 toc16 4 DELAY MISMATCH (ns) MAX5054–MAX5057 4A, 20ns, Dual MOSFET Drivers OUTPUT RISING 2 1 0 -1 -2 -2 -3 -3 OUTPUT FALLING -4 -4 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF) MAX5054 toc18 LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF) MAX5054 toc19 IN_2V/div IN_2V/div OUT_ 2V/div MAX5055 (TTL INPUT) OUT_ 2V/div MAX5055 (TTL INPUT) 20ns/div 40ns/div LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF) MAX5054 toc21 MAX5054 toc20 IN_2V/div IN_2V/div OUT_ 2V/div OUT_ 2V/div MAX5055 (TTL INPUT) 20ns/div 6 MAX5055 (TTL INPUT) 40ns/div _______________________________________________________________________________________ 4A, 20ns, Dual MOSFET Drivers LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF) MAX5054 toc22 LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF) MAX5054 toc23 IN_2V/div IN_2V/div OUT_ 5V/div OUT_ 5V/div MAX5055 MAX5055 20ns/div 40ns/div LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF) LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF) MAX5054 toc24 MAX5054 toc25 IN_2V/div IN_2V/div OUT_ 5V/div OUT_ 5V/div MAX5055 MAX5055 20ns/div 40ns/div VDD vs. OUTPUT VOLTAGE VDD vs. OUTPUT VOLTAGE MAX5054 toc26 MAX5054 toc27 VDD 5V/div OUTA 5V/div MAX5055 INA- = INB- = GND CLA = CLB = 10,000pF VDD 5V/div OUTA 5V/div OUTB 5V/div MAX5055 INA- = INB- = GND CLA = CLB = 10,000pF 2ms/div OUTB 5V/div 2ms/div _______________________________________________________________________________________ 7 MAX5054–MAX5057 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX5054–MAX5057 4A, 20ns, Dual MOSFET Drivers Pin Descriptions MAX5054 PIN NAME 1 INA- Inverting Logic-Input Terminal for Driver A. Connect to GND when not used. FUNCTION 2 INB- Inverting Logic-Input Terminal for Driver B. Connect to GND when not used. 3 GND Ground 4 OUTB Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off. 5 VDD 6 OUTA Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors. Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off. 7 INB+ Noninverting Logic-Input Terminal for Driver B. Connect to VDD when not used. 8 INA+ Noninverting Logic-Input Terminal for Driver A. Connect to VDD when not used. — EP Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical ground connection. MAX5055/MAX5056/MAX5057 PIN MAX5055 MAX5056 MAX5057 1, 8 1, 8 1, 8 2 — 3 3 4 8 NAME FUNCTION N.C. No Connection. Not internally connected. 2 INA- Inverting Logic-Input Terminal for Driver A. Connect to GND if not used. 3 GND Ground — — INB- Inverting Logic-Input Terminal for Driver B. Connect to GND if not used. 5 5 5 OUTB Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off. 6 6 6 VDD Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors. 7 7 7 OUTA Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off. — 4 4 INB+ Noninverting Logic-Input Terminal for Driver B. Connect to VDD if not used. — 2 — INA+ Noninverting Logic-Input Terminal for Driver A. Connect to VDD if not used. — — — EP Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical ground connection. _______________________________________________________________________________________ 4A, 20ns, Dual MOSFET Drivers MAX5054–MAX5057 IN_+ VIH VIL VDD MAX5055 MAX5056 MAX5057 90% OUT_ tD-OFF1 tD-ON1 IN_+ tF IN_- P BREAKBEFOREMAKE CONTROL 10% tR OUT_ N VIH VIL tD-OFF2 tD-ON2 GND RISING MISMATCH = tD-ON2 - tD-ON1 FALLING MISMATCH = tD-OFF2 - tD-OFF1 NONINVERTING INPUT DRIVER Figure 1. Timing Diagram VDD MAX5055 MAX5056 MAX5057 VDD MAX5054 IN_- P BREAKBEFOREMAKE CONTROL IN_+ P BREAKBEFOREMAKE CONTROL IN_OUT_ OUT_ N N GND GND INVERTING INPUT DRIVER Figure 2. MAX5054 Block Diagram (1 Driver) Detailed Description VDD Undervoltage Lockout (UVLO) The MAX5054–MAX5057 have internal undervoltage lockout for VDD. When VDD is below the UVLO threshold, OUT_ is low, independent of the state of the inputs. The undervoltage lockout is typically 3.5V with 200mV typical hysteresis to avoid chattering. When VDD rises above the UVLO threshold, the outputs go high or low depending upon the logic-input levels. Bypass VDD using low-ESR ceramic capacitors for proper operation (see the Applications Information section). Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams (1 Driver) Logic Inputs The MAX5054B–MAX5057 have TTL-compatible logic inputs, while the MAX5054A is a CMOS logic-input driver. The logic-input signals can be independent of the VDD voltage. For example, the device can be powered by a 5V supply while the logic inputs are provided from CMOS logic. Also, the logic inputs are protected against the voltage spikes up to 18V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 300mV and 0.1 x VDD hysteresis, respectively, to avoid possible double pulsing during transition. The low 2.5pF input capacitance reduces loading and increases switching speed. _______________________________________________________________________________________ 9 MAX5054–MAX5057 4A, 20ns, Dual MOSFET Drivers Table 1. MAX5054 Truth Table INA+/INB+ INA-/INB- OUTA/OUTB Low Low Low Low High Low High Low High High High Low Table 2. MAX5055/MAX5056/MAX5057 Truth Table VDD MAX5054A PWM INPUT INA+ OFF ON INA- OUTA GND NONINVERTING IN_+ OUT_ Low Low High High INVERTING IN_- OUT_ Low High High Low The logic inputs are high impedance and must not be left floating. If the inputs are left open, OUT_ can go to an undefined state as soon as VDD rises above the UVLO threshold. Therefore, the PWM output from the controller must assume proper state when powering up the device. The MAX5054 has two logic inputs per driver providing greater flexibility in controlling the MOSFET. Use IN_+ for noninverting logic and IN_- for inverting logic operation. Connect IN_+ to V DD and IN_- to GND if not used. Alternatively, the unused input can be used as an ON/OFF function. Use IN_+ for active-low shutdown logic and IN_- for active-high shutdown logic (see Figure 4). See Table 1 for all possible input combinations. Driver Output The MAX5054–MAX5057 have low RDS(ON) p-channel and n-channel devices (totem pole) in the output stage for the fast turn-on and turn-off high gate-charge switching MOSFETs. The peak source or sink current is typically 4A. The OUT_ voltage is approximately equal to VDD when in high state and is ground when in low state. The driver R DS(ON) is lower at higher V DD , thus higher source-/sink-current capability and faster switching speeds. The propagation delays from the noninverting and inverting logic inputs to outputs are matched to 2ns. The break-before-make logic avoids any cross-conduction between the internal p- and n-channel devices, and eliminates shoot-through currents reducing the quiescent supply current. 10 Figure 4. Unused Input as an ON/OFF Function (1/2 MAX5054A) Applications Information RLC Series Circuit The driver’s RDS(ON) (RON), internal bond and lead inductance (LP), trace inductance (LS), gate inductance (LG), and gate capacitance (CG) form a series RLC circuit with a second-order characteristic equation. The series RLC circuit has an undamped natural frequency (ϖ0) and a damping ratio (ζ) where: ϖ0 = 1 (LP + LS + LG ) × CG RON ξ= 2 × (LP + LS + LG ) CG The damping ratio needs to be greater than 0.5 (ideally 1) to avoid ringing. Add a small resistor (RGATE) in series with the gate when driving a very low gate-charge MOSFET, or when the driver is placed away from the MOSFET. Use the following equation to calculate the series resistor: RGATE ≥ (LP + LS + LG ) − RON CG LP can be approximated as 3nH and 2nH for SO and TDFN packages, respectively. LS is on the order of 20nH/in. Verify LG with the MOSFET vendor. ______________________________________________________________________________________ 4A, 20ns, Dual MOSFET Drivers Power Dissipation Power dissipation of the MAX5054–MAX5057 consists of three components: caused by the quiescent current, capacitive charge/discharge of internal nodes, and the output current (either capacitive or resistive load). Maintain the sum of these components below the maximum power dissipation limit. The current required to charge and discharge the internal nodes is frequency dependent (see the Supply Current vs. Supply Voltage graph in the Typical Operating Characteristics). The power dissipation (PQ) due to the quiescent switching supply current (IDD-SW) per driver can be calculated as: PQ = VDD x IDD-SW For capacitive loads, use the following equation to estimate the power dissipation per driver: PCLOAD = CLOAD x (VDD)2 x fSW where CLOAD is the capacitive load, VDD is the supply voltage, and fSW is the switching frequency. Calculate the total power dissipation (PT) per driver as follows: PT = PQ + PCLOAD Use the following equation to estimate the MAX5054– MAX5057 total power dissipation per driver when driving a ground-referenced resistive load: PT = PQ + PRLOAD where D (duty cycle) is the fraction of the period the MAX5054–MAX5057’s output pulls high duty cycle, RON(MAX) is the maximum on-resistance of the device with the output high, and ILOAD is the output load current of the MAX5054–MAX5057. Layout Information The MAX5054–MAX5057 MOSFET drivers source and sink large currents to create very fast rising and falling edges at the gate of the switching MOSFET. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Use the following PC board layout guidelines when designing with the MAX5054–MAX5057: • Place one or more 0.1µF decoupling ceramic capacitors from VDD to GND as close to the device as possible. Connect VDD and GND to large copper areas. Place one bulk capacitor of 10µF (min) on the PC board with a low resistance path to the VDD input and GND of the MAX5054–MAX5057. • Two AC current loops form between the device and the gate of the driven MOSFET. The MOSFET looks like a large capacitance from gate to source when the gate pulls low. The active current loop is from the MOSFET gate to OUT_ of the MAX5054–MAX5057, to GND of the MAX5054–MAX5057, and to the source of the MOSFET. When the gate of the MOSFET pulls high, the active current is from the VDD terminal of the decoupling capacitor, to V DD of the MAX5054– MAX5057, to OUT_ of the MAX5054–MAX5057, to the MOSFET gate, to the MOSFET source, and to the negative terminal of the decoupling capacitor. Both charging current and discharging current loops are important. Minimize the physical distance and the impedance in these AC current paths. • Keep the device as close to the MOSFET as possible. • In a multilayer PC board, the inner layers should consist of a GND plane containing the discharging and charging current loops. • Pay extra attention to the ground loop and use a low-impedance source when using a TTL logicinput device. Fast fall time at OUT_ may corrupt the input during transition. PRLOAD = D x RON(MAX) x ILOAD2 ______________________________________________________________________________________ 11 MAX5054–MAX5057 Supply Bypassing and Grounding Pay extra attention to bypassing and grounding the MAX5054–MAX5057. Peak supply and output currents may exceed 8A when both drivers drive large external capacitive loads in phase. Supply voltage drops and ground shifts create forms of negative feedback for inverters and may degrade the delay and transition times. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same AC ground return path. Any series inductance in the VDD, OUT_, and/or GND paths can cause oscillations due to the very high di/dt when switching the MAX5054–MAX5057 with any capacitive load. Place one or more 0.1µF ceramic capacitors in parallel as close to the device as possible to bypass VDD to GND. Use a ground plane to minimize ground return resistance and series inductance. Place the external MOSFET as close as possible to the MAX5054–MAX5057 to further minimize board inductance and AC path impedance. MAX5054–MAX5057 4A, 20ns, Dual MOSFET Drivers Exposed Pad Both the SO-EP and TDFN-EP packages have an exposed pad on the bottom of their package. These pads are internally connected to GND. For the best thermal conductivity, solder the exposed pad to the ground plane to dissipate 1.5W and 1.9W in SO-EP and TDFN-EP packages, respectively. Do not use the ground-connected pads as the only electrical ground connection or ground return. Use GND (pin 3) as the primary electrical ground connection. Additional Application Circuits VOUT VIN MAX5054 VDD INA+ OUTA INA- MAX5054 VDD VDD PWM IN INA+ INB+ OUTA INA- PWM IN OUTB PWM IN INBGND INB+ OUTB INBGND Figure 5. Push-Pull Converter with Synchronous Rectification Drive Using MAX5054 12 ______________________________________________________________________________________ 2 R27 10Ω PVIN REG9 REG5 TP3 3 4 C19 1µF C18 1000pF C17 0.33µF R11 360Ω R3 2.2kΩ REG5 LXH REG5 C6 0.1µF C3 4.7µF C4 4.7µF R15 31.6kΩ 1% D8 1 C2 390pF R16 10.5kΩ 1% TP1 C1 100pF C5 4700pF R25 100kΩ C24 1000pF +VIN R21 24.9kΩ 1% RCFF 14 13 12 11 10 9 8 7 6 17 18 19 20 21 22 2 1 REG9 R12 100kΩ 1% R19 475Ω R23 10Ω 2 VOUT OUT FB 4 1 2 65 U3 R17 0.027Ω 1% D3 1 PVIN 3 4 IN 1 PGND 2 GND C21 4.7µF 80V 2 2 C34 330pF 8 2 D2 VOUT 1 2 4 R24 10Ω 3 2 1 87 5 6 N1 8 7 D7 2 10 2T 8 +VIN T1 XFRMRH R22 15kΩ 6 4T 1 5 8T 2 1 3 XFRMRH R18 4.7Ω D5 R13 47Ω REG9 R5 38.3kΩ 1% 7 N2 R6 1MΩ 1% +VIN R7 0Ω R8 8.2Ω R2 2.55kΩ 1% 5 SENSE (+) SENSE (-) TRIM 3 R9 8.2Ω 1 +VIN R14 270Ω C9 1µF DRVB XFRMRH C8 4.7µF +VIN ON/OFF D1 R4 1MΩ 1% C7 0.22µF C27 0.15µF C20 220pF R20 0Ω 29 16 DRVL 15 CS PGND DRVDD DRVB XFRMRH DRVH BST 23 24 25 26 27 28 C36 C28 R1 0.22µF 0.047µF 11.5kΩ 1% VOUT U2 LXL LXH LXVDD STT PVIN REG9 REG5 FB COMP AVIN GND UVLO STARTUP IC_PADDLE SYNCOUT FLTINT MAX5051 RCOSC U1 SYNCIN 4 COM 5 CSS 3 2 1 D6 1 1 6 5 4 N3 1 7 4 6 INA- INB+ OUTB OUTA 1 4 EN IN RESET L1 2.4µH MAX5054 U4 4 3 GND 2 1 C11 0.47µF 100V N4 56 C32 1µF C22 2200pF 2kV +5V C23 1000pF 1 87 D4 R10 2 3 20Ω 2 2 C35 1µF C10 0.47µF 100V 3 5 2 C30 0.1µF C13 270µF 4V 5V C25 0.047µF 100V +5V 5 C26 0.1µF GND VDD INB- 8 HOLD REG9 7 8 N.C. 6 WDI OUT INA+ U5 C12 1µF 100V +VIN 2 N5 3 3 4 5 1 GND OUT VCC U6 CA AN 2 1 LXH C33 1µF 10V R29 1Ω XFRMRH VOUT -VIN C15 270µF 4V U1: MAX5051 U2: PS2913-1-M U3: MAX8515 U4: MAX5054 U5: MAX5023M U6: PS9715 N1, N2: SI4486 N3, N4: SI4864 N5: BSS123 C31 5V 0.1µF C14 270µF 4V C16 3.3µF +VIN R28 2kΩ R26 560Ω SGND VOUT DRVB MAX5054–MAX5057 REG5 4A, 20ns, Dual MOSFET Drivers Figure 6. Schematic of a 48V Input, 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply ______________________________________________________________________________________ 13 4A, 20ns, Dual MOSFET Drivers MAX5054–MAX5057 Pin Configurations TOP VIEW MAX5054 MAX5055 INA- 1 8 INA+ N.C. 1 8 N.C. INB- 2 7 INB+ INA- 2 7 OUTA GND 3 6 OUTA GND 3 6 VDD OUTB 4 5 VDD INB- 4 5 OUTB TDFN-EP SO/SO-EP MAX5056 MAX5057 N.C. 1 8 N.C. N.C. 1 8 N.C. INA+ 2 7 OUTA INA- 2 7 OUTA GND 3 6 VDD GND 3 6 VDD INB+ 4 5 OUTB INB+ 4 5 OUTB SO/SO-EP SO/SO-EP Selector Guide Chip Information PROCESS: CMOS PART PINPACKAGE LOGIC INPUT MAX5054AATA 8 TDFN-EP* VDD / 2 CMOS Dual Inverting and Dual Noninverting Inputs MAX5054BATA 8 TDFN-EP* TTL Dual Inverting and Dual Noninverting Inputs MAX5055AASA 8 SO-EP* TTL Dual Inverting Inputs MAX5055BASA 8 SO TTL Dual Inverting Inputs MAX5056AASA 8 SO-EP* TTL Dual Noninverting Inputs MAX5056BASA 8 SO TTL Dual Noninverting Inputs MAX5057AASA 8 SO-EP* TTL Inverting and Noninverting Inputs MAX5057BASA 8 SO TTL Inverting and Noninverting Inputs Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 TDFN-EP T833+2 21-0137 90-0059 8 SO-EP S8E+14 21-0111 90-0151 8 SO S8+4 21-0041 90-0096 *EP = Exposed pad. 14 ______________________________________________________________________________________ 4A, 20ns, Dual MOSFET Drivers REVISION NUMBER REVISION DATE 0 8/04 Initial release 1 9/05 Package-related changes 2 9/10 Added automotive part; updated Package Information table 3 3/11 Corrected top mark discrepancy and actual top mark for MAX5054AATA/V+ DESCRIPTION PAGES CHANGED 0 TBD 1, 2, 14, 15, 16 1, 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX5054–MAX5057 Revision History