54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks General Description The ’LS192 is an up/down BCD decade (8421) counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stage without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. Connection Diagram Logic Symbol Dual-In-Line Package TL/F/10178 – 2 VCC e Pin 16 GND e Pin 8 TL/F/10178 – 1 Order Number 54LS192DMQB, 54LS192FMQB, 54LS192LMQB, DM74LS192M or DM74LS192N See NS Package Number E20A, J16A, M16A, N16E or W16A Pin Names CPU CPD MR PL P0 – P3 Q0 – Q3 TCD TCU Mode Select Table Description Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW) C1995 National Semiconductor Corporation TL/F/10178 MR PL CPU CPD Mode H L L L L X L H H H X X H L H X X H H L Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial RRD-B30M105/Printed in U. S. A. 54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks May 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C 54LS DM74LS 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol 54LS192 Parameter DM74LS192 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Voltage IOL Low Level Output Current TA Free Air Operating Temperature ts (H) ts (L) Setup Time HIGH or LOW Pn to PL 20 20 20 10 ns th (H) th (L) Hold Time HIGH or LOW Pn to PL 3 3 3 3 ns tw (L) CP Pulse Width LOW 17 17 ns tw (L) PL Pulse Width LOW 20 20 ns tw (H) MR Pulse Width HIGH 15 15 ns trec Recovery Time, MR to CP 3 3 ns trec Recovery Time, PL to CP 10 10 ns 2 2 V 0.7 0.8 V b 0.4 b 0.4 mA 8 mA 70 §C 4 b 55 V 125 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max 54LS 2.5 DM74 2.7 VCC e Min, IOL e Max, 54LS VOL Low Level Output Voltage Typ (Note 1) Max Units b 1.5 V V 0.4 VIH e Min DM74 0.5 IOL e 4 mA, VCC e Min DM74 0.4 Input Current @ Max Input Voltage VCC e Max, VI e 10V VI e 7V DM74 High Level Input Current IIL IOS II IIH ICC DM54 V 0.1 mA VCC e Max, VI e 2.7V 20 mA Low Level Input Current VCC e Max, VI e 0.4V b 0.4 mA Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max, MR, PL e GND Other Inputs e 4.5V 54LS b 20 b 100 DM74 b 20 b 100 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. 2 31 mA mA Switching Characterisitcs VCC e a 0.5V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol RL e 2k CL e 15 pF Parameter Min Units Max fmax Maximum Count Frequency 30 MHz tPLH tPHL Propagation Delay CPU or CPD to Qn 31 28 tPLH tPHL Propagation Delay CPU to TCU 16 21 tPLH tPHL Propagation Delay CPD to TCD 16 24 tPLH tPHL Propagation Delay Pn to Qn 20 30 tPLH tPHL Propagation Delay PL to Qn 32 30 tPHL Propagation Delay, MR to Qn 25 ns ns ns ns Functional Description TCU e Q0 # Q3 # CPU TCD e Q0 # Q1 # Q2 # Q3 # CPD Each circuit has an asynchronous parallel load capability permitting the counter to be reset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data inputs (P0 – P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. The ’192 is an asynchronously presettable decade and 4-bit binary synchronous up/down (reversible) counter. The operating modes of the ’192 decade counter and the ’193 binary counter are identical, with the only difference being the count sequences as noted in the State Diagram. Each circuit contains four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up, and count down operations. Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave, and thus the Q output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock input is LOW. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When a circuit has reached the maximum count state (9 for the ’192, 15 for the ’193), the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. State Diagram TL/F/10178 – 4 3 TL/F/10178 – 3 Logic Diagram 4 5 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS192LMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS192DMQB NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS192M NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS192N NS Package Number N16E 7 54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS192FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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