54AC191 Up/Down Counter with Preset and Ripple Clock General Description Features The ’AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature allows the ’AC191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. n n n n n n n Logic Symbols Connection Diagrams ICC reduced by 50% High speed — 133 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Outputs source/sink 24 mA Standard Military Drawing (SMD) — ’AC191: 5962-89749 Pin Assignment for DIP and Flatpack DS100279-1 IEEE/IEC DS100279-3 Pin Assignment for LCC DS100279-2 Pin Names Description CE Count Enable Input CP Clock Pulse Input P0–P3 Parallel Data Inputs PL Asynchronous Parallel Load Input U/D Up/Down Count Control Input Q0–Q3 Flip-Flop Outputs RC Ripple Clock Output TC Terminal Count Output DS100279-4 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100279 www.national.com 54AC191 Up/Down Counter with Preset and Ripple Clock July 1998 Functional Description Mode Select Table The ’AC191 is a synchronous up/down counter. The ’AC191 is organized as a 4-bit binary counter. It contains four edge-triggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Load inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is determined by the U/D input signal, as indicated in the Mode Select Table. CE and U/D can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The terminal count (TC) output is normally LOW. It goes HIGH when the circuits reach zero in the count down mode or 15 in the count up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) output. The RC output is normally HIGH. When CE is LOW and TC is HIGH, RC output wil go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage counters, as indicated in Figure 1 and Figure 2. In Figure 1, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC output pulse, as indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure 2. All clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output of any device goes HIGH shortly after its CP input goes HIGH. The configuration shown in Figure 3 avoids ripple delays and their associated restrictions. The CE input for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figure 1 and Figure 2 doesn’t apply, because the TC output of a given stage is not affected by its own CE. www.national.com Inputs PL CE Mode U/D CP H L L N H L H N Count Down L X X X Preset (Asyn.) H H X X No Change (Hold) Count Up RC Truth Table Inputs CE TC* CP RC H L H J J H H X X H H X L X H L X X X H *TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition 2 Outputs PL Functional Description (Continued) DS100279-7 FIGURE 1. N-Stage Counter Using Ripple Clock DS100279-8 FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow DS100279-9 FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow 3 www.national.com State Diagram DS100279-5 Logic Diagram DS100279-6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 4 Absolute Maximum Ratings (Note 1) Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 175˚C Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 2.0V to 6.0V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Characteristics for ’AC Family Devices Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 54AC TA = −55˚C to +125˚C Units Conditions Guaranteed Limits 3.0 2.1 4.5 3.15 5.5 3.85 3.0 0.9 4.5 1.35 5.5 1.65 3.0 2.9 4.5 4.4 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL Maximum Low Level Output Voltage 3.0 2.4 4.5 3.7 5.5 4.7 3.0 0.1 4.5 0.1 5.5 0.1 −12 mA V IOH −24 mA −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IIN Maximum Input 3.0 0.50 4.5 0.50 12 mA V IOL 24 mA 5.5 0.50 5.5 ± 1.0 µA VI = VCC, GND 24 mA Leakage Current IOLD (Note 3) Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 80.0 µA VIN = VCC Supply Current or GND 5 www.national.com DC Characteristics for ’AC Family Devices (Continued) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. AC Electrical Characteristics 54AC TA = −55˚C to +125˚C CL = 50 pF VCC Symbol Parameter (V) (Note 5) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Max Maximum Count 3.3 55 Frequency 5.0 80 Propagation Delay 3.3 1.0 16.5 CP to Qn 5.0 1.0 12.0 Propagation Delay 3.3 1.0 16.0 CP to Qn 5.0 1.0 12.0 Propagation Delay 3.3 1.0 19.5 CP to TC 5.0 1.0 14.0 Propagation Delay 3.3 1.0 19.0 CP to TC 5.0 1.0 14.5 Propagation Delay 3.3 1.0 14.0 CP to RC 5.0 1.0 10.5 Propagation Delay 3.3 1.0 12.5 CP to RC 5.0 1.0 9.5 Propagation Delay 3.3 1.0 14.0 CE to RC 5.0 1.0 10.0 Propagation Delay 3.3 1.0 12.5 CE to RC 5.0 1.0 9.5 Propagation Delay 3.3 1.0 14.5 U/D to RC 5.0 1.0 11.0 Propagation Delay 3.3 1.0 15.0 U/D to RC 5.0 1.0 11.0 Propagation Delay 3.3 1.0 14.0 U/D to TC 5.0 1.0 10.5 Propagation Delay 3.3 1.0 13.5 U/D to TC 5.0 1.0 10.0 Propagation Delay 3.3 1.0 16.5 Pn to Qn 5.0 1.0 11.5 Propagation Delay 3.3 1.0 15.5 Pn to Qn 5.0 1.0 10.5 Propagation Delay 3.3 1.0 18.0 PL to Qn 5.0 1.0 12.5 Propagation Delay 3.3 1.0 15.5 PL to Qn 5.0 1.0 11.5 Note 5: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.national.com Units 6 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Fig. No. AC Operating Requirements 54AC Symbol ts th ts th ts th tw tw trec TA = −55˚C to +125˚C CL = 50 pF VCC (V) (Note 6) Parameter Fig. No. Guaranteed Minimum Setup Time, HIGH or LOW 3.3 4.0 Pn to PL 5.0 3.0 Hold Time, HIGH or LOW 3.3 1.5 Pn to PL 5.0 2.0 Setup Time, LOW 3.3 9.0 CE to CP 5.0 6.0 Hold Time, LOW 3.3 0 CE to CP 5.0 0.5 Setup Time, HIGH or LOW 3.3 10.5 U/D to CP 5.0 7.5 Hold Time, HIGH or LOW 3.3 0 U/D to CP 5.0 1.0 PL Pulse Width, LOW 3.3 5.0 5.0 5.0 3.3 6.0 5.0 6.0 CP Pulse Width, LOW Units Recovery Time 3.3 1.5 PL to CP 5.0 1.0 ns ns ns ns ns ns ns ns ns Note 6: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 75.0 pF Conditions VCC = OPEN VCC = 5.0V Capacitance 7 www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 9 www.national.com 54AC191 Up/Down Counter with Preset and Ripple Clock Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.