INTEGRATED CIRCUITS 74F193 Up/down binary counter with separate up/down clocks Product specification IC15 Data Handbook 1995 Jul 17 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 Multistage counters will not be fully synchronous since there is a two-gate delay time difference added for each stage that is added. FEATURES • Synchronous reversible 4-bit counting • Asynchronous parallel load capability • Asynchronous reset (clear) • Cascadable without external logic The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel Data inputs (D0 - D3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs when the Parallel Load (PL) input is Low. A High level on the Master Reset (MR) input will disable the parallel load gates, override both clock inputs, and set all Q outputs Low. If one of the clock inputs is Low during and after a reset or load operation, the next Low-to-High transition of the clock will be interpreted as a legitimate signal and will be counted. DESCRIPTION The 74F193 is a 4-bit synchronous up/down counter in the binary mode. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the Low-to-High transition of either clock input. If the CPU clock is pulsed while CPD is held High, the device will count up. If CPD clock is pulsed while CPU is held High, the device will count down. The device can be cleared at any time by the asynchronous reset pin. It may also be loaded in parallel by activating the asynchronous parallel load pin. Inside the device are four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, asynchronous preset, load, and synchronous count up and count down functions. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F193 125MHz 32mA ORDERING INFORMATION Each flip-flop contains JK feedback from slave to master, such that a Low-to-High transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 16-pin plastic DIP N74F193N SOT38-4 16-pin plastic SO N74F193D SOT109-1 PIN CONFIGURATION One clock should be held High while counting with the other, because the circuit will either count by twos or not at all, depending on the state of the first JK flip-flop, which cannot toggle as long as either clock input is Low. Applications requiring reversible operation must make the reversing decision while the activating clock is High to avoid erroneous counts. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally High. When the circuit has reached the maximum count state of 15, the next High-to-Low transition of CPU will cause TCU to go Low. TCU will stay Low until CPU goes High again, duplicating the count up clock, although delayed by two gate delays. Likewise, the TCD output will go Low when the circuit is in the zero state and the CPD goes Low. The TC outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. D1 1 16 VCC Q1 2 15 D0 Q0 3 14 MR CPD 4 13 TCD CPU 5 12 TCU Q2 6 11 PL Q3 7 10 D2 GND 8 9 D3 SF00745 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 - D3 Data inputs 1.0/1.0 20µA/0.6mA CPU Count up clock input (active rising edge) 1.0/3.0 20µA/1.8mA CPD Count down clock input (active rising edge) 1.0/3.0 20µA/1.8mA PL Asynchronous parallel load control input (active Low) 1.0/1.0 20µA/0.6mA MR Asynchronous master reset input 1.0/1.0 20µA/0.6mA Q0 - Q3 Flip-flop outputs 50/33 1.0mA/20mA TCU Terminal count up (carry) output (active Low) 50/33 1.0mA/20mA TCD Terminal count down (borrow) output (active Low) 50/33 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. 1.0mA/20mA 1995 Jul 17 2 853-0353 15459 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks LOGIC SYMBOL 74F193 LOGIC SYMBOL (IEEE/IEC) 15 1 10 11 9 C3 5 D0 11 5 4 14 D1 D2 4 12 TCU 15 Q2 Q3 1 10 3 VCC = Pin 16 GND = Pin 8 2 6 9 7 SF00746 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 COUNT UP COUNT DOWN TCU = Q0 . Q1 . Q2 . Q3 . CPU TCD = Q0 . Q1 . Q2 . Q3 . CPD Logic Equations for Terminal Count 1995 Jul 17 R 3D [1] [2] [4] [8] 3 2 6 7 SF00747 STATE DIAGRAM 0 13 13 MR Q1 12 G2 14 TCD Q0 2CT=0 1– PL CPD 1CT=15 G1 D3 CPU CTR DIV 16 2+ SF00748 3 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 LOGIC DIAGRAM D0 D1 15 D2 1 D3 10 9 11 PL 12 13 TCU TCD 5 CPU CPD 4 J RD CP Q K SD J RD Q Q J RD CP SD Q CP Q K SD J RD Q CP Q K SD Q 14 MR 3 Q0 VCC = Pin 16 GND = Pin 8 2 Q1 6 Q1 7 Q1 SF00749 FUNCTION TABLE INPUTS H L X ↑ OUTPUTS OPERATING MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD H H X X X X L H X X X X X X X X L L L L L L L L H H L H L L L L L L L L X X L H L H X X L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H H H L H L H H H L H ↑ H X X X X H1 H Count up H2 Count down L = = = = H H ↑ High voltage level Low voltage level Don’t care Low-to-High clock transition 1995 Jul 17 X X X Count up X Count down H NOTES: TCU=CPU at terminal count up (HHHH) TCD=CPD at terminal count down (LLLL) 4 MODE Reset (clear) Parallel load Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5.0 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL TEST CONDITIONSNO TAG PARAMETER VCC = MIN, VIL = MAX, IOH = MAX, VIH = MIN VOH O High level output voltage High-level VOL O Low level output voltage Low-level VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH High-level input current IIL Low level in Low-level input ut current IOS Short-circuit output Others currentNO TAG 10%VCC 2.5 5%VCC 2.7 NO TAG MAX V 3.4 V 10%VCC 0.35 0.50 V 5%VCC 0.35 0.50 V –0.73 –1.2 V VCC = MAX, VI = 7.0V 100 µA VCC = MAX, VI = 2.7V 20 µA –1.8 mA –0.6 mA –150 mA VCC = MIN, VIL = MAX, IOL = MAX, VIH = MIN CPU, CPD UNIT TYP MIN VCC = MAX, MAX VI = 0 0.5V 5V VCC = MAX –60 ICC Supply current (total)4 VCC = MAX 32 50 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with parallel load and Master reset inputs grounded, all other inputs at 4.5V and all outputs open. 1995 Jul 17 5 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω TEST CONDITIONS MIN TYP Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 100 125 tPLH tPHL Propagation delay CPU or CPD to TCU or TCD Waveform 2 2.5 3.0 5.5 5.0 8.5 8.0 2.5 3.0 90 9.0 9.0 MHz ns ns tPLH tPHL Propagation delay CPU or CPD to Qn Waveform 1 2.5 5.0 5.5 8.5 8.5 12.0 2.5 5.0 9.0 13.0 ns ns tPLH tPHL Propagation delay Dn to Qn Waveform 4 2.0 6.0 4.0 9.5 7.0 13.5 1.5 6.0 8.0 15.0 ns ns tPLH tPHL Propagation delay PL to Qn Waveform 3 4.5 5.5 6.5 8.5 10.0 12.0 4.0 5.0 11.0 13.0 ns ns tPHL Propagation delay MR to Qn Waveform 5 5.0 7.5 11.0 5.0 12.0 ns tPLH Propagation delay MR to TCU Waveform 5 6.0 8.5 12.0 5.5 13.0 ns tPHL Propagation delay MR to TCD Waveform 5 5.0 7.5 11.0 5.0 12.0 ns tPLH tPHL Propagation delay PL to TCU or TCD Waveform 3 6.0 6.0 9.5 9.0 13.5 12.0 6.0 6.0 15.0 13.0 ns ns tPLH tPHL Propagation delay Dn to TCU or TCD Waveform 4 5.5 4.5 9.0 8.5 13.0 12.5 5.0 4.5 14.0 13.5 ns ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN TYP MAX Tamb= 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX ts(H) ts(L) Setup time, High or Low Dn to PL Waveform 6 4.5 4.5 5.0 5.0 ns ns th(H) th(L) Hold time, High or Low Dn to PL Waveform 6 2.0 2.0 2.0 2.0 ns ns tw(L) PL Pulse width Low Waveform 3 6.0 6.0 ns tw(H) tw(L) CPU or CPD Pulse width High or Low Waveform 1 3.5 5.0 3.5 5.0 ns ns tw(L) CPU or CPD Pulse width Low (Change of direction) Waveform 1 10.0 10.0 ns tw(H) MR Pulse width High Waveform 5 6.0 6.0 ns trec Recovery time, PL to CPU or CPD Waveform 3 6.0 6.0 ns trec Recovery time MR to CPU or CPD Waveform 5 4.0 4.0 ns 1995 Jul 17 6 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 AC WAVEFORMS For all waveforms Vm = 1.5V 1/fMAX CPU, CPD tW(L) CPU, CPD VM tW(H) VM tPHL tPHL tPLH tPLH TCU, TCD Qn VM VM VM VM VM VM SF00753 SF00750 Waveform 2. Propagation Delay, Clock to Terminal Count Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width and Maximum Clock Frequency Dn VM VM tW(L) tPLH PL VM VM VM tPHL VM tPLH Qn, TCU, TCD trec tPHL VM VM tPHL CPU, CPD tPLH VM Qn, TCU, TCD VM VM SF00754 TCU, TCD, Qn VM Waveform 4. Propagation Delay, Data to Flip-Flop Outputs, Terminal Count Up and Down Outputs VM SF00751 Waveform 3. Parallel Pulse Width, Parallel Load to Output Delays, and Parallel Load to Clock Recovery Time Dn VM tS(H) MR VM VM th(H) tS(L) th(L) VM PL tW(H) VM trec The shaded areas indicate when the input is permitted to change for predictable output performance. CPU, CPD VM Waveform 6. Data Setup and Hold Times tPLH VM TCU tPHL Qn, TCD VM SF00752 Waveform 5. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time 1995 Jul 17 7 SF00755 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 Timing Diagram (Typical clear, load, and count sequence) CLEAR1 MR PL LOAD D0 D1 DATA D2 D3 COUNT UP2 CPU COUNT DOWN2 CPD Q0 Q1 OUTPUTS Q2 Q3 TCU TCD 0 SEQUENCE 13 14 15 0 1 2 1 COUNT UP 0 15 14 13 COUNT DOWN CLEAR PRESET NOTES: 1. Clear overrides load, data, and count inputs. 2. When counting up, count-down input must be High; when counting down, count-up input must be High. SF00756 Binary Counter TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1995 Jul 17 8 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks DIP16: plastic dual in-line package; 16 leads (300 mil) 1995 Juk 17 9 74F193 SOT38-4 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks SO16: plastic small outline package; 16 leads; body width 3.9 mm 1995 Juk 17 10 74F193 SOT109-1 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks NOTES 1995 Juk 17 11 74F193 Philips Semiconductors Product specification Up/down binary counter with separate up/down clocks 74F193 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 10-98 9397-750-05094