54AC74/54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q General Description The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level HIGH Features ICC reduced by 50% Output source/sink 24 mA ’ACT74 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC74: 5962-88520 — ’ACT74: 5962-87525 n 54AC74 now qualified to 300Krad RHA designation, refer to the SMD for more information n n n n Logic Symbols 10026602 10026601 IEEE/IEC Pin Names Description D 1, D 2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q 1, Q 1, Q 2, Q 2 Outputs 10026603 FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 2003 National Semiconductor Corporation DS100266 www.national.com 54AC74/54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop July 2003 54AC74/54ACT74 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC 10026604 10026605 Truth Table (Each Half) Inputs Outputs SD CD CP D Q L H X X H L H L X X L H L L X X H H Q H H N H H L H H N L L H H H L X Q0 Q0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock Logic Diagram 10026606 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 ’ACT (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) −0.5V to +7.0V 54AC/ACT DC Input Diode Current (IIK) −55˚C to +125˚C Minimum Input Edge Rate (∆V/∆t) VI = −0.5V −20 mA ’AC Devices VI = VCC + 0.5V +20 mA VIN from 30% to 70% of VCC DC Input Voltage (VI) −0.5V to VCC + 0.5V VCC @ 3.3V, 4.5V, 5.5V DC Output Diode Current (IOK) VO = −0.5V −20 mA ’ACT Devices VO = VCC + 0.5V +20 mA VIN from 0.8V to 2.0V DC Output Voltage (VO) −0.5V to VCC + 0.5V VCC @ 4.5V, 5.5V DC Output Source DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. ± 50 mA or Sink Current (IO) Storage Temperature (TSTG) 125 mV/ns Minimum Input Edge Rate (∆V/∆t) −65˚C to +150˚C Junction Temperature (TJ) CDIP 175˚C Recommended Operating Conditions Supply Voltage (VCC) ’AC 2.0V to 6.0V DC Characteristics for ’AC Family Devices 54AC Symbol Parameter VCC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High 3.0 2.1 Level Input 4.5 3.15 Voltage 5.5 3.85 Maximum Low 3.0 0.9 Level Input 4.5 1.35 Voltage 5.5 1.65 Minimum High 3.0 2.9 Level Output 4.5 4.4 Voltage 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low 3.0 0.1 Level Output 4.5 0.1 Voltage 5.5 0.1 −12 mA V IOH −24 mA −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH 3 www.national.com 54AC74/54ACT74 Absolute Maximum Ratings 54AC74/54ACT74 DC Characteristics for ’AC Family Devices (Continued) 54AC Symbol Parameter VCC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits 3.0 IIN Maximum Input 0.5 12 mA 4.5 0.5 5.5 0.5 V IOL 5.5 ± 1.0 µA VI = VCC, GND 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 5.5 40.0 µA VIN = VCC 24 mA 24 mA Leakage Current IOLD IOHD ICC (Note 3) Minimum Dynamic Output Current Maximum Quiescent Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices 54ACT Symbol Parameter VCC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage 4.5 2.0 5.5 2.0 4.5 0.8 5.5 0.8 4.5 4.4 5.5 5.4 Maximum Input VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA (Note 5) VIN = VIL or VIH 4.5 3.70 5.5 4.70 4.5 0.1 5.5 0.1 V IOH −24 mA −24 mA V IOUT = 50 µA (Note 5) VIN = VIL or VIH 4.5 IIN V 0.50 V IOL 24 mA 5.5 0.50 5.5 ± 1.0 µA VI = VCC, GND 24 mA 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min Leakage Current ICCT Maximum ICC/Input IOLD IOHD www.national.com (Note 6) Minimum Dynamic Output Current 4 54AC74/54ACT74 DC Characteristics for ’ACT Family Devices (Continued) 54ACT Symbol Parameter VCC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits ICC Maximum Quiescent 5.5 40.0 µA Supply Current VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. AC Electrical Characteristics Symbol Parameter VCC 54AC (V) TA = −55˚C to +125˚C (Note 8) CL = 50 pF Min fmax tPLH tPHL tPLH tPHL Units Fig. No. Max Maximum Clock 3.3 70 Frequency 5.0 95 MHz Propagation Delay 3.3 1.0 13.0 CDn or SDn to Qn or Qn 5.0 1.0 9.5 Propagation Delay 3.3 1.0 14.0 CDn or SDn to Qn or Qn 5.0 1.0 10.5 Propagation Delay 3.3 1.0 17.5 CPn to Qn or Qn 5.0 1.0 12.0 Propagation Delay 3.3 1.0 13.5 CPn to Qn or Qn 5.0 1.0 10.0 ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54AC Symbol ts Parameter Set-up Time, HIGH or LOW th tw trec VCC TA = −55˚C to +125˚C (V) CL = 50 pF (Note 9) Guaranteed Limits 3.3 5.0 Dn to CPn 5.0 4.0 Hold Time, HIGH or LOW 3.3 0.5 Dn to CPn 5.0 0.5 CPn or CDn or SDn 3.3 8.0 Pulse Width 5.0 5.5 Recovery Time 3.3 0.5 CDn or SDn to CP 5.0 0.5 Units Fig. No. ns ns ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com 54AC74/54ACT74 AC Electrical Characteristics 54ACT Symbol Parameter VCC TA = −55˚C (V) to +125˚C (Note 10) CL = 50 pF Min fmax Maximum Clock Fig. Units No. Max 5.0 85 MHz 5.0 1.0 11.5 ns 5.0 1.0 12.5 ns 5.0 1.0 14.0 ns 5.0 1.0 12.0 ns Frequency tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACT Symbol Parameter ts Set-up Time, HIGH or LOW VCC TA = −55˚C (V) CL = 50 pF (Note 11) Guaranteed Limits 5.0 4.0 ns 5.0 1.0 ns 5.0 7.0 ns 5.0 0.5 ns Units No. Dn to CPn th Hold Time, HIGH or LOW Dn to CPn tw CPn or CDn or SDn Pulse Width trec Recovery Time CDn or SDn to CP Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation 35.0 pF VCC = 5.0V Capacitance www.national.com 6 Fig. Conditions 54AC74/54ACT74 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 14-Lead Ceramic Dual-In-Line Package (D) NS Package Number J14A 7 www.national.com 54AC74/54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Ceramic Flatpak (F) NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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