LMX2335U/LMX2336U PLLatinum™ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2335U 1.2 GHz/1.2 GHz LMX2336U 2.0 GHz/1.2 GHz General Description Features The LMX2335U and LMX2336U devices are high performance frequency synthesizers with integrated dual modulus prescalers. The LMX2335U and LMX2336U devices are designed for use in applications requiring two RF phase-locked loops. A 64/65 or a 128/129 prescale ratio can be selected for each RF synthesizer. Using a proprietary digital phase locked loop technique, the LMX2335U and LMX2336U devices generate very stable, low noise control signals for the RF voltage controlled oscillators. Both RF synthesizers include a two-level programmable charge pump. The RF1 synthesizer has dedicated Fastlock circuitry. Serial data is transferred to the devices via a three wire interface (Data, LE, Clock). Supply voltages from 2.7V to 5.5V are supported. The LMX2335U and the LMX2336U feature very low current consumption: n Ultra Low Current Consumption n Upgrade and Compatible to the LMX2335L and LMX2336L devices n 2.7V to 5.5V operation n Selectable Synchronous or Asynchronous Powerdown Mode: ICC-PWDN = 1 µA typical at 3.0V n Selectable Dual Modulus Prescaler RF1: 64/65 or 128/129 RF2: 64/65 or 128/129 n Selectable Charge Pump TRI-STATE ® Mode n Programmable Charge Pump Current Levels RF1 and RF2: 0.95 or 3.8 mA n Selectable Fastlock™ Mode for the RF1 Synthesizer n Push-Pull Analog Lock Detect Mode n LMX2335U is available in 16-Pin TSSOP and 16-Pin CSP n LMX2336U is available in 20-Pin TSSOP, 24-Pin CSP, and 20-Pin UTCSP LMX2335U (1.2 GHz)– 3.0 mA, LMX2336U (2.0 GHz)– 3.5 mA at 3.0V. The LMX2335U device is available in 16-pin TSSOP, and 16-pin Chip Scale Package (CSP) surface mount plastic packages. The LMX2336U device is available in 20-Pin TSSOP, 24-Pin CSP, and 20-Pin UTCSP surface mount plastic packages. Applications n Mobile Handsets (GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC, DCS) n Cordless Handsets (DECT, DCT) n Wireless Data n Cable TV Tuners Thin Shrink Small Outline Package (MTC16) Thin Shrink Small Outline Package (MTC20) 10136780 10136787 Chip Scale Package (SLB16A) Chip Scale Package (SLB24A) Ultra Thin Chip Scale Package (SLE20A) 10136795 10136781 10136788 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation. © 2002 National Semiconductor Corporation DS101367 www.national.com LMX2335U/LMX2336U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications November 2002 LMX2335U/LMX2336U LMX2335U Functional Block Diagram 10136789 LMX2336U Functional Block Diagram 10136701 www.national.com 2 LMX2335U Thin Shrink Small Outline Package (TM) (Top View) LMX2335U Chip Scale Package (SLB) (Top View) 10136702 10136738 LMX2336U Thin Shrink Small Outline Package (TM) (Top View) LMX2336U Chip Scale Package (SLB) (Top View) 10136703 10136736 LMX2336U Ultra Thin Chip Scale Package (SLE) (Top View) 10136796 3 www.national.com LMX2335U/LMX2336U Connection Diagrams LMX2335U/LMX2336U Pin Descriptions Pin No. Pin No. Pin No. Pin LMX2336U LMX2336U LMX2336U Name 20-Pin 20-Pin 24-Pin UTCSP TSSOP CSP Pin No. LMX2335U 16-Pin TSSOP Pin No. LMX2335U 16-Pin CSP I/O Description VCC 20 1 24 1 16 – Power supply bias for the RF1 PLL analog and digital circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. VP RF1 1 2 2 2 1 – RF1 PLL charge pump power supply. Must be ≥ VCC. Do RF1 2 3 3 3 2 O RF1 PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. GND 3 4 4 4 3 – LMX2335U: Ground for the RF1 PLL analog and digital circuits. LMX2336U: Ground for the RF1 PLL digital circuitry. fIN RF1 4 5 5 5 4 I RF1 PLL prescaler input. Small signal input from the VCO. fIN RF1 5 6 6 X X I LMX2335U: Don’t care. LMX2336U: RF1 PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX2336U RF1 PLL can be driven differentially when the bypass capacitor is omitted. GND 6 7 7 X X – LMX2335U: Don’t care. LMX2336U: Ground for the RF1 PLL analog circuitry. OSCin 7 8 8 6 5 I Oscillator input. It has an approximate VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. OSCout 8 9 10 7 6 O Oscillator output. This output is connected directly to a crystal. If a TCXO is used, it is left open. FoLD 9 10 11 8 7 O Programmable multiplexed output pin. Functions as a general purpose CMOS TRI-STATE output, RF1/RF2 PLL push-pull analog lock detect output, N and R divider output, or Fastlock output, which connects a parallel resistor to the external loop filter. Clock 10 11 12 9 8 I MICROWIRE Clock input. High impedance CMOS input. Data is clocked into the 22-bit shift register on the rising edge of Clock. Data 11 12 14 10 9 I MICROWIRE Data input. High impedance CMOS input. Binary serial data. The MSB of Data is entered first. The last two bits are the control bits. LE 12 13 15 11 10 I MICROWIRE Latch Enable input. High impedance CMOS input. When LE transitions HIGH, Data stored in the shift registers is loaded into one of 4 internal control registers. www.national.com 4 (Continued) Pin No. Pin No. Pin No. Pin LMX2336U LMX2336U LMX2336U Name 20-Pin 20-Pin 24-Pin UTCSP TSSOP CSP Pin No. LMX2335U 16-Pin TSSOP Pin No. LMX2335U 16-Pin CSP I/O Description GND 13 14 16 X X – LMX2335U: Don’t care. LMX2336U: Ground for the RF2 PLL analog circuitry. fIN RF2 14 15 17 X X I LMX2335U: Don’t care. LMX2336U: RF2 PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX2336U RF2 PLL can be driven differentially when the bypass capacitor is omitted. fIN RF2 15 16 18 12 11 I RF2 PLL prescaler input. Small signal input from the VCO. GND 16 17 19 13 12 − LMX2335U: Ground for the RF2 PLL analog and digital circuits, MICROWIRE, FoLD and oscillator circuits. LMX2336U: Ground for the RF2 PLL digital circuitry, MICROWIRE, FoLD and oscillator circuits. Do RF2 17 18 20 14 13 O RF2 PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. VP RF2 18 19 22 15 14 – RF2 PLL charge pump power supply. Must be ≥ VCC. VCC 19 20 23 16 15 – Power supply bias for the RF2 PLL analog and digital circuits, MICROWIRE, FoLD and oscillator circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. NC X X 1, 9, 13, 21 X X – LMX2335U: Don’t Care. LMX2336U: No connect. 5 www.national.com LMX2335U/LMX2336U Pin Descriptions LMX2335U/LMX2336U Ordering Information Model Temperature Range Package Description Packing NS Package Number LMX2335USLBX −40˚C to +85˚C Chip Scale Package (CSP) Tape and Reel 2500 Units Per Reel SLB16A LMX2335UTM −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) 96 Units Per Rail MTC16 LMX2335UTMX −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) Tape and Reel 2500 Units Per Reel MTC16 LMX2336USLEX −40˚C to +85˚C Ultra Thin Chip Scale Package (UTCSP) Tape and Reel 2500 Units Per Reel SLE20A LMX2336USLBX −40˚C to +85˚C Chip Scale Package (CSP) Tape and Reel 2500 Units Per Reel SLB24A LMX2336UTM −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) 73 Units Per Rail MTC20 LMX2336UTMX −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) Tape and Reel 2500 Units Per Reel MTC20 www.national.com 6 LMX2335U/LMX2336U Detailed Block Diagram 10136704 Notes: 1. VCC supplies power to the RF1 and RF2 prescalers, RF1 and RF2 feedback dividers, RF1 and RF2 reference dividers, RF1 and RF2 phase detectors, the OSCin buffer, MICROWIRE, and FoLD circuits. 2. VP RF1 and VP RF2 supply power to the charge pumps. They can be run separately as long as VP RF1 ≥ VCC and VP RF2 ≥ VCC. 3. X signifies a pin that is NOT available on the LMX2335U PLL. 7 www.national.com LMX2335U/LMX2336U Absolute Maximum Ratings (Notes 1, 2, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. −0.3V to +6.5V VP RF1 to GND −0.3V to +6.5V VP RF2 to GND −0.3V to +6.5V 130˚C/W 24-Pin CSP θJA Thermal Impedance 112˚C/W Recommended Operating Conditions (Note 1) Power Supply Voltage VCC to GND 16-Pin CSP θJA Thermal Impedance Power Supply Voltage VCC to GND +2.7V to +5.5V VP RF1 to GND VCC to +5.5V VP RF2 to GND Voltage on any pin to GND (VI) VI must be < +6.5V −0.3V to VCC+0.3V Storage Temperature Range (TS) −65˚C to +150˚C Lead Temperature (solder 4 s) (TL) 137.1˚C/W 20-Pin TSSOP θJA Thermal Impedance 114.5˚C/W −40˚C to +85˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. +260˚C 16-Pin TSSOP θJA Thermal Impedance VCC to +5.5V Operating Temperature (TA) Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations. Note 3: GND = 0V Electrical Characteristics VCC = VP RF1 = VP RF2 = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Units Typ Max 3.0 4.0 mA 3.5 4.5 mA 1.5 2.0 mA 2.0 2.5 mA 1.5 2.0 mA 1.5 2.0 1.0 10.0 µA ICC PARAMETERS ICCRF1 + RF2 ICCRF1 ICCRF2 ICC-PWDN Power Supply Current, RF1 + RF2 Synthesizers Power Supply Current, RF1 Synthesizer Only LMX2335U LMX2336U LMX2335U LMX2336U Power Supply Current, RF2 Synthesizer Only LMX2336U Powerdown Current LMX2335U/ LMX2335U LMX2336U Clock, Data and LE = GND OSCin = GND PWDN RF1 Bit = 0 PWDN RF2 Bit = 0 Clock, Data and LE = GND OSCin = GND PWDN RF1 Bit = 0 PWDN RF2 Bit = 1 Clock, Data and LE = GND OSCin = GND PWDN RF1 Bit = 1 PWDN RF2 Bit = 0 Clock, Data and LE = GND OSCin = GND PWDN RF1 Bit = 1 PWDN RF2 Bit = 1 RF1 SYNTHESIZER PARAMETERS fIN RF1 NRF1 RF1 Operating Frequency LMX2335U 100 1200 MHz LMX2336U 200 2000 MHz Prescaler = 64/65 (Note 4) 192 131135 Prescaler = 128/129 (Note 4) 384 262143 3 32767 RF1 N Divider Range RRF1 RF1 R Divider Range FφRF1 RF1 Phase Detector Frequency PfIN RF1 RF1 Input Sensitivity www.national.com 10 MHz 2.7V ≤ VCC ≤ 3.0V (Note 5) −15 0 dBm 3.0V < VCC ≤ 5.5V (Note 5) −10 0 dBm 8 (Continued) VCC = VP RF1 = VP RF2 = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units RF1 SYNTHESIZER PARAMETERS IDo RF1 SOURCE IDo RF1 SINK RF1 Charge Pump Output Source Current RF1 Charge Pump Output Sink Current VDo RF1 = VP RF1/2 IDo RF1 Bit = 0 (Note 6) -0.95 mA VDo RF1 = VP RF1/2 IDo RF1 Bit = 1 (Note 6) -3.80 mA VDo RF1 = VP RF1/2 IDo RF1 Bit = 0 (Note 6) 0.95 mA VDo RF1 = VP RF1/2 IDo RF1 Bit = 1 (Note 6) 3.80 mA IDo RF1 TRI-STATE RF1 Charge Pump Output TRI-STATE 0.5V ≤ VDo RF1 ≤ VP RF1 - 0.5V Current (Note 6) IDo RF1 SINK Vs IDo RF1 SOURCE RF1 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch VDo RF1 = VP RF1/2 TA = +25˚C (Note 7) IDo RF1 Vs VDo RF1 RF1 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage IDo RF1 Vs TA RF1 Charge Pump Output Current Magnitude Variation Vs Temperature -2.5 2.5 nA 3 10 % 0.5V ≤ VDo RF1 ≤ VP RF1 - 0.5V TA = +25˚C (Note 7) 10 15 % VDo RF1 = VP RF1/2 (Note 7) 10 % RF2 SYNTHESIZER PARAMETERS fIN RF2 NRF2 RF2 Operating Frequency LMX2335U 100 1200 MHz LMX2336U 100 1200 MHz Prescaler = 64/65 (Note 4) 192 131135 Prescaler = 128/129 (Note 4) 384 262143 3 32767 RF2 N Divider Range RRF2 RF2 R Divider Range FφRF2 RF2 Phase Detector Frequency PfIN RF2 RF2 Input Sensitivity 10 MHz 2.7V ≤ VCC ≤ 3.0V (Note 5) -15 0 dBm 3.0V < VCC ≤ 5.5V (Note 5) -10 0 dBm 9 www.national.com LMX2335U/LMX2336U Electrical Characteristics LMX2335U/LMX2336U Electrical Characteristics (Continued) VCC = VP RF1 = VP RF2 = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units RF2 SYNTHESIZER PARAMETERS IDo RF2 SOURCE IDo RF2 SINK RF2 Charge Pump Output Source Current RF2 Charge Pump Output Sink Current VDo RF2 = VP RF2/2 IDo RF2 Bit = 0 (Note 6) -0.95 mA VDo RF2 = VP RF2/2 IDo RF2 Bit = 1 (Note 6) -3.80 mA VDo RF2 = VP RF2/2 IDo RF2 Bit = 0 (Note 6) 0.95 mA VDo RF2= VP RF2/2 IDo RF2 Bit = 1 (Note 6) 3.80 mA IDo RF2 TRI-STATE RF2 Charge Pump Output TRI-STATE 0.5V ≤ VDo RF2 ≤ VP RF2 - 0.5V Current (Note 6) IDo RF2 SINK Vs IDo RF2 SOURCE RF2 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch VDo RF2 = VP RF2/2 TA = +25˚C (Note 7) IDo RF2 Vs VDo RF2 RF2 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage IDo RF2 Vs TA RF2 Charge Pump Output Current Magnitude Variation Vs Temperature -2.5 2.5 nA 3 10 % 0.5V ≤ VDo RF2 ≤ VP RF2 - 0.5V TA = +25˚C (Note 7) 10 15 % VDo RF2 = VP RF2/2 (Note 7) 10 % OSCILLATOR PARAMETERS FOSC Oscillator Operating Frequency VOSC Oscillator Sensitivity (Note 8) IOSC Oscillator Input Current VOSC = VCC = 5.5V VOSC = 0V, VCC = 5.5V 2 40 MHz 0.5 VCC VPP 100 µA -100 µA 0.8 VCC V DIGITAL INTERFACE (Data, LE, Clock, FoLD) VIH High-Level Input Voltage VIL Low-Level Input Voltage 0.2 VCC V IIH High-Level Input Current VIH = VCC = 5.5V −1.0 1.0 µA IIL Low-Level Input Current VIL = 0V, VCC = 5.5V −1.0 1.0 µA VOH High-Level Output Voltage IOH = −500 µA VOL Low-Level Output Voltage IOL = 500 µA VCC − 0.4 V 0.4 V MICROWIRE INTERFACE tCS Data to Clock Set Up Time (Note 9) 50 tCH Data to Clock Hold Time (Note 9) 10 ns tCWH Clock Pulse Width HIGH (Note 9) 50 ns tCWL Clock Pulse Width LOW (Note 9) 50 ns tES Clock to Load Enable Set Up Time (Note 9) 50 ns tEW Latch Enable Pulse Width (Note 9) 50 ns www.national.com 10 ns (Continued) VCC = VP RF1 = VP RF2 = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units PHASE NOISE CHARACTERISTICS LN(f) RF1 RF1 Synthesizer Normalized Phase Noise Contribution (Note 10) TCXO Reference Source IDo RF1 Bit = 1 -212.0 dBc/ Hz L(f) RF1 RF1 Synthesizer Single Side Band Phase Noise Measured LMX2335U fIN RF1 = 900 MHz f = 1 kHz Offset FφRF1 = 200 kHz Loop Bandwidth = 12 kHz N = 4500 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF1 Bit = 1 PWDN RF2 Bit = 1 TA = +25˚C (Note 11) -85.94 dBc/ Hz LMX2336U fIN RF1 = 1960 MHz f = 1 kHz Offset FφRF1 = 200 kHz Loop Bandwidth = 15 kHz N = 9800 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF1 Bit = 1 PWDN RF2 Bit = 1 TA = +25˚C (Note 11) -79.18 dBc/ Hz 11 www.national.com LMX2335U/LMX2336U Electrical Characteristics LMX2335U/LMX2336U Electrical Characteristics (Continued) VCC = VP RF1 = VP RF2 = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units PHASE NOISE CHARACTERISTICS LN(f) RF2 RF2 Synthesizer Normalized Phase Noise Contribution (Note 10) TCXO Reference Source IDo RF2 Bit = 1 -212.0 dBc/ Hz L(f) RF2 RF2 Synthesizer Single Side Band Phase Noise Measured LMX2335U fIN RF2 = 900 MHz f = 1 kHz Offset FφRF2 = 200 kHz Loop Bandwidth = 12 kHz N = 4500 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF2 Bit = 1 PWDN RF1 Bit = 1 TA = +25˚C (Note 11) -85.94 dBc/ Hz LMX2336U fIN RF2 = 900 MHz f = 1 kHz Offset FφRF2 = 200 kHz Loop Bandwidth = 12 kHz N = 4500 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF2 Bit = 1 PWDN RF1 Bit = 1 TA = +25˚C (Note 11) -85.94 dBc/ Hz Note 4: Some of the values in this range are illegal divide ratios (B < A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N ≥ P * (P−1), where P is the value selected for the prescaler. Note 5: Refer to the LMX2335U and LMX2336U fIN Sensitivity Test Setup section Note 6: Refer to the LMX2335U and LMX2336U Charge Pump Test Setup section Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made. Note 8: Refer to the LMX2335U and LMX2336U OSCin Sensitivity Test Setup section Note 9: Refer to the LMX2335U and LMX2336U Serial Data Input Timing section Note 10: Normalized Phase Noise Contribution is defined as : LN(f) = L(f) − 20 log (N) − 10 log (Fφ), where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and Fφ is the RF1/RF2 phase detector comparison frequency.. Note 11: The synthesizer phase noise is measured with the LMX2335TMEB/LMX2335SLBEB or LMX2336TMEB/LMX2336SLBEB/LMX2336SLEEB Evaluation boards and the HP8566B Spectrum Analyzer. www.national.com 12 LMX2335U/LMX2336U Typical Performance Characteristics Sensitivity LMX2335U fIN RF1 Input Power Vs Frequency VCC = VP RF1 = 3.0V 10136746 LMX2335U fIN RF1 Input Power Vs Frequency VCC = VP RF1 = 5.5V 10136747 13 www.national.com LMX2335U/LMX2336U Typical Performance Characteristics Sensitivity (Continued) LMX2336U fIN RF1 Input Power Vs Frequency VCC = VP RF1 = 3.0V 10136744 LMX2336U fIN RF1 Input Power Vs Frequency VCC = VP RF1 = 5.5V 10136745 www.national.com 14 LMX2335U/LMX2336U Typical Performance Characteristics Sensitivity (Continued) LMX2335U and LMX2336U fIN RF2 Input Power Vs Frequency VCC = VP RF2 = 3.0V 10136792 LMX2335U and LMX2336U fIN RF2 Input Power Vs Frequency VCC = VP RF2 = 5.5V 10136793 15 www.national.com LMX2335U/LMX2336U Typical Performance Characteristics Sensitivity (Continued) LMX2335U and LMX2336U OSCin Input Voltage Vs Frequency VCC = 3.0V 10136752 LMX2335U and LMX2336U OSCin Input Voltage Vs Frequency VCC = 5.5V 10136753 www.national.com 16 LMX2335U/LMX2336U Typical Performance Characteristics Charge Pump LMX2335U and LMX2336U RF1 Charge Pump Sweeps −40˚C ≤ TA ≤ +85˚C 10136760 17 www.national.com LMX2335U/LMX2336U Typical Performance Characteristics Charge Pump (Continued) LMX2335U and LMX2336U RF2 Charge Pump Sweeps −40˚C ≤ TA ≤ +85˚C 10136761 www.national.com 18 LMX2335U/LMX2336U Typical Performance Characteristics Input Impedance LMX2335U TSSOP and LMX2336U TSSOP fIN RF1 and fIN RF2 Input Impedance VCC = 5.5V, TA = +25˚C LMX2335U TSSOP and LMX2336U TSSOP fIN RF1 and fIN RF2 Input Impedance VCC = 3.0V, TA = +25˚C 10136766 10136767 LMX2335U CSP and LMX2336U CSP fIN RF1 and fIN RF2 Input Impedance VCC = 5.5V, TA = +25˚C LMX2335U CSP and LMX2336U CSP fIN RF1 and fIN RF2 Input Impedance VCC = 3.0V, TA = +25˚C 10136768 10136769 19 www.national.com www.national.com 20 LMX2335U/LMX2336U TSSOP and LMX2335U/LMX2336U CSP fIN RF1 and fIN RF2 Input Impedance Table Typical Performance Characteristics Input Impedance (Continued) 10136770 LMX2335U/LMX2336U LMX2335U/LMX2336U Typical Performance Characteristics Input Impedance (Continued) LMX2336U UTCSP fIN RF1 and fIN RF2 Input Impedance VCC = 5.5V, TA = +25˚C LMX2336U UTCSP fIN RF1 and fIN RF2 Input Impedance VCC = 3.0V, TA = +25˚C 10136797 10136797 21 www.national.com www.national.com 22 LMX2336U UTCSP fIN RF1 and fIN RF2 Input Impedance Table Typical Performance Characteristics Input Impedance (Continued) 10136798 LMX2335U/LMX2336U LMX2335U/LMX2336U Typical Performance Characteristics Input Impedance (Continued) LMX2335U TSSOP and LMX2336U TSSOP OSCin Input Impedance Vs Frequency TA = +25˚C 10136776 LMX2335U CSP and LMX2336U CSP OSCin Input Impedance Vs Frequency TA = +25˚C 10136777 23 www.national.com www.national.com 24 LMX2335U/LMX2336U TSSOP and LMX2335U/LMX2336U CSP OSCin Input Impedance Table Typical Performance Characteristics Input Impedance (Continued) 10136778 LMX2335U/LMX2336U LMX2335U/LMX2336U Typical Performance Characteristics Input Impedance (Continued) LMX2336U UTCSP OSCin Input Impedance Vs Frequency TA = +25˚C 101367A1 25 www.national.com www.national.com 26 Typical Performance Characteristics Input Impedance (Continued) LMX2336U UTCSP OSCin Input Impedance Table 101367A2 LMX2335U/LMX2336U LMX2335U/LMX2336U Charge Pump Current Specification Definitions 10136783 I1 = Charge Pump Sink Current at VDo = VP − ∆V I2 = Charge Pump Sink Current at VDo = VP/2 I3 = Charge Pump Sink Current at VDo = ∆V I4 = Charge Pump Source Current at VDo = VP − ∆V I5 = Charge Pump Source Current at VDo = VP/2 I6 = Charge Pump Source Current at VDo = ∆V ∆V = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to VCC and GND. Typical values are between 0.5V and 1.0V. VP refers to either VP RF1 or VP RF2 VDo refers to either VDo RF1 or VDo RF2 IDo refers to either IDo RF1 or IDo RF2 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 10136763 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch 10136764 Charge Pump Output Current Magnitude Variation Vs Temperature 10136765 27 www.national.com LMX2335U/LMX2336U Test Setups LMX2335U and LMX2336U Charge Pump Test Setup 10136750 The block diagram above illustrates the setup required to measure the LMX2336U device’s RF1 charge pump sink current. The same setup is used for the LMX2336TMEB/ LMX2336SLEEB Evaluation Boards. The RF2 charge pump measurement setup is similar to the RF1 charge pump measurement setup. The purpose of this test is to assess the functionality of the RF1 charge pump. This setup uses an open loop configuration. A power supply is connected to Vcc and swept from 2.7V to 5.5V. By means of a signal generator, a 10 MHz signal is typically applied to the fIN RF1 pin. The signal is one of two inputs to the phase detector. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. This establishes the other input to the phase detector. Alternatively, this input can be tied directly to the ground plane. With the Do RF1 pin connected to a Semiconductor Parameter Analyzer in this way, the sink, source, and TRI-STATE currents can be measured by simply toggling the Phase Detector Polarity and Charge Pump State states in Code Loader. Similarly, the LOW and HIGH currents can be measured by switching the Charge Pump Gain’s state between 1X and 4X in Code Loader. www.national.com Let Fr represent the frequency of the signal applied to the OSCin pin, which is simply zero in this case (DC), and let Fp represent the frequency of the signal applied to the fIN RF1 pin. The phase detector is sensitive to the rising edges of Fr and Fp. Assuming positive VCO characteristics; the charge pump turns ON and sinks current when the first rising edge of Fp is detected. Since Fr has no rising edge, the charge pump continues to sink current indefinitely. Toggling the Phase Detector Polarity state to negative VCO characteristics allows the measurement of the RF1 charge pump source current. Likewise, selecting TRI-STATE (TRI-STATE IDo RF1 Bit = 1) for Charge Pump State in Code Loader facilitates the measurement of the TRI-STATE current. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. The LMX2335U charge pump test setup is very much similar to the above test setup. 28 LMX2335U/LMX2336U Test Setups (Continued) LMX2335U and LMX2336U fIN Sensitivity Test Setup 10136740 the 10 MHz reference output of the signal generator. The output of the feedback divider is thus monitored and should be equal to fIN RF1 / N. The fIN RF1 input frequency and power level are then swept with the signal generator. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz. The power attenuation from the cable and the 3 dB pad must be accounted for. The feedback divider will actually miscount if too much or too little power is applied to the fIN RF1 input. Therefore, the allowed input power level will be bounded by the upper and lower sensitivity limits. In a typical application, if the power level to the fIN RF1 input approaches the sensitivity limits, this can introduce spurs and degradation in phase noise. When the power level gets even closer to these limits, or exceeds it, then the RF1 PLL loses lock. The LMX2335U fIN sensitivity test setup is very much similar to the above test setup. The block diagram above illustrates the setup required to measure the LMX2336U device’s RF1 input sensitivity level. The same setup is used for the LMX2336TMEB/ LMX2336SLEEB Evaluation Boards. The RF2 input sensitivity test setup is similar to the RF1 sensitivity test setup. The purpose of this test is to measure the acceptable signal level to the fIN RF1 input of the PLL chip. Outside the acceptable signal range, the feedback divider begins to divide incorrectly and miscount the frequency. The setup uses an open loop configuration. A power supply is connected to Vcc and the bias voltage is swept from 2.7V to 5.5V. The RF2 PLL is powered down (PWDN RF2 Bit = 1). By means of a signal generator, an RF signal is applied to the fIN RF1 pin. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. The N value is typically set to 10000 in Code Loader, i.e. RF1 N_CNTRB Word = 156 and RF1 N_CNTRA Word = 16 for PRE RF1 Bit = 0. The feedback divider output is routed to the FoLD pin by selecting the RF1 PLL N Divider Output word (FoLD Word = 6 or 14) in Code Loader. A Universal Counter is connected to the FoLD pin and tied to 29 www.national.com LMX2335U/LMX2336U Test Setups (Continued) LMX2335U and LMX2336U OSCin Sensitivity Test Setup 10136741 The block diagram above illustrates the setup required to measure the LMX2336U device’s OSCin buffer sensitivity level. The same setup is used for the LMX2336TMEB/ LMX2336SLEEB Evaluation Boards. This setup is similar to the fIN sensitivity setup except that the signal generator is now connected to the OSCin pin and both fIN pins are tied to VCC. The 51 Ω shunt resistor matches the OSCin input to the signal generator. The R counter is typically set to 1000, i.e. RF1 R_CNTR Word = 1000 or RF2 R_CNTR Word = 1000. The reference divider output is routed to the FoLD pin by selecting the RF1 PLL R Divider Output word (FoLD Word = 2 or 10) or the RF2 PLL R Divider Output word (FoLD Word = 1 or 9) in Code Loader. Similarly, a Universal www.national.com Counter is connected to the FoLD pin and is tied to the 10 MHz reference output from the signal generator. The output of the reference divider is monitored and should be equal to OSCin/ RF1 R_CNTR or OSCin/ RF2 R_CNTR. Again, VCC is swept from 2.7V to 5.5V. The OSCin input frequency and voltage level are then swept with the signal generator. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz. The LMX2335U OSCin sensitivity test setup is very much similar to the above test setup. 30 LMX2335U/LMX2336U Test Setups (Continued) LMX2335U and LMX2336U fIN Impedance Test Setup 10136779 The block diagram above illustrates the setup required to measure the LMX2336U device’s RF1 input impedance. The RF2 input impedance and reference oscillator impedance setups are very much similar. The same setup is used for a LMX2336TMEB Evaluation Board. Measuring the device’s input impedance facilitates the design of appropriate matching networks to match the PLL to the VCO, or in more critical situations, to the characteristic impedance of the printed circuit board (PCB) trace, to prevent undesired transmission line effects. Before the actual measurements are taken, the Network Analyzer needs to be calibrated, i.e. the error coefficients need to be calculated. Therefore, three standards will be used to calculate these coefficients: an open, short and a matched load. A 1-port calibration is implemented here. To calculate the coefficients, the PLL chip is first removed from the PCB. The Network Analyzer port is then connected to the RF1 OUT connector of the evaluation board and the desired operating frequency is set. The typical frequency range selected for the LMX2336U device’s RF1 synthesizer is from 100 MHz to 2000 MHz. The standards will be located down the length of the RF1 OUT transmission line. The transmission line adds electrical length and acts as an offset from the reference plane of the Network Analyzer; therefore, it must be included in the calibration. Although not shown, 0 Ω resistors are used to complete the RF1 OUT transmission line (trace). To implement an open standard, the end of the RF1 OUT trace is simply left open. To implement a short standard, a 0 Ω resistor is placed at the end of the RF1 OUT transmission line. Last of all, to implement a matched load standard, two 100 Ω resistors in parallel are placed at the end of the RF1 OUT transmission line. The Network Analyzer calculates the calibration coefficients based on the measured S11 parameters. With this all done, calibration is now complete. The PLL chip is then placed on the PCB. A power supply is connected to VCC and the bias voltage is swept from 2.7V to 5.5V. The OSCin pin is tied to the ground plane. Alternatively, the OSCin pin can be tied to VCC. In this setup, the complementary input (fIN RF1) is AC coupled to ground. With the Network Analyzer still connected to RF1 OUT, the measured fIN RF1 impedance is displayed. Note: The impedance of the reference oscillator is measured when the oscillator buffer is powered up (PWDN RF1 Bit = 0 or PWDN RF2 Bit = 0), and when the oscillator buffer is powered down (PWDN RF1 Bit = 1 and PWDN RF2 Bit = 1). The LMX2335U fIN impedance test setup is very much similar to the above test setup. Note that there are no complementary inputs in the LMX2335U device. 31 www.national.com LMX2335U/LMX2336U LMX2335U and LMX2336U Serial Data Input Timing 10136784 Notes: 1. Data is clocked into the 22-bit shift register on the rising edge of Clock 2. The MSB of Data is shifted in first. www.national.com 32 lus configuration. The output of the prescaler is used to clock the subsequent feedback dividers. The complementary inputs of both the RF1 and RF2 synthesizers can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended configuration. A 64/65 or a 128/129 prescale ratio can be selected for the both the RF1 and RF2 synthesizers. On the other hand, the LMX2335U PLL is only intended for single ended operation. Similarly, a 64/65 or a 128/129 prescale ratio can be selected for both the RF1 and RF2 synthesizers. The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX2335U or LMX2336U, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, programmable reference R and feedback N frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the reference divider to obtain a comparison reference frequency. This reference signal, Fr, is then presented to the input of a phase/frequency detector and compared with the feedback signal, Fp, which was obtained by dividing the VCO frequency down by way of the feedback divider. The phase/frequency detector measures the phase error between the Fr and Fp signals and outputs control signals that are directly proportional to the phase error. The charge pump then pumps charge into or out of the loop filter based on the magnitude and direction of the phase error. The loop filter converts the charge into a stable control voltage for the VCO. The phase/frequency detector’s function is to adjust the voltage presented to the VCO until the feedback signal’s frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency will be N times that of the comparison frequency, where N is the feedback divider ratio. 1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N COUNTERS) The programmable feedback dividers operate in concert with the prescalers to divide the input signal fIN by a factor of N. The output of the programmable reference divider is provided to the feedback input of the phase detector circuit. The divide ratio should be chosen such that the maximum phase comparison frequency (FφRF1 or FφRF2) of 10 MHz is not exceeded. The programmable feedback divider circuit is comprised of an A counter (swallow counter) and a B counter (programmble binary counter). The RF1 N_CNTRA counter and RF2 N_CNTRA counter are both 7-bit CMOS swallow counters, programmable from 0 to 127. The RF1 N_CNTRB and RF2 N_CNTRB counters are both 11-bit CMOS binary counters, programmable from 3 to 2047. A continuous integer divide ratio is achieved if N ≥ P * (P−1), where P is the value of the prescaler selected. Divide ratios less than the minimum continuous divide ratio are achievable as long as the binary programmable counter value is greater than the swallow counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections 2.5.1, 2.5.2, 2.7.1 and 2.7.2 for details on how to program the N_CNTRA and N_CNTRB counters. The following equations are useful in determining and programming a particular value of N: N = (P x N_CNTRB) + N_CNTRA fIN = N x Fφ Definitions: Fφ: RF1 or RF2 phase detector comparison frequency RF1 or RF2 input frequency fIN: N_CNTRA: RF1 or RF2 A counter value N_CNTRB: RF1 or RF2 B counter value P: Preset modulus of the dual moduIus prescaler LMX2335U RF1 synthesizer: P = 64 or 128 LMX2336U RF1 synthesizer: P = 64 or 128 LMX2335U RF2 synthesizer: P = 64 or 128 LMX2336U RF2 synthesizer: P = 64 or 128 1.1 REFERENCE OSCILLATOR INPUT The reference oscillator frequency for both the RF1 and RF2 PLLs is provided from an external reference via the OSCin pin. The reference buffer circuit supports input frequencies from 5 to 40 MHz with a minimum input sensitivity of 0.5 VPP. The reference buffer circuit has an approximate VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Typically, the OSCin pin is connected to the output of a crystal oscillator. 1.2 REFERENCE DIVIDERS (R COUNTERS) The reference dividers divide the reference input signal, OSCin, by a factor of R. The output of the reference divider circuits feeds the reference input of the phase detector. This reference input to the phase detector is often referred to as the comparison frequency. The divide ratio should be chosen such that the maximum phase comparison frequency (FφRF1 or FφRF2) of 10 MHz is not exceeded. The RF1 and RF2 reference dividers are each comprised of 15-bit CMOS binary counters that support a continuous integer divide ratio from 3 to 32767. The RF1 and RF2 reference divider circuits are clocked by the output of the reference buffer circuit which is common to both. 1.3 PRESCALERS The fIN RF1 (fIN RF2) and fIN RF1 (fIN RF2) input pins of the LMX2336U device drives the input of a bipolar, differentialpair amplifier. The output of the bipolar, differential-pair amplifier drives a chain of ECL D-type flip-flops in a dual modu- 33 www.national.com LMX2335U/LMX2336U 1.0 Functional Description LMX2335U/LMX2336U 1.0 Functional Description (Continued) 1.5 PHASE/FREQUENCY DETECTORS The RF1 and RF2 phase/frequency detectors are driven from their respective N and R counter outputs. The maximum frequency for both the RF1 and RF2 phase detector inputs is 10 MHz. The phase/frequency detector outputs control the respective charge pumps. The polarity of the pump-up or pump-down control signals are programmed using the PD_POL RF1 or PD_POL RF2 control bits, de- pending on whether the RF1 or RF2 VCO characteristics are positive or negative. Refer to Sections 2.4.2 and 2.6.2 for more details. The phase/frequency detectors have a detection range of −2π to +2π. The phase/frequency detectors also receive a feedback signal from the charge pump in order to eliminate dead zone. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 10136785 Notes: 1. 2. The minimum width of the pump-up and pump-down current pulses occur at the Do RF1 or Do RF2 pins when the loop is phase locked. The diagram assumes positive VCO characteristics, i.e. PD_POL RF1 or PD_POL RF2 = 1. 3. Fr is the phase detector input from the reference divider (R counter). 4. Fp is the phase detector input from the programmable feedback divder (N counter). 5. Do refers to either the RF1 or RF2 charge pump output. 1.6 CHARGE PUMPS The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control voltage towards VP RF1 or VP RF2 during pump-up events and towards GND during pump-down events. When locked, Do RF1 or Do RF2 are primarily in a TRI-STATE mode with small corrections occuring at the phase comparator rate. The charge pump output current magnitude can be selected by toggling the IDo RF1 or IDo RF2 control bits. 1.8 MULTI-FUNCTION OUTPUTS The FoLD output pin is a multi-function output that can be configured as the RF1 FastLock output, a push-pull analog lock detect output, counter reset, or used to monitor the output of the various reference divider (R counter) or feedback divider (N counter) circuits. The FoLD control word is used to select the desired output function. When the PLL is in powerdown mode, the FoLD output is pulled to a LOW state. A complete programming description of the multi-function output is provided in Section 2.8 FoLD. 1.8.1 Push-Pull Analog Lock Detect Output An analog lock detect status generated from the phase detector is available on the FoLD output pin if selected. The lock detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active during a comparison cycle. When viewed with an oscilloscope, narrow negative pulses are observed when the charge pump turns on. The lock detect output signal is a push-pull configuration. Three separate lock detect signals are routed to the multiplexer. Two of these monitor the ‘lock’ status of the individual synthesizers. The third detects the condition when both the RF1 and RF2 synthesizers are in a ‘locked state’. External circuitry however, is required to provide a steady DC signal to indicate when the PLL is in a locked state. Refer to Section 2.8 FoLD for details on how to program the different lock detect options. 1.7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The interface is comprised of three signal pins: Clock, Data and LE (Latch Enable). Serial data is clocked into the 22-bit shift register on the rising edge of Clock. The last two bits decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of four control registers depending on the state of the address bits. The MSB of Data is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0 Programming Description. www.national.com 34 (Continued) 1.8.2 Open Drain FastLock Output 1.9 POWER CONTROL Each synthesizer in the LMX2335U or LMX2336U is individually power controlled by device powerdown bits. The powerdown word is comprised of the PWDN RF1 (PWDN RF2) bit, in conjuction with the TRI-STATE IDo RF1 (TRI-STATE IDo RF2) bit. The powerdown control word is used to set the operating mode of the device. Refer to Sections 2.4.4, 2.5.4, 2.6.4, and 2.7.4 for details on how to program the RF1 or RF2 powerdown bits. When either the RF1 synthesizer or the RF2 synthesizer enters the powerdown mode, the respective prescaler, phase detector, and charge pump circuit are disabled. The Do RF1 (Do RF2), fIN RF1 (fIN RF2), and fIN RF1 (fIN RF2) pins are all forced to a high impedance state. The reference divider and feedback divider circuits are held at the load point during powerdown. The oscillator buffer is disabled when both the RF1 and RF2 synthesizers are powered down. The OSCin pin is forced to a HIGH state through an approximate 100 kΩ resistance when this condition exists. When either synthesizer is activated, the respective prescaler, phase detector, charge pump circuit, and the oscillator buffer are all powered up. The feedback divider, and the reference divider are held at load point. This allows the reference oscillator, feedback divider, reference divider and prescaler circuitry to reach proper bias levels. After a finite delay, the feedback and reference dividers are enabled and they resume counting in ‘close’ alignment (the maximum error is one prescaler cycle). The MICROWIRE control register remains active and capable of loading and latching data while in the powerdown mode. The LMX233xU Fastlock feature allows faster loop response time during lock aquisition. The loop response time (lock time) can be approximately halved if the loop bandwidth is doubled. In order to achieve this, the same gain/ phase relationship at twice the loop bandwidth must be maintained. This can be achieved by increasing the charge pump current from 0.95 mA (IDo RF1 Bit = 0) in the steady state mode, to 3.8 mA (IDo RF1 Bit = 1) in Fastlock. When the FoLD output is configured as a FastLock output, an open drain device is enabled. The open drain device switches in a parallel resistor R2’ to ground, of equal value to resistor R2 of the external loop filter. The loop bandwidth is effectively doubled and stability is maintained. Once locked to the correct frequency, the PLL will return to a steady state condition. Refer to Section 2.8 FoLD for details on how to configure the FoLD output to an open drain Fastlock output. 1.8.3 Counter Reset Three separate counter reset functions are provided. When the FoLD is programmed to Reset RF2 Counters, both the RF2 feedback divider and the RF2 reference divider are held at their load point. When the Reset RF1 Counters is programmed, both the RF1 feedback divider and the RF1 reference divider are held at their load point. When the Reset All Counters mode is enabled, all feedback dividers and reference dividers are held at their load point. When the device is programmed to normal operation, both the feedback divider and reference divider are enabled and resume counting in ‘close’ alignment to each other. Refer to Section 2.8 FoLD for more details. 1.8.4 Reference Divider and Feedback Divider Output The outputs of the various N and R dividers can be monitored by selecting the appropriate FoLD word. This is essential when performing OSCin or fIN sensitivity measurements. Refer to the Test Setups section for more details. Refer to Section 2.8 FoLD for more details on how to route the appropriate divider output to the FoLD pin. Synchronous Powerdown Mode In this mode, the powerdown function is gated by the charge pump. When the device is configured for synchronous powerdown, the device will enter the powerdown mode upon completion of the next charge pump pulse event. Asynchronous Powerdown Mode In this mode, the powerdown function is NOT gated by the completion of a charge pump pulse event. When the device is configured for asynchronous powerdown, the part will go into powerdown mode immediately. TRI-STATE IDo PWDN 0 0 PLL Active, Normal Operation Operating Mode 1 0 PLL Active, Charge Pump Output in High Impedance State 0 1 Synchronous Powerdown 1 1 Asynchronous Powerdown Notes: 1. TRI-STATE IDo refers to either the TRI-STATE IDo RF1 or TRI-STATE IDo RF2 bit . 2. PWDN refers to either the PWDN RF1 or PWDN RF2 bit. 35 www.national.com LMX2335U/LMX2336U 1.0 Functional Description LMX2335U/LMX2336U 2.0 Programming Description 2.1 MICROWIRE INTERFACE The 22-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 20-bit Data[19:0] Field and a 2-bit Address[1:0] Field as shown below. The Address Field is used to decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of 4 control registers depending on the state of the address bits. The MSB of Data is loaded in first. The Data Field assignments are shown in Section 2.3 CONTROL REGISTER CONTENT MAP. MSB LSB Data[19:0] Address[1:0] 21 2 1 0 2.2 CONTROL REGISTER LOCATION The address bits Address[1:0] decode the internal register address. The table below shows how the address bits are mapped into the target control register. Address[1:0] Target Field Register 0 0 RF2 R 0 1 RF2 N 1 0 RF1 R 1 1 RF1 N 2.3 CONTROL REGISTER CONTENT MAP The control register content map describes how the bits within each control register are allocated to specific control functions. www.national.com 36 PWDN RF2 FoLD1 FoLD3 PWDN RF1 RF2 N RF1 R RF1 N PRE RF1 PRE RF2 FoLD0 FoLD2 20 RF2 R 21 TRISTATE IDo RF1 TRISTATE IDo RF2 19 Reg. Most Significant Bit IDo RF1 IDo RF2 18 PD_ POL RF1 PD_ POL RF2 17 2.0 Programming Description 16 14 RF1 N_CNTRB[10:0] RF2 N_CNTRB[10:0] 15 (Continued) 13 11 Data Field 12 9 8 RF1 R_CNTR[14:0] RF2 R_CNTR[14:0] 10 SHIFT REGISTER BIT LOCATION 7 5 4 RF1 N_CNTRA[6:0] RF2 N_CNTRA[6:0] 6 3 2 0 1 1 0 0 1 0 1 0 Address Field 1 Least Significant Bit LMX2335U/LMX2336U 37 www.national.com LMX2335U/LMX2336U 2.0 Programming Description (Continued) 2.4 RF2 R REGISTER The RF2 R register contains the RF2 R_CNTR, PD_POL RF2, IDo RF2, and TRI-STATE IDo RF2 control words, in addition to two bits that compose the FoLD control word. The detailed description and programming information for each control word is discussed in the following sections. RF2 R_CNTR[14:0] Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 1 0 Address Field Data Field TRI- RF2 R PD_ STATE FoLD0 FoLD2 IDo IDo RF2 R_CNTR[14:0] POL 0 0 RF2 RF2 RF2 2.4.1 RF2 R_CNTR[14:0] RF2 SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) RF2 R[2:16] The RF2 reference divider (RF2 R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited. Divide Ratio RF2 R_CNTR[14:0] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 • 32767 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 2.4.2 PD_POL RF2 RF2 SYNTHESIZER PHASE DETECTOR POLARITY RF2 R[17] The PD_POL RF2 bit is used to control the RF2 synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit Register Location Description Function 0 PD_POL RF2 RF2 R[17] RF2 Phase Detector Polarity 1 RF2 VCO Negative Tuning Characteristics RF2 VCO Positive Tuning Characteristics RF2 VCO Characteristics 10136786 2.4.3 IDo RF2 RF2 SYNTHESIZER CHARGE PUMP CURRENT GAIN The IDo RF2 bit controls the RF2 synthesizer’s charge pump gain. Two current levels are available. Control Bit IDo RF2 www.national.com Register Location RF2 R[18] Description RF2 Charge Pump Current Gain 38 RF2 R[18] Function 0 1 LOW 0.95 mA HIGH 3.80 mA (Continued) 2.4.4 TRI-STATE IDo RF2 RF2 SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT RF2 R[19] The TRI-STATE IDo RF2 bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE IDo RF2 bit. Furthermore, the TRI-STATE IDo RF2 bit operates in conjuction with the PWDN RF2 bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function 0 TRI-STATE IDo RF2 RF2 R[19] RF2 Charge Pump TRI-STATE Current 1 RF2 Charge Pump Normal Operation RF2 Charge Pump Output in High Impedance State 2.5 RF2 N REGISTER The RF2 N register contains the RF2 N_CNTRA, RF2 N_CNTRB, PRE RF2, and PWDN RF2 control words. The RF2 N_CNTRA and RF2 N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 Data Field RF2 PWDN N RF2 PRE 1 0 Address Field RF2 N_CNTRB[10:0] RF2 N_CNTRA[6:0] 0 1 RF2 2.5.1 RF2 N_CNTRA[6:0] RF2 SYNTHESIZER SWALLOW COUNTER (A COUNTER) RF2 N[2:8] The RF2 N_CNTRA control word is used to setup the RF2 synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The RF2 N_CNTRA control word can be programmed to values ranging from 0 to 127. Divide Ratio RF2 N_CNTRA[6:0] 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 • 127 • 1 • 1 • 1 • 1 • 1 • 1 1 • 2.5.2 RF2 N_CNTRB[10:0] RF2 SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) RF2 N[9:19] The RF2 N_CNTRB control word is used to setup the RF2 synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The RF2 N_CNTRB control word can be programmed to values ranging from 3 to 2047. Divide Ratio 10 9 8 7 6 RF2 N_CNTRB[10:0] 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 • • • • • • • • • • • • 2047 1 1 1 1 1 1 1 1 1 1 1 2.5.3 PRE RF2 RF2 SYNTHESIZER PRESCALER SELECT The RF2 synthesizer utilizes a selectable dual modulus prescaler. Control Bit Register Location RF2 N[20] Description Function 0 PRE RF2 RF2 N[20] RF2 Prescaler Select 39 64/65 Prescaler Selected 1 128/129 Prescaler Selected www.national.com LMX2335U/LMX2336U 2.0 Programming Description LMX2335U/LMX2336U 2.0 Programming Description 2.5.4 PWDN RF2 (Continued) RF2 SYNTHESIZER POWERDOWN RF2 N[21] The PWDN RF2 bit is used to switch the RF2 PLL between a powered up and powered down mode. Furthermore, the PWDN RF2 bit operates in conjuction with the TRI-STATE IDo RF2 bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description PWDN RF2 RF2 N[21] RF2 Powerdown Function 0 1 RF2 PLL Active RF2 PLL Powerdown 2.6 RF1 R REGISTER The RF1 R register contains the RF1 R_CNTR, PD_POL RF1, IDo RF1, and TRI-STATE IDo RF1 control words, in addition to two bits that compose the FoLD control word. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 1 Address Field Data Field RF1 R 0 TRIPD_ STATE FoLD1 FoLD3 IDo IDo RF1 R_CNTR[14:0] POL 1 0 RF1 RF1 RF1 2.6.1 RF1 R_CNTR[14:0] RF1 SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) RF1 R[2:16] The RF1 reference divider (RF1 R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited. Divide Ratio RF1 R_CNTR[14:0] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 • • • • • • • • • • • • • • • • 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2.6.2 PD_POL RF1 RF1 SYNTHESIZER PHASE DETECTOR POLARITY RF1 R[17] The PD_POL RF1 bit is used to control the RF1 synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit Register Location Description Function 0 PD_POL RF1 RF1 R[17] RF1 Phase Detector Polarity RF1 VCO Negative Tuning Characteristics RF1 VCO Characteristics 10136782 www.national.com 40 1 RF1 VCO Positive Tuning Characteristics (Continued) 2.6.3 IDo RF1 RF1 SYNTHESIZER CHARGE PUMP CURRENT GAIN The IDo RF1 bit controls the RF1 synthesizer’s charge pump gain. Two current levels are available. Control Bit Register Location IDo RF1 RF1 R[18] Description RF1 R[18] Function RF1 Charge Pump Current Gain 0 1 LOW 0.95 mA HIGH 3.80 mA RF1 SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT RF1 R[19] 2.6.4 TRI-STATE IDo RF1 The TRI-STATE IDo RF1 bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE IDo RF1 bit. Furthermore, the TRI-STATE IDo RF1 bit operates in conjuction with the PWDN RF1 bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location TRI-STATE IDo RF1 RF1 R[19] Description Function 0 RF1 Charge Pump TRI-STATE Current 1 RF1 Charge Pump Normal Operation RF1 Charge Pump Output in High Impedance State 2.7 RF1 N REGISTER The RF1 N register contains the RF1 N_CNTRA, RF1 N_CNTRB, PRE RF1, and PWDN RF1 control words. The RF1 N_CNTRA and RF1 N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 PRE 0 Address Field Data Field RF1 PWDN N RF1 1 RF1 N_CNTRB[10:0] RF1 N_CNTRA[6:0] 1 1 RF1 2.7.1 RF1 N_CNTRA[6:0] RF1 SYNTHESIZER SWALLOW COUNTER (A COUNTER) RF1 N[2:8] The RF1 N_CNTRA control word is used to setup the RF1 synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The RF1 N_CNTRA control word can be programmed to values ranging from 0 to 127. Divide Ratio RF1 N_CNTRA[6:0] 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 • • • • • • • • 127 1 1 1 1 1 1 1 2.7.2 RF1 N_CNTRB[10:0] RF1 SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) RF1 N[9:19] The RF1 N_CNTRB control word is used to setup the RF1 synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The RF1 N_CNTRB control word can be programmed to values ranging from 3 to 2047. Divide Ratio 10 9 8 7 6 RF1 N_CNTRB[10:0] 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 • 2047 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 41 www.national.com LMX2335U/LMX2336U 2.0 Programming Description LMX2335U/LMX2336U 2.0 Programming Description 2.7.3 PRE RF1 (Continued) RF1 SYNTHESIZER PRESCALER SELECT RF1 N[20] The RF1 synthesizer utilizes a selectable dual modulus prescaler. Control Bit Register Location Description Function 0 PRE RF1 2.7.4 PWDN RF1 RF1 N[20] RF1 Prescaler Select 64/65 Prescaler Selected 1 128/129 Prescaler Selected RF1 SYNTHESIZER POWERDOWN RF1 N[21] The PWDN RF1 bit is used to switch the RF1 PLL between a powered up and powered down mode. Furthermore, the PWDN RF1 bit operates in conjuction with the TRI-STATE IDo RF1 bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function 0 PWDN RF1 www.national.com RF1 N[21] RF1 Powerdown 42 RF1 PLL Active 1 RF1 PLL Powerdown (Continued) 2.8 FoLD[3:0] MULTI-FUNCTION OUTPUT SELECT [RF1 R[20], RF2 R[20], RF1 R [21], RF2 R[21]] The FoLD control word is used to select which signal is routed to the FoLD pin. FoLD3 FoLD2 FoLD1 FoLD0 0 0 0 0 LOW Logic State Output FoLD Output State 0 0 0 1 RF2 PLL R Divider Output, Push-Pull Output 0 0 1 0 RF1 PLL R Divider Output, Push-Pull Output 0 0 1 1 Open Drain Fastlock Output 0 1 0 0 RF2 PLL Analog Lock Detect, Push-Pull Output 0 1 0 1 RF2 PLL N Divider Output, Push-Pull Output 0 1 1 0 RF1 PLL N Divider Output, Push-Pull Output 0 1 1 1 Reset RF2 Counters, LOW Logic State Output 1 0 0 0 RF1 Analog Lock Detect, Push-Pull Output 1 0 0 1 RF2 PLL R Divider Output, Push-Pull Output 1 0 1 0 RF1 PLL R Divider Output, Push-Pull Output 1 0 1 1 Reset RF1 Counters, LOW Logic State Output 1 1 0 0 RF1 and RF2 Analog Lock Detect, Push-Pull Output 1 1 0 1 RF2 PLL N Divider Output, Push-Pull Output 1 1 1 0 RF1 PLL N Divider Output, Push-Pull Output 1 1 1 1 Reset All Counters, LOW Logic State Output 43 www.national.com LMX2335U/LMX2336U 2.0 Programming Description LMX2335U/LMX2336U Physical Dimensions inches (millimeters) unless otherwise noted 16-Pin Thin Shrink Small Outline Package (TM) NS Package Number MTC16 www.national.com 44 LMX2335U/LMX2336U Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Pin Thin Shrink Small Outline Package (TM) NS Package Number MTC20 45 www.national.com LMX2335U/LMX2336U Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Pin Chip Scale Package (SLB) NS Package Number SLB16A www.national.com 46 LMX2335U/LMX2336U Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Pin Chip Scale Package (SLB) NS Package Number SLB24A 47 www.national.com LMX2335U/LMX2336U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Pin Ultra Thin Chip Scale Package (SLE) NS Package Number SLE20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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