June 1999
LMX2335L/LMX2336L
PLLatinum™ Low Power Dual Frequency Synthesizer for
RF Personal Communications
LMX2335L
LMX2336L
1.1 GHz/1.1 GHz
2.0 GHz/1.1 GHz
Features
General Description
The LMX2335L and LMX2336L are monolithic, integrated
dual frequency synthesizers, including two high frequency
prescalers, and are designed for applications requiring two
RF phase-lock loops. They are fabricated using National’s
0.5µ ABiC V silicon BiCMOS process.
The LMX2335L/36L contains two dual modulus prescalers. A
64/65 or a 128/129 prescaler can be selected for each RF
synthesizer. A second reference divider chain is included in
the IC for improved system noise. The LMX2335L/36L combined with a high quality reference oscillator, two loop filters,
and two external voltage controlled oscillators generates
very stable low noise RF local oscillator signals.
Serial data is transferred into the LMX2335L/36L via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX2335L/36L feature very
low current consumption; LMX2335L 4.0 mA at 5V,
LMX2336L 5.5 mA at 5V. The LMX2335L is available in SO,
TSSOP and CSP 16-pin surface mount plastic packages.
The LMX2336L is available in a TSSOP 20-pin and CSP
24-pin surface mount plastic package.
n Ultra low current consumption
n 2.7V to 5.5V operation
n Selectable synchronous and asynchronous powerdown
mode:
ICC = 1 µA (typ)
n Dual modulus prescaler: 64/65 or 128/129
n Selectable charge pump TRI-STATE ® mode
n Selectable charge pump current levels
n Selectable Fastlock™ mode
n Upgrade and compatible to LMX2335/36
n Small-outline, plastic, surface mount TSSOP package
n LMX2336 available in CSP package
Applications
n Cellular telephone systems (AMPS, ETACS, RCR-27)
n Cordless telephone systems
(DECT, ISM , PHS, CT-1+)
n Personal Communication Systems
(DCS-1800, PCN-1900)
n Dual Mode PCS phones
n Cable TV Tuners (CATV)
n Other wireless communication systems
Functional Block Diagram
DS012807-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS012807
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LMX2335L/LMX2336L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal
Communications
PRELIMINARY
Connection Diagrams
LMX2335L
(Top View)
LMX2336L
(Top View)
DS012807-2
Order Number LMX2335LM or LM2335LTM
NS Package Number M16A and MTC16
DS012807-3
Order Number LMX2336LTM
NS Package Number MTC20
LMX2335L
(Top View)
LMX2336L
(Top View)
DS012807-38
Order Number LMX2335LSLB
NS Package Number SLB16A
DS012807-36
Order Number LMX2336LSLB
NS Package Number SLB24A
Pin Descriptions
Pin No.
2336LTM
Pin No.
Pin No.
2336LSLB 2335LTM
1
24
1
Pin No.
2335LSLB
16
Pin
I/O
Description
Name
VCC1
2
2
2
1
Vp1
3
3
3
2
D o1
4
4
4
3
GND
Power supply voltage input for RF1 analog and RF1 digital
circuits. Input may range from 2.7V to 5.5V. VCC1 must equal
VCC2. Bypass capacitors should be placed as close as possible
to this pin and be connected directly to the ground plane.
Power supply for RF1 charge pump. Must be ≥ VCC.
O
RF1 charge pump output. For connection to a loop filter for
driving the input of an external VCO.
LMX2335L: Ground for RF1 analog and RF1 digital circuits.
LMX2336L: Ground for RF digital circuits.
5
5
5
4
fIN 1
I
RF1 prescaler input. Small signal input from the VCO.
6
6
X
X
/fIN 1
I
RF1 prescaler complementary input. A bypass capacitor should
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with loss of
some sensitivity.
7
7
X
X
GND
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Ground for RF1 analog circuitry.
2
Pin Descriptions
Pin No.
2336LTM
Pin No.
(Continued)
Pin No.
2336LSLB 2335LTM
Pin No.
Pin
2335LSLB
Name
8
8
6
5
OSCin
I/O
I
Description
Oscillator input. The input has a VCC/2 input threshold and can
be driven from an external CMOS or TTL logic gate.
9
10
7
6
OSCout
O
Oscillator output.
10
11
8
7
FoLD
O
Multiplexed output of the programmable or reference dividers,
lock detect signals and Fastlock mode. CMOS output (see
Programmable Modes).
11
12
9
8
Clock
I
High impedance CMOS Clock input. Data for the various latches
is clocked in on the rising edge, into the 20-bit shift register.
12
14
10
9
Data
I
Binary serial data input. Data entered MSB first. The last two bits
are the control bits. High impedance CMOS input.
13
15
11
10
LE
I
Load enable high impedance CMOS input. When LE goes HIGH,
data stored in the shift registers is loaded into one of the 4
appropriate latches (control bit dependent).
14
16
X
X
GND
15
17
X
X
/fIN2
I
RF2 prescaler complementary input. A bypass capacitor should
be placed as close as possible to this pin and be connected
directly to the ground plane. Capacitor is optional with loss of
some sensitivity.
I
RF2 prescaler input. Small signal input from the VCO.
16
18
12
11
fIN 2
17
19
13
12
GND
18
20
14
13
Do 2
Ground for RF2 analog circuitry.
LMX2335L: Ground for RF2 analog, RF2 digital, MICROWIRE,
FoLD and Oscillator circuits. LMX2336L: Ground for IF digital,
MICROWIRE, FoLD and oscillator circuits.
O
RF2 charge pump output. For connection to a loop filter for
driving the input of an external VCO.
19
22
15
14
Vp2
Power supply for RF2 charge pump. Must be ≥ VCC.
20
23
16
15
VCC2
Power supply voltage input for RF2 analog, RF2 digital,
MICROWIRE, FoLD and oscillator circuits. Input may range from
2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should
be placed as close as possible to this pin and be connected
directly to the ground plane.
X
1, 9, 13,
21
X
X
NC
No connect.
3
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Block Diagram
DS012807-4
Note 1: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase
detector, R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same
voltage level.
Note 2: VP1 and VP2 can be run separately as long as VP ≥ VCC.
LMX2335L Pin # → 8/10 ← LMX2336L Pin #
Pin Name → FoLD
X signifies a function not bonded out to a pin
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4
Absolute Maximum Ratings (Notes 1, 2)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
VCC
VP
Voltage on Any Pin
with GND = 0V (VI)
Storage Temperature Range (TS)
Lead Temperature (solder 4 sec.) (TL)
Power Supply Voltage
VCC
VP
Operating Temperature (TA)
−0.3V to +6.5V
−0.3V to +6.5V
2.7V to 5.5V
VCC to +5.5V
−40˚C to +85˚C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
−0.3V to VCC +0.3V
−65˚C to +150˚C
+260˚C
Note 2: This device is a high performance RF integrated circuit with an ESD
rating < 2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected work stations.
Electrical Characteristics
VCC = 5.0V, VP = 5.0V; TA = 25˚C, except as specified
Symbol
Parameter
Conditions
Value
Min
ICC
Power Supply
LMX2335L
Current
VCC = 2.7V to 5.5V
Units
Typ
Max
4.0
5.2
mA
RF1 and RF2
ICC
LMX2335L RF1 only
2.0
2.6
mA
ICC
LMX2336L
5.5
7
mA
3.3
4.3
mA
1.1
GHz
RF1 and RF2
LMX2336L RF1 only
fIN 1
fIN 2
Operating
Frequency
fIN1
LMX2335L
0.100
0.050
1.1
GHz
LMX2336L
0.200
2.0
GHz
1.1
GHz
fIN2
0.050
ICC-PWDN
Powerdown Current
fOSC
Oscillator Frequency
LMX2335L/2336L
fOSC
fφ
Maximum Phase Detector Frequency
PfIN
RF Input Sensitivity
PfIN
VCC = 5.5V
With resonator load on OSCout
5
No load on OSCout
5
VCC = 3.0V, f > 100 MHz
VCC = 5.0V, f > 100 MHz
Oscillator Sensitivity
OSCin
VIH
High-Level Input Voltage
(Note 4)
VIL
Low-Level Input Voltage
IIH
High-Level Input Current
IIL
Low-Level Input Current
IIH
Oscillator Input Current
(Note 4)
VIH = VCC = 5.5V (Note 4)
VIL = 0V, VCC = 5.5V (Note 4)
VIH = VCC = 5.5V
IIL
Oscillator Input Current
IDo-SOURCE
Charge Pump Output Current
IDo-SOURCE
IDo-SINK
MHz
40
0
0
0.5
High-Level Output Voltage
VOL
Low-Level Output Voltage
IOL = 500 µA
5
dBm
VPP
0.8 VCC
V
−1.0
−1.0
0.2 VCC
V
1.0
µA
1.0
µA
100
−5.0
MHz
MHz
−10
−100
VOH
Charge Pump
TRI-STATE Current
µA
20
−15
VIL = 0V, VCC = 5.5V
VDo = VP/2, ICPo = LOW
(Note 3)
VDo = VP/2, ICPo = LOW
(Note 3)
VDo = VP/2, ICPo = HIGH
(Note 3)
VDo = VP/2, ICPo = HIGH
(Note 3)
0.5V ≤ VDo ≤ VCC − 0.5V
T = 25˚C
IOH = −500 µA
IDo-TRI
10
10
VOSC
IDo-SINK
1
µA
µA
−1.25
mA
1.25
mA
−4.25
mA
4.25
mA
5.0
VCC −
0.4
nA
V
0.4
V
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Electrical Characteristics
(Continued)
VCC = 5.0V, VP = 5.0V; TA = 25˚C, except as specified
Symbol
Parameter
Conditions
Value
Min
Typ
Units
Max
tCS
Data to Clock Set Up Time
See Data Input Timing
50
ns
tCH
Data to Clock Hold Time
See Data Input Timing
10
ns
tCWH
Clock Pulse Width High
See Data Input Timing
50
ns
tCWL
Clock Pulse Width Low
See Data Input Timing
50
ns
tES
Clock to Load Enable Set Up Time
See Data Input Timing
50
ns
tEW
Load Enable Pulse Width
See Data Input Timing
50
ns
Note 3: See PROGRAMMABLE MODES for ICPo description.
Note 4: Clock, Data and LE does not include fIN1, fIN2 and OSCin.
Charge Pump Current Specification Definitions
DS012807-18
I1 = CP sink current at VDo = VP − ∆V
I2 = CP sink current at VDo = VP/2
I3 = CP sink current at VDo = ∆V
I4 = CP source current at VDo = VP − ∆V
I5 = CP source current at VDo = VP/2
I6 = CP source current at VDo = ∆V
V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V.
1. IDo vs VDo = Charge Pump Output Current magnitude variation vs Voltage =
[1⁄2 * {|I1| − |I3|}]/[1⁄2 * {|I1| + |I3|}] * 100% and [1⁄2 * {|I4| − |I6|}]/[1⁄2 * {|I4| + |I6|}] * 100%
2. IDo-sink vs IDo-source = Charge Pump Output Current Sink vs Source Mismatch =
[|I2| − |I5|]/[1⁄2 * {|I2| + |I5|}] * 100%
3. IDo vs TA = Charge Pump Output Current magnitude variation vs Temperature =
[|I2 @ temp| − |I2 @ 25˚C|]/|I2 @ 25˚C| * 100% and [|I5 @ temp| − |I5 @ 25˚C|]/|I5 @ 25˚C| * 100%
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6
RF Sensitivity Test Block Diagram
DS012807-19
Note 5: N = 10,000R = 50P = 64
Note 6: Sensitivity limit is reached when the error of the divided RF output, FoLD, is ≥ 1 Hz.
Typical Performance Characteristics
ICC vs VCC
LMX2335L
ICC vs VCC
LMX2336L
DS012807-20
Charge Pump Current vs Do Voltage
Icp = HIGH
DS012807-21
Charge Pump Current vs Do Voltage
Icp = LOW
DS012807-22
DS012807-23
7
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Typical Performance Characteristics
(Continued)
LMX2335L Input Impedance (for SO package)
VCC = 2.7V to 5.5V, IIN = 50 MHz to 1.5 GHz
LMX2336L Input Impedance (for TSSOP package)
VCC = 2.7V to 5.5V, fIN = 50 MHz to 2.5 GHz
DS012807-24
Marker
Marker
Marker
Marker
1
2
3
4
=
=
=
=
1 GHz, Real = 94, Imaginary = −118
1.2 GHz, Real = 72, Imaginary = −88
1.5 GHz, Real = 53, Imaginary = −45
500 MHz, Real = 201, Imaginary = −224
DS012807-25
Marker
Marker
Marker
Marker
1
2
3
4
=
=
=
=
1 GHz, Real = 97, Imaginary = −146
1.89 GHz, Real = 43, Imaginary = −67
2.5 GHz, Real = 30, Imaginary = −33
500 MHz, Real = 189, Imaginary = −233
LMX2335L Input Impedance (for TSSOP package)
VCC = 2.7V to 5.5V, fIN = 50 MHz to 2.5 GHz
DS012807-31
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8
Typical Performance Characteristics
(Continued)
IDO TRI-STATE
vs Do Voltage
LMX2335L RF1 Sensitivity vs Frequency
DS012807-27
DS012807-26
LMX2335L RF2 Sensitivity vs Frequency
LMX2336L RF1 Sensitivity vs Frequency
DS012807-28
LMX2336L RF2 Sensitivity vs Frequency
DS012807-29
Oscillator Input Sensitivity vs Frequency
DS012807-30
DS012807-37
9
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Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate
latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored
in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits.
The DATA is transferred into the counters as follows:
Control Bits
DATA Location
C1
C2
0
0
RF2 R Counter
0
1
RF1 R Counter
1
0
RF2 N Counter
1
1
RF1 N Counter
DS012807-5
PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS)
If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
DS012807-6
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
R
R
R
R
R
R
R
R
R
R
Ratio 15 14 13 12 11 10
R
R
R
R
R
9
8
7
6
5
4
3
2
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
•
32767
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
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10
•
Functional Description
(Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below.
DS012807-7
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
•
127
•
1
•
1
•
1
•
1
•
1
•
1
1
Ratio
A
•
Notes:
Divide ratio: 0 to 127
B≥A
A<P
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
•
2047
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
1
Ratio
B
•
Note:
Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B≥A
PULSE SWALLOW FUNCTION
fVCO = [(P x B) + A] x fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B:
A:
fOSC:
R:
P:
Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
Preset divide ratio of binary 7-bit swallow counter
(0 ≤ A ≤ P; A ≤ B)
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
Preset modulus of dual moduIus prescaler (P = 64 or 128)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump tristate
and the output of the FoLD pin. The prescaler and power down modes are selected with bits N19 and N20. The programmable
modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and Table 3.
11
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Functional Description
(Continued)
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
R19
R20
0
0
RF2 Phase
RF2 ICPo
RF2 Do
RF2 LD
RF2 Fo
0
1
RF1 LD
RF1 Fo
Detector Polarity
RF1 Phase
TRI-STATE
RF1 ICPo
Detector Polarity
RF1 Do
TRI-STATE
C1
C2
N19
N20
1
0
RF2
Pwdn
1
1
Prescaler
RF2
RF1
Pwdn
Prescaler
RF1
TABLE 2. Mode Select Truth Table
Phase Detector
Do TRI-STATE
ICPo
RF1
RF2
Pwdn
Polarity (Note 9)
(Note 7)
(Note 8)
Prescaler
Prescaler
(Note 7)
0
Negative
Normal Operation
LOW
64/65
64/65
pwrd up
1
Positive
TRI-STATE
HIGH
128/129
128/129
pwrd dn
Note 7: Refer to POWERDOWN OPERATION in Functional Description.
Note 8: The ICPo LOW current state = 1/4 x ICPo HIGH current.
Note 9: PHASE DETECTOR POLARITY
Depending upon VCO characteristics, the R16 bits should be set accordingly:
When VCO characteristics are positive like (1), R16 should be set HIGH;
When VCO characteristics are negative like (2), R16 should be set LOW.
VCO Characteristics
DS012807-8
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12
Functional Description
(Continued)
TABLE 3. The FoLD Output Truth Table
RF1 R[19]
RF2 R[19]
RF1 R[20]
RF2 R[20]
FoLD
(RF1 LD)
(RF2 LD)
(RF1 FO)
(RF2 FO)
Output State
0
0
0
0
Disabled (Note 10)
0
1
0
0
RF2 Lock Detect (Note 11)
1
0
0
0
RF1 Lock Detect (Note 11)
1
1
0
0
RF1/RF2 Lock Detect (Note 11)
X
0
0
1
RF2 Reference Divider Output
X
0
1
0
RF1 Reference Divider Output
X
1
0
1
RF2 Programmable Divider Output
X
1
1
0
RF1 Programmable Divider Output
0
0
1
1
Fastlock (Note 12)
0
1
1
1
RF2 Counter Reset (Note 13)
1
0
1
1
RF1 Counter Reset (Note 13)
1
1
1
1
RF1 and RF2 Counter Reset (Note 13)
X — don’t care condition
Note 10: When the FoLD output is disabled it is actively pulled to a low logic state.
Note 11: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.
Note 12: The Fastlock mode utilized the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop’s Icpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
Note 13: The RF2 counter reset mode resets RF2 PLL’s R and N counters and brings RF2 charge pump output to a TRI-STATE condition. The RF1 counter reset
mode resets RF1 PLL’s R and N counters and brings RF1 charge pump output to a TRI-STATE condition. The RF1 and RF2 counter reset mode resets all counters
and brings both charge pump output to a TRI-STATE condition. Upon removal of the Reset bits the N counter resumes counting in “close” alignment with the R
counter. (The maximum error is one prescaler cycle).
disabled until both IF and RF powerdown bits are activated.
The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown modes.
The device returns to an actively powered up condition in either synchronous ar asynchronous modes immediately upon
LE latching LOW data into bit N20.
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are
both available by microwire selection. Synchronously powerdown occurs if the respective loop’s R18 bit (Do TRI-STATE)
is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous
powerdown occurs if the loop’s R18 bit is HI when its N20 bit
becomes HI.
In the synchronous powerdown mode, the powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program bit N20 is
loaded, the part will go into powerdown mode when the
charge pump reaches a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers
down immediately after the LE pin latches in a HI condition
on the powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions
in either synchronous or asynchronous modes forces the respective loop’s R & N dividers to their load state condition
and debiasing of it’s respective Fin input to a high impedance state. The oscillator circuitry function does not become
Powerdown Mode Select Table
13
R18
N20
0
0
PLL Active
Powerdown Status
1
0
PLL Active (Charge Pump Output
TRI-STATE)
0
1
Synchronous Powerdown Initiated
1
1
Asynchronous Powerdown Initiated
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Functional Description
(Continued)
SERIAL DATA INPUT TIMING
DS012807-9
Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
tCS = Data to Clock Set Up Time
tCH = Data to Clock Hold Time
tCWH = Clock Pulse Width High
tCWL = Clock Pulse Width Low
tES = Clock to Load Enable Set Up Time
tEW = Load Enable Pulse Width
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with
amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS012807-10
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.
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14
Typical Application Example
DS012807-11
Operational Notes:
*
**
VCO is assumed AC coupled.
RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω
to 200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω. fIN IF impedances are higher.
***
50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a
CMOS clock is used and no terminating resistor is required. OSCinmay be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below).
****
R2 configured FoLD for use in FastLock mode.
***** Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling.
DS012807-12
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board
layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
15
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Application Information
A block diagram of the basic phase locked loop is shown in Figure 1.
DS012807-13
FIGURE 1. Conventional PLL Architecture
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (KVCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, WHILE
the complex impedance of the filter is given in equation 2.
(4)
From Equation (3) we can see that the phase term will be dependent on the single pole and zero such that the phase
margin is determined in Equation (1).
(5)
φ(ω) = tan−1 (ω • T2) −tan−1 (ω • T1) + 180˚C
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in Equation (4) with a solid trace. The parameter φp shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
the loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase — just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
Figure 4 over to a different cutoff frequency, illustrated by
dotted line, without affecting the relative open loop gain and
phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in
the gain and phase equations 4 and 5 will have to compensate by the corresponding “1/w” or “1/w2” factor. Examination
of equations 3 and 5 indicates the damping resistor variable
R2 could be chosen to compensate with “w” terms for the
phase margin. This implies that another resistor of equal
value to R2 will need to be switched in parallel with R2 during
the initial lock period. We must also insure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp’ =
2 wp. KVCO, Kφ, N, or the net product of these terms can be
changed by a factor of 4, to counteract with w2 term present
in the denominator of equation 3. The Kφ term was chosen to
complete the transformation because it can readily be
switched between 1X and 4X values. This is accomplished
by increasing the charge pump output current from 1 mA in
the standard mode to 4 mA in Fastlock.
DS012807-14
FIGURE 2. PLL Linear Model
DS012807-15
FIGURE 3. Passive Loop Filter
(1)
(2)
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
(3)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time contants T1 and T2, and
the design constants Kφ, KVCO, and N.
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16
Application Information
ations. The device configuration ensures that as long as a
second identical damping resistor is wired in appropriately,
the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise
operation by sending a MICROWIRE instruction with the
RF1 ICPo bit set low. This transition does not affect the
charge on the loop filter capacitors and is enacted synchronous with the charge pump output. This creates a nearly
seamless change between Fastlock and standard mode.
(Continued)
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in National Semiconductors LMX2335L/36L PLL is shown in Figure 5. When a new frequency is loaded, and the RF1 ICPo bit
is set high, the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error while an
open drain NMOS on chip device switches in a second R2
resistor element to ground. The user calculates the loop filter
component values for the normal steady state consider-
DS012807-16
FIGURE 4. Open Loop Response Bode Plot
DS012807-17
FIGURE 5. Fastlock PLL Architecture
17
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Pin Chip Scale Package
Order Number LMX2336LSLB
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2336LSLBX
NS Package Number SLB24A
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18
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
JEDEC 16-Lead (0.150" Wide) Small Outline Molded Package (M)
Order Number LMX2335LM
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335LMX
NS Package Number M16A
19
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TM)
Order Number LMX2335LTM
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335LTMX
NS Package Number MTC16
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20
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2336LTM
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2336LTMX
NS Package Number MTC20
21
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LMX2335L/LMX2336L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal
Communications
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Pin Chip Scale Package
Order Number LMX2335LSLB
*For Tape and Reel (2500 Units Per Reel)
Order Number LMX2335LSLBX
NS Package Number SLB16A
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