54ACTQ841 Quiet Series 10-Bit Transparent Latch with TRI-STATE ® Outputs General Description Features The ’ACTQ841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The ’841 is a 10-bit transparent latch, a 10-bit version of the ’373. The ’ACTQ841 utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance, FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. n Guaranteed simultaneous switching noise level and dynamic threshold performance n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Improved latch-up immunity n Outputs source/sink 24 mA n ’ACTQ841 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) 5962-92200 Logic Symbols DS100250-1 DS100250-2 Pin Names Description D0–D9 Data Inputs O0–O9 TRI-STATE Outputs OE Output Enable LE Latch Enable GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100250 www.national.com 54ACTQ841 Quiet Series 10-Bit Transparent Latch with TRI-STATE Outputs August 1998 Connection Diagrams Pin Assignment for DIP and Flatpack Pin Assignment for LCC DS100250-4 DS100250-3 Functional Description The ’ACTQ841 consists of ten D-type latches with TRI-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Function Table Inputs OE Internal Output LE D Q O Function X X X X Z H H L L Z High Z High Z H H H H Z High Z H L X NC Z Latched L H L L L Transparent L H H H H Transparent L L X NC NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance NC = No Change Logic Diagram DS100250-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) DC Latch-Up Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V ± 300 mA 175˚C Recommended Operating Conditions −20 mA +20 mA −0.5V to VCC + 0.5V Supply Voltage (VCC) ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 2: All outputs loaded; thresholds on input associated with output under test. DC Electrical Characteristics for ’ACTQ Family Devices Symbol Parameter 54ACTQ TA = VCC (V) Units Conditions −55˚C to +125˚C Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IOL = −24 mA IOL = −24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA 5.5 ± 10.0 µA VI = VIL, VIH VO = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V Leakage Current IOZ Maximum TRI-STATE Leakage Current ICCT Maximum ICC/Input 3 www.national.com DC Electrical Characteristics for ’ACTQ Family Devices Symbol Parameter 54ACTQ TA = VCC (V) (Continued) Units Conditions −55˚C to +125˚C Guaranteed Limits IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current (Note 4) 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 160.0 µA VIN = VCC 5.0 1.5 V (Note 6) 5.0 −1.2 V (Note 6) Supply Current VOLP Quiet Output or GND (Note 5) Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) (Note 7) Min tPLH, Propagation Delay tPHL Dn to On tPLH, Propagation Delay tPHL LE to On tPZH, Output Enable Time tPZL OE to On tPHZ, Output Disable Time tPLZ OE to On Fig. to +125˚C CL = 50 pF 5.0 5.0 5.0 5.0 Units No. ns Figure 4 ns Figure 4 ns Figure 5 ns Figure 5 Max 2.0 9.5 2.0 11.0 2.0 11.0 2.0 11.0 1.5 11.0 1.5 13.0 1.5 8.5 1.5 5.5 Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Fig. Units No. Guaranteed Minimum tS Setup Time, HIGH or LOW 5.0 3.0 ns Figure 7 5.0 1.5 ns Figure 7 5.0 4.0 ns Figure 6 Dn to LE tH Hold Time, HIGH or LOW Dn to LE tW LE Pulse Width, HIGH Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. www.national.com 4 Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 85.0 pF Conditions VCC = OPEN VCC = 5.0V Capacitance AC Loading DS100250-9 DS100250-10 FIGURE 2. Test Input Signal Levels *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms DS100250-11 DS100250-13 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. TRI-STATE Output HIGH and LOW Enable and Disable Time 5 www.national.com AC Waveforms (Continued) DS100250-14 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100250-12 FIGURE 6. Propagation Delay, Pulse Width Waveforms www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 28-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 7 www.national.com 54ACTQ841 Quiet Series 10-Bit Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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