54AC374 • 54ACT374 Octal D Flip-Flop with TRI-STATE ® Outputs General Description The ’AC/’ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. Features n ICC and IOZ reduced by 50% n Buffered positive edge-triggered clock n TRI-STATE outputs for bus-oriented applications Outputs source/sink 24 mA See ’273 for reset version See ’377 for clock enable version See ’373 for transparent latch version See ’574 for broadside pinout version See ’564 for broadside pinout version with inverted outputs n ’ACT374 has TTL-compatible inputs n Standard Military Drawing (SMD) — ’AC374: 5962-87694 — ’ACT374: 5962-87631 n n n n n n Logic Symbols IEEE/IEC DS100289-1 DS100289-2 Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE TRI-STATE Output Enable Input O0–O7 TRI-STATE Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100289 www.national.com 54AC374 • 54ACT374 Octal D Flip-Flop with TRI-STATE Outputs August 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100289-4 DS100289-3 Functional Description The ’AC/’ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs Outputs Dn CP OE On H N L H L N L L X X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition Logic Diagram DS100289-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol VIH VIL VOH Parameter VCC 54AC TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High 3.0 2.1 Level Input 4.5 3.15 Voltage 5.5 3.85 Maximum Low 3.0 0.9 Level Input 4.5 1.35 Voltage 5.5 1.65 Minimum High 3.0 2.9 Level Output 4.5 4.4 Voltage 5.5 5.4 Units Conditions VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low 3.0 0.1 Level Output 4.5 0.1 Voltage 5.5 0.1 −12 mA V IOH −24 mA −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IIN Maximum Input 3.0 0.50 4.5 0.50 12 mA V IOL 24 mA 5.5 0.50 5.5 ± 1.0 µA VI = VCC, GND 24 mA 5.5 ± 5.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Leakage Current IOZ Maximum TRI-STATE Current 3 www.national.com DC Characteristics for ’AC Family Devices Symbol IOLD Parameter IOHD (Note 3) Minimum Dynamic Output Current ICC Maximum Quiescent (Continued) VCC 54AC TA = −55˚C to +125˚C (V) Guaranteed Limits 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 5.5 80.0 µA VIN = VCC Units Supply Current Conditions or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL IIN Maximum Low Level Output Voltage Maximum Input VCC 54ACT TA = −55˚C to +125˚C (V) Guaranteed Limits 4.5 2.0 5.5 2.0 4.5 0.8 5.5 0.8 4.5 4.4 5.5 5.4 Units V Conditions VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA (Note 5) VIN = VIL or VIH 4.5 3.70 5.5 4.70 4.5 0.1 5.5 0.1 V IOH −24 mA V IOUT = 50 µA (Note 5) VIN = VIL or VIH 4.5 0.50 5.5 0.50 V IOL 5.5 ± 1.0 µA VI = VCC, GND Maximum 5.5 ± 5.0 µA VI = VIL, VIH VO = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 5.5 80.0 µA VIN = VCC TRI-STATE Current ICCT Maximum ICC/Input IOLD IOHD (Note 6) Minimum Dynamic Output Current ICC Maximum Quiescent Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 24 mA 24 mA Leakage Current IOZ −24 mA AC Electrical Characteristics 54AC TA = −55˚C to +125˚C CL = 50 pF VCC Symbol fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter (V) (Note 8) Min Maximum Clock 3.3 60 Frequency 5.0 95 MHz 3.3 3.0 16.5 CP to On 5.0 3.0 12.0 Propagation Delay 3.3 3.0 15.0 CP to On 5.0 3.0 11.0 Output Enable Time 3.3 1.0 14.0 5.0 1.5 10.5 3.3 1.0 14.0 5.0 1.5 10.5 3.3 1.0 16.0 5.0 1.5 12.5 3.3 1.0 13.0 5.0 1.5 10.5 Output Disable Time Output Disable Time No. Max Propagation Delay Output Enable Time Fig. Units ns ns ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54AC TA = −55˚C VCC Symbol Parameter (V) Fig. to +125˚C CL = 50 pF (Note 9) Units No. Guaranteed Minimum ts th tw Setup Time, HIGH or LOW 3.3 6.5 Dn to CP 5.0 5.0 Hold Time, HIGH or LOW 3.3 1.0 Dn to CP 5.0 1.5 CP Pulse Width, 3.3 6.5 HIGH or LOW 5.0 5.0 ns ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 10) Min fmax Maximum Clock Units Max 5.0 70 MHz 5.0 1.5 12.0 ns 5.0 1.5 11.5 ns 5.0 1.5 11.5 ns Frequency tPLH Propagation Delay CP to On tPHL Propagation Delay CP to On tPZH Output Enable Time 5 www.national.com AC Electrical Characteristics (Continued) 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 10) Units Min Max tPZL Output Enable Time 5.0 1.5 11.5 ns tPHZ Output Disable Time 5.0 1.5 13.0 ns tPLZ Output Disable Time 5.0 1.5 11.0 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 5.5 ns 5.0 1.5 ns 5.0 5.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP tw CP Pulse Width, HIGH or LOW Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 40 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20 Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 7 www.national.com 54AC374 • 54ACT374 Octal D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20 Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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