54ACT823 9-Bit D Flip-Flop General Description The ACT823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACT823 offers noninverting outputs and is fully compatible with AMD’s Am29823. n n n n TRI-STATE outputs for bus interfacing Inputs and outputs are on opposite sides ACT823 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 5962-9161001 Features n Outputs source/sink 24 mA Ordering Code Order Number Package Number Package Description 54ACT823DMQB J24A 24-Lead Ceramic Dual-in-line 54ACT823FMQB W24C 24-Lead Cerpack 54ACT823LMQB E28A 28-Lead Ceramic Leadless Chip Carrier, Type C Logic Symbols IEEE/IEC DS100253-1 DS100253-2 Pin Names Description D0–D8 Data Inputs O0–O8 Data Outputs OE Output Enable CLR Clear CP Clock Input EN Clock Enable FACT™ is a trademark of Fairchild Semiconductor Corporation. TRI-STATE™ is a trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100253 www.national.com 54ACT823 9-Bit D Flip-Flop August 1998 Connection Diagrams Pin Assignment for DIP and Cerpack DS100253-3 Pin Assignment for LCC DS100253-4 www.national.com 2 Functional Description able pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. The ACT823 consists of nine D-type edge-triggered flip-flops. These have TRI-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output En- When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs Internal Output Q O Function OE CLR EN CP H X L N L L Z High Z H X L N H H Z High Z H L X X X L Z Clear L L X X X L L Clear H H H X X NC Z Hold L H H X X NC NC Hold H H L N L L Z Load H H L N H H Z Load L H L N L L L Load L H L N H H H Load D H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change Logic Diagram DS100253-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 175˚C Recommended Operating Conditions −0.5V to 7.0V Supply Voltage (VCC) ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (∆V/∆t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Electrical Characteristics Symbol VIH VIL Parameter VCC TA = (V) −55˚C to +125˚C Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Units Conditions V VOUT = 0.1V V or VCC −0.1V VOUT = 0.1V Maximum Low Level 4.5 0.8 Input Voltage 4.5 0.8 VOH Minimum High Level Output Voltage 4.5 3.7 VOL Maximum Low Level Output Voltage 4.5 0.5 IIN Maximum Input Leakage Current 5.5 ± 1.0 µA VI = VCC, GND IOZ Maximum TRI-STATE 5.5 ± 10.0 µA VI = VIL, VIH VO = VCC, GND or VCC −0.1V IOH = −24 mA V IOL = 24 mA V Current ICCT Maximum ICC/Input 5.5 1.6 mA IOLD 5.5 50 mA VI = VCC −2.1V VOLD = 1.65V Max IOHD (Note 3) Minimum Dynamic Output Current 5.5 −50 mA VOHD = 3.85V Min ICC Maximum Quiescent 5.5 160 µA VIN = VCC Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics Symbol Parameter TA = −55˚C to +125˚C CL = 50 pF VCC (V) (Note 4) Min fmax Maximum Clock 5.0 95 5.0 1.0 Units Max MHz Frequency tPLH Propagation Delay CP to On www.national.com 4 12.0 ns AC Electrical Characteristics Symbol tPHL Parameter Propagation Delay (Continued) TA = −55˚C to +125˚C CL = 50 pF VCC (V) (Note 4) Units Min Max 5.0 1.0 12.0 ns 5.0 1.0 18.0 ns 5.0 1.0 11.5 ns 5.0 1.0 12.0 ns 5.0 1.0 13.5 ns 5.0 1.0 12.0 ns CP to On tPHL Propagation Delay CLR to On tPZH Output Enable Time OE to On tPZL Output Enable Time OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On Note 4: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol Parameter VCC(V) (Note 5) TA = −55˚C to +125˚C CL = 50 pF Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 4.0 ns 5.0 3.0 ns 5.0 4.0 ns 5.0 3.0 ns 5.0 6.0 ns D to CP th Hold Time, HIGH or LOW Dn to CP ts Setup Time, HIGH or LOW EN to CP th Hold Time, HIGH or LOW EN to CP tw CP Pulse Width HIGH or LOW tw CLR Pulse Width, LOW 5.0 7.5 ns trec CLR to CP 5.0 4.5 ns Recovery Time Note 5: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com Capacitance Max Units CIN Symbol Input Capacitance 4.5 pF Conditions VCC = OPEN CPD Power Dissipation Capacitance 4.4 pF VCC = 5.0V www.national.com Parameter 6 Physical Dimensions inches (millimeters) unless otherwise noted 24 Lead Ceramic Dual-in-line Package Number J24A 24 Lead Cerpack Package Number W24C 7 www.national.com 54ACT823 9-Bit D Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28 Lead Ceramic Leadless Chip Carrier Package Number E28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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