54AC74 • 54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features n n n n ICC reduced by 50% Output source/sink 24 mA ’ACT74 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC74: 5962-88520 — ’ACT74: 5962-87525 Logic Symbols DS100266-2 DS100266-1 Pin Names IEEE/IEC Description D1, D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs DS100266-3 FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100266 www.national.com 54AC74 • 54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop August 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100266-4 DS100266-5 Truth Table (Each Half) Inputs Outputs SD CD CP D Q L H X X H Q L H L X X L H H L L X X H H H N H H L H H N L L H H H L X Q0 Q0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock Logic Diagram DS100266-6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High 3.0 2.1 Level Input 4.5 3.15 Voltage 5.5 3.85 Maximum Low 3.0 0.9 Level Input 4.5 1.35 Voltage 5.5 1.65 Minimum High 3.0 2.9 Level Output 4.5 4.4 Voltage 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low 3.0 0.1 Level Output 4.5 0.1 Voltage 5.5 0.1 −12 mA V IOH −24 mA −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IIN Maximum Input 3.0 0.5 4.5 0.5 5.5 0.5 5.5 ± 1.0 12 mA V µA IOL 24 mA 24 mA VI = VCC, GND Leakage Current 3 www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter (Continued) VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits IOLD IOHD (Note 3) Minimum Dynamic Output Current ICC Maximum Quiescent 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 5.5 40.0 µA VIN = VCC Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH VOL IIN Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Input 4.5 2.0 5.5 2.0 4.5 0.8 5.5 0.8 4.5 4.4 5.5 5.4 V VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA (Note 5) VIN = VIL or VIH 4.5 3.70 5.5 4.70 4.5 0.1 5.5 0.1 V IOH −24 mA −24 mA V IOUT = 50 µA (Note 5) VIN = VIL or VIH 4.5 0.50 5.5 0.50 V IOL 24 mA 5.5 ± 1.0 µA 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 5.5 40.0 µA VIN = VCC Leakage Current ICCT Maximum ICC/Input IOLD IOHD (Note 6) Minimum Dynamic Output Current ICC Maximum Quiescent Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 AC Electrical Characteristics VCC Symbol Parameter (V) (Note 8) 54AC TA = −55˚C to +125˚C CL = 50 pF Min fmax tPLH tPHL tPLH tPHL Maximum Clock 3.3 70 Frequency 5.0 95 Units Fig. No. Max MHz Propagation Delay 3.3 1.0 13.0 CDn or SDn to Qn or Qn 5.0 1.0 9.5 Propagation Delay 3.3 1.0 14.0 CDn or SDn to Qn or Qn 5.0 1.0 10.5 Propagation Delay 3.3 1.0 17.5 CPn to Qn or Qn 5.0 1.0 12.0 Propagation Delay 3.3 1.0 13.5 CPn to Qn or Qn 5.0 1.0 10.0 ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol ts th tw trec Parameter (V) 54AC TA = −55˚C to +125˚C CL = 50 pF (Note 9) Guaranteed Limits VCC Set-up Time, HIGH or LOW 3.3 5.0 Dn to CPn 5.0 4.0 Hold Time, HIGH or LOW 3.3 0.5 Dn to CPn 5.0 0.5 CPn or CDn or SDn 3.3 8.0 Pulse Width 5.0 5.5 Recovery Time 3.3 0.5 CDn or SDn to CP 5.0 0.5 Units Fig. No. ns ns ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 10) Min fmax Maximum Clock Units Max 5.0 85 MHz 5.0 1.0 11.5 ns 5.0 1.0 12.5 ns 5.0 1.0 14.0 ns 5.0 1.0 12.0 ns Frequency tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn 5 www.national.com AC Electrical Characteristics (Continued) Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol Parameter 54ACT TA = VCC (V) Set-up Time, HIGH or LOW Guaranteed Limits 5.0 4.0 ns 5.0 1.0 ns 5.0 7.0 ns 5.0 0.5 ns Dn to CPn th Hold Time, HIGH or LOW Dn to CPn tw CPn or CDn or SDn Pulse Width trec Recovery Time CDn or SDn to CP Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 35.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V Fig. No. pF (Note 11) ts Units −55˚C CL = 50 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 14-Lead Ceramic Dual-In-Line Package (D) NS Package Number J14A 7 www.national.com 54AC74 • 54ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Ceramic Flatpak (F) NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.